CN107567691A

CN107567691A - Transmitter and its dividing method

Info

Publication number: CN107567691A
Application number: CN201680025606.8A
Authority: CN
Inventors: 郑鸿实; 金庆中; 明世澔
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2015-03-02
Filing date: 2016-03-02
Publication date: 2018-01-09
Anticipated expiration: 2036-03-02
Also published as: CA2978212A1; KR101800417B1; CN107567691B; KR101898696B1; KR20170130323A; KR20190042520A; KR20160106477A; MX2017011152A; CA2978212C; KR102114463B1; KR101970824B1; KR20180103793A

Abstract

Provide a kind of transmitter.The transmitter includes：Dispenser, it is configured as that information bit is divided into multiple pieces based on a preset reference value in multiple preset reference values；External encoder, it is configured as encoding to produce the first Parity Check Bits the multiple piece each block；And low-density checksum (LDPC) encoder, it is configured as encoding each block in the multiple piece and the first Parity Check Bits the LDPC code word for including the second Parity Check Bits with generation, wherein, one preset reference value in the multiple preset reference value is determined according at least one of following：For the code check encoded to each block in the multiple piece and the first Parity Check Bits and whether repetition is performed at least a portion LDPC code word in LDPC code word.

Description

Transmitter and its dividing method

Technical field

The apparatus and method consistent with exemplary embodiment are related to a kind of transmitter and its dividing method, more specifically, relating to A kind of and transmitter and its dividing method that signaling can be split.

Background technology

Broadcast communication services in the society of the Information of 21 century just add into digitlization, multichannel, bandwidth Wide and high quality epoch.Specifically, it is widely available due to digital TV in high resolution (TV) and portable broadcaster, because The demand growth of support of this digital broadcast service for various receiving side signal cases.

According to this demand, the various standards of standard group setting meet the various services of the needs of user to provide.Therefore, need Want a kind of to be used to provide a user the method preferably serviced with more excellent performance.

The content of the invention

Technical problem

The exemplary embodiment of inventive concept can overcome the sender unit of correlation technique and lacking for receiver and its method Point.However, do not require that these embodiments overcome the shortcomings that such or these embodiments can not overcome such shortcoming.

Exemplary embodiment offer is a kind of split so that the quantity for the information bit being partitioned into information bit Equal to or less than the transmitter and its dividing method of certain number.

Technical scheme

According to the one side of exemplary embodiment, there is provided a kind of transmitter, it may include：Dispenser, it is configured as being based on Information bit is divided into multiple pieces by a preset reference value in multiple preset reference values；External encoder, is configured as pair Each block in the multiple piece is encoded to produce the first Parity Check Bits；And low-density checksum (LDPC) Encoder, be configured as encoding each block in the multiple piece and the first Parity Check Bits includes the to produce The LDPC code word of two Parity Check Bits, wherein, one preset reference value in the multiple preset reference value according to Descend at least one and be determined：For the code encoded to each block in the multiple piece and the first Parity Check Bits Rate and whether repetition is performed at least a portion LDPC code word in LDPC code word.It is each in the multiple preset reference value Individual preset reference value can be according at least one in the code check and repetition situation as each root tuber in the multiple piece The individual and threshold value of the maximum quantity of bit that can have.

According to the one side of another exemplary embodiment, there is provided a kind of dividing method of transmitter, it may include：Based on more Information bit is divided into multiple pieces by a preset reference value in individual preset reference value；To each block in the multiple piece Encoded to produce the first Parity Check Bits；And to each block and the first Parity Check Bits in the multiple piece Being encoded includes the code word of the second Parity Check Bits with generation, wherein, it is one in the multiple preset reference value Preset reference value is determined according at least one of following：For to each block in the multiple piece and the first even-odd check The repetition situation of at least a portion code word in code check and code word that bit is encoded.

Beneficial effect

As described above, according to various exemplary embodiments, information bit can be divided into equal to or less than certain number with full Foot carries out encoding required performance to information bit.

Brief description of the drawings

Above and/or other aspect of inventive concept is described below with reference to accompanying drawings, wherein：

Fig. 1 is the block diagram for describing the configuration of the transmitter according to exemplary embodiment；

Fig. 2 is the diagram for describing the dividing method according to exemplary embodiment；

Fig. 3 and Fig. 4 is the diagram for describing the parity matrix according to exemplary embodiment；

Fig. 5 is for describing the diagram for being used to set the method for preset reference value according to exemplary embodiment；

Fig. 6 is the diagram for describing the dividing method according to exemplary embodiment；

Fig. 7 is the diagram for describing the frame structure according to exemplary embodiment；

Fig. 8 and Fig. 9 is the block diagram for describing the detailed configuration of the transmitter according to exemplary embodiment；

Figure 10 to Figure 23 is for describing the diagram for being used to handle the method for signaling according to exemplary embodiment；

Figure 24 and Figure 25 is the block diagram for describing the configuration of the receiver according to exemplary embodiment；

Figure 26 and Figure 27 is carried out for log-likelihood ratio (LLR) value to receiver described according to exemplary embodiment The diagram of the example of combination；

Figure 28 is the diagram for showing the example according to the offer of the exemplary embodiment information relevant with the length of L1 signalings；

Figure 29 is the flow chart for describing the dividing method according to exemplary embodiment.

For realizing the optimal mode of the present invention

Embodiment

Hereinafter, the exemplary embodiment of present inventive concept is more fully described with reference to the accompanying drawings.

Fig. 1 is the block diagram for describing the configuration of the transmitter according to exemplary embodiment.

Reference picture 1, transmitter 100 include dispenser 110, external encoder 120 and low-density checksum (LDPC) and compiled Code device 130.

The information bit that dispenser 110 will enter into transmitter 100 is divided into multiple pieces (or bit blocks).

Here, information bit can be signaling (being alternatively referred to as " signaling bit " or " signaling information ").Information bit can The data or service data (example sent from transmitter 100 are received and handled including receiver 200 (as shown in Figure 24 or Figure 25) Such as, broadcast data) needed for information.

Hereinafter, for convenience of explanation, will be that the situation of signaling is described to information bit.

In detail, transmitter 100 can perform external encode to produce parity bits (or Parity Check Bits) to signaling, and To performing in-line coding including signaling and by the bit by external encode of Parity Check Bits caused by external encode.

Here, external encode is the encoding operation performed before the in-line coding in concatenated coding operation, and be can be used Various encoding schemes, such as, Bose, Chaudhuri, Hocquenghem (BCH) coding and/or CRC (CRC) are compiled Code.In this case, the internal code as the in-line coding encoded for such as LDPC, LDPC code can be used.

Encoded for LDPC, it is necessary to depending on code check and the certain amount of LDPC information bits of code length.However, work as signaling When the quantity of bit changes, the LDPC information bits for LDPC codings are likely larger than by the quantity of the bit of external encode Quantity.

Therefore, when the quantity of signaling bit is more than preset value, signaling can be divided into multiple pieces to avoid by dispenser 110 It is more than the quantity of required LDPC information bits by the quantity of the bit of external encode.

Hereinafter, the method detailed for being split to signaling is described reference picture 2.

As described above, when the quantity of signaling bit changes, segmentation is needed in some cases and signaling is encoded to It is sent to receiver 200 so that need at least one forward error correction (FEC) frame to send all signaling bits.Here, Fec frame can represent that signaling is encoded as the form added with Parity Check Bits.

In detail, when signaling is not divided, signaling is encoded to produce a fec frame by external encode and LDPC, so as to A fec frame is needed to be used for signalling.However, when signaling is divided at least two, these signaling being partitioned into quilts External encode and LDPC codings are to produce at least two fec frames, therefore, it is necessary at least two fec frames are used for signalling.

Therefore, dispenser 110 calculates the quantity N of the fec frame for signaling based on equation 1 below or 2_{L1D_FECFRAME}。

In above-mentioned equation 1 and 2,Represent the smallest positive integral equal to or more than x.In addition, K_{L1D_ex_pad}Represent except filling out The length (that is, the quantity of signaling bit) for the signaling filled outside bit.

K_segRepresent the threshold value limited for segmentation, and the number of the bit for the signaling (that is, the fragment of signaling) being partitioned into Amount is no more than K_seg。

In this case, K_segMultiple preset reference values can be arranged to.

Here, according to LDPC code rate and the repetition of bit can whether be performed to determine multiple preset values.For example, K_segCan quilt It is arranged to 2352,3072 or 6312.Repeat to represent by Parity Check Bits (that is, LDPC even-odd checks caused by LDPC codings Bit) repeated in LDPC code word.When repeating to be performed, have the LDPC code word that repeats can be by LDPC information bits, logical Cross Parity Check Bits caused by LDPC codings and the Parity Check Bits repeated are formed.Aforementioned exemplary describes only LDPC odd evens Check bit is repeated, but at least another part of LDPC code word bit can also be repeated.

Therefore, dispenser 110 may be selected the preset reference values based on selection in the lump of multiple preset reference values signaling entered Row segmentation.That is, dispenser 110 can calculate the quantity of the fec frame for signaling based on the preset reference value of selection N_{L1D_FECFRAME}。

When LDPC code rate is that 3/15 and LDPC Parity Check Bits are repeated, dispenser 110 can be based on K_seg=2352 Signaling is split.

When LDPC code rate is that 3/15 and LDPC Parity Check Bits are not repeated, dispenser 110 can be based on K_seg= 3072 pairs of signalings are split.

When code check is that 6/15 and LDPC Parity Check Bits are not repeated, dispenser 110 can be based on K_seg=6312 pairs Signaling is split.

Meanwhile the pattern of the processing signaling of transmitter 100 can be pre-arranged.That is, for splitting to signaling K_segValue, LDPC code code check, whether perform repetition etc. and can be pre-arranged.

In addition, dispenser 110 calculates the quantity (or length of filling field) of filling bit.In detail, dispenser 110 The quantity K of the filling bit for signaling can be calculated based on equation 3 below_{L1D_PAD}。

In addition, K can be used in dispenser 110_{L1D_PAD}Zero bit bit of 0 value (that is, have) of quantity fills filling word Section.Therefore, K_{L1D_PAD}Individual zero bit can be added to signaling, so as to which as shown in Figure 2, all signalings can be by signaling and packing ratio Special-shaped into.

So, the quantity of filling bit is calculated and zero bit with the quantity of calculating as many is filled into filling word Section, therefore signaling (that is, multiple signaling blocks) can be formed by the bit of identical quantity.

Next, dispenser 110 can calculate the total length K for all signalings for including filling bit based on equation 4 below_L1D。

K_L1D=K_{L1D_ex_pad}+K_{L1D_PAD} …(4)

That is, dispenser 110 can sum to calculate including filling out to the quantity of signaling bit and the quantity of filling bit Fill the total length of all signalings of bit.

In addition, dispenser 110, which can be based on equation 5 below, calculates N_{L1D_FECFRAME}In each signaling block in individual signaling block The quantity K of signaling bit_sig。

K_sig=K_L1D/N_{L1D_FECFRAME} …(5)

Next, dispenser 110 can be based on K_sigSignaling is split.In detail, as shown in Figure 2, dispenser 110 Signaling can be divided into and K_sigAmount of bits by signaling as many to be divided into N_{L1D_FECFRAME}Individual block.

In detail, because zero bit is disposed in the afterbody of signaling, therefore signaling is according to K_sigIndividual amount of bits is continuously divided Cut to form first piece to (N_{L1D_FECFRAME}- 1) block.In addition, in signaling according to K_sigAfter individual amount of bits is successively divided Remaining signaling moiety forms N together with filling bit_{L1D_FECFRAME}Block.

So, dispenser 110 can be based on one of multiple preset reference values and signaling is divided into multiple pieces.

That is, dispenser 110 can be based on K_seg=2352, K_seg=3072 and K_segOne of=6132 calculate N_{L1D_FECFRAME}, based on N_{L1D_FECFRAME}Calculate K_sig, and signaling is divided into N_{L1D_FECFRAME}Individual block so that each block is by K_sigIt is individual Bit is formed.

External encoder 120 is encoded to multiple pieces to produce parity bits (or Parity Check Bits).In this feelings Under condition, external encoder 120 can be encoded to multiple pieces to produce even-odd check corresponding with the multiple piece respectively respectively Bit.

For example, external encoder 120 can be to by K_sigEach in the block that individual bit is formed performs external encode to produce M_outerIndividual Parity Check Bits, and Parity Check Bits are added to and form the bit of each block to export by N_outer(=K_sig+ M_outer) bit by external encode that is formed of individual bit.

However, for convenience of explanation, external encode will be retouched under the hypothesis for performing external encode by BCH code below State.

That is, Bose-Chaudhuri-Hocquenghem Code device 120 multiple pieces can be performed respectively coding (that is, Bose-Chaudhuri-Hocquenghem Code) with produce respectively with institute State multiple pieces of corresponding Parity Check Bits, i.e. BCH Parity Check Bits (or BCH parity bits).

For example, Bose-Chaudhuri-Hocquenghem Code device 120 can be systematically to by K_sigThe block that individual bit is formed is encoded to produce M_outer Individual BCH Parity Check Bits, and BCH Parity Check Bits are added to and form the bit of each block to export by N_outer(=K_sig +M_outer) bit by Bose-Chaudhuri-Hocquenghem Code that is formed of individual bit.Here, M_outer=168.

LDPC encoder 130 performs coding (that is, LDPC codings) to multiple pieces and Parity Check Bits to produce odd even school Test bit, i.e. LDPC Parity Check Bits.That is, LDPC encoder 130 can include to each block in multiple pieces It is corresponding with each block in multiple pieces to produce that the bit by Bose-Chaudhuri-Hocquenghem Code of BCH Parity Check Bits performs LDPC codings LDPC Parity Check Bits.

Encoded for LDPC, it is necessary to depending on code check and the certain amount of LDPC information bits of code length.Therefore, when passing through To signaling or the signaling being partitioned into execution Bose-Chaudhuri-Hocquenghem Code, the quantity of the caused bit by Bose-Chaudhuri-Hocquenghem Code is less than required LDPC During the quantity of information bit, transmitter 100 can fill appropriate number of zero bit (that is, the bit with 0 value) with needed for acquisition LDPC information bits quantity.Therefore, LDPC information bits be may make up by the bit of Bose-Chaudhuri-Hocquenghem Code and zero bit of filling. Here, the quantity K for the LDPC LDPC information bits encoded_ldpcIt is 3240 or 6480.

For example, as the quantity N of the bit by Bose-Chaudhuri-Hocquenghem Code_outer(=K_sig+M_outer) it is less than the LDPC information ratio of LDPC code Special quantity K_ldpcWhen, transmitter 100 can be by K_ldpc-N_outerIndividual zero bit padding is into some of LDPC information bits with generation By K_ldpcThe LDPC information bits that individual bit is formed.Therefore, K_ldpcIndividual LDPC information bits can be by N_outerIt is individual by Bose-Chaudhuri-Hocquenghem Code Bit and K_ldpc-N_outerIndividual zero bit is formed.

Here, the quantity K of the LDPC information bits of LDPC code_ldpcCan be 3240 or 6480.

Because zero bit of filling is to obtain the bit needed for the certain amount of bit for being used for LDPC codings, therefore fill Zero bit be removed after by LDPC codings, be not delivered to receiver 200 so as to these zero bits.So, zero is filled The processing that zero bit of filling is not sent to receiver 200 then simultaneously by the processing of bit or zero bit of filling is referred to alternatively as contracting Subtract.In this case, zero bit of filling is referred to alternatively as reducing bit (or the bit being contracted by).

However, when by performing Bose-Chaudhuri-Hocquenghem Code to signaling or the signaling being partitioned into and the caused bit by Bose-Chaudhuri-Hocquenghem Code When quantity is equal to the quantity of required LDPC information bits, transmitter 100 can be not filled with zero bit and LDPC information bits can Only by being formed by the bit of Bose-Chaudhuri-Hocquenghem Code, without zero bit.

Meanwhile aforementioned exemplary describes and performs Bose-Chaudhuri-Hocquenghem Code to signaling.Here, BCH code is only the example of foreign key.Also It is to say, also various codes (such as, BCH code and/or CRC code) can be used to encode signaling for transmitter 100.

In addition, aforementioned exemplary describes information bit by external encode, this is only an example.That is, information ratio Spy can not be formed LDPC information bits or only information bit may make up LDPC by external encode together with zero bit of filling Information bit and be not filled.

Aforementioned exemplary describes zero bit that will be contracted by and is filled, and this is only an example.That is, due to zero Bit be with by the bit and being filled of 200 default value of transmitter 100 and receiver be only used for together with including will by with The information bit for being sent to the information of receiver 200 afterwards forms LDPC information bits together, thus substitute zero bit have by Transmitter 100 and the bit of the default another value (for example, 1) of receiver 200 can be filled to be reduced.

LDPC encoder 130 can be systematically encoded to LDPC information bits to produce LDPC Parity Check Bits, And export the LDPC code word (or bit by LDPC codings) formed by LDPC information bits and LDPC Parity Check Bits. That is LDPC code is systematic code, therefore, LDPC code word by the LDPC information bits before being encoded by LDPC and can pass through LDPC Parity Check Bits caused by LDPC codings are formed.

For example, LDPC encoder 130 can be to K_ldpcIndividual LDPC information bitsLDPC is performed to compile Code is to produce N_{ldpc_parity}Individual LDPC Parity Check Bits And export by N_inner(= K_ldpc+N_{ldpc_parity}) the LDPC code word that is formed of individual bit

In this case, LDPC encoder 130 can be held with various code checks to input bit (that is, LDPC information bits) Row LDPC is encoded to produce the LDPC code word with predetermined length.

For example, LDPC encoder 130 3240 LDPC information bits can be performed with 3/15 code check LDPC codings with Produce the LDPC code word formed by 16200 bits.As another example, LDPC encoder 130 can be with 6/15 code check pair 6480 LDPC information bits perform LDPC codings to produce the LDPC code word formed by 16200 bits.

Meanwhile the processing for performing LDPC codings is to produce LDPC code word to meet HC^T=0 processing, therefore, LDPC are compiled Parity matrix can be used to perform LDPC codings in code device 130.Here, H represents parity matrix, and C represents LDPC code word.

Hereinafter, the structure of the parity matrix according to various exemplary embodiments is described with reference to the accompanying drawings.Strange In even parity check matrix, the element of the part in addition to 1 is 0.

As an example, structure as shown in Figure 3 can be had according to the parity matrix of exemplary embodiment.

Reference picture 3, parity matrix 20 can be made up of five sub- matrix As, B, C, Z and D.Hereinafter, in order to describe The structure of parity matrix 20, each matrix structure will be described.

Submatrix A is formed by K row and g row, and submatrix C is formed by K+g row and N-K-g row.Here, K (or K_ldpc) represent the length of LDPC information bits, N (or N_inner) represent LDPC code word length.

In addition, in submatrix A and submatrix C, when the length of LDPC code word is 16200 and code check is 3/15, The index of 1 row being located at can be limited based on table 1 in the 0th row in i-th row group.The quantity for belonging to the row of same row group can be with It is 360.

[table 1]

Hereinafter, table 1 will be see, for example the position of 1 row being located in submatrix A and submatrix C is described in detail (alternatively, referred to as " index " or " index value ").

When the length of LDPC code word is 16200 and code check is 3/15, the coding parameter based on parity matrix 200 M₁, coding parameter M₂, coding parameter Q₁And coding parameter Q₂It is 1080,11880,3 and 33 respectively.

Here, Q₁Represent size of the row by cyclic shift for belonging to same row group in submatrix A, Q₂Represent to belong in submatrix C In same row group row by the size of cyclic shift.

In addition, Q₁=M₁/ L, Q₂=M₂/ L, M₁=g, M₂=N-K-g, L represent to arrange in submatrix A and submatrix C respectively Pattern repeat interval, i.e. belong to the quantity (for example, 360) of the row of same row group.

The index of 1 row being located at can be based respectively on M in submatrix A and submatrix C₁Value determines.

For example, in table 1 more than, due to M₁=1080, therefore 1 institute in the 0th row of the i-th row group in submatrix A The position for the row being located at can be based on more than table 1 index value among the value less than 1080 determine, i-th in submatrix C The position of 1 row being located at can be determined in 0th row of row group.

Specifically, sequence corresponding with the 0th row group is " 8 372 841 4,522 5,253 7430 in the table 1 more than 8542 9822 10550 11896 11988”.Therefore, in the 0th row of the 0th row group in submatrix A, 1 can be respectively positioned at the In 8 rows, the 372nd row and the 841st row, and submatrix C the 0th row group the 0th row in, 1 can be located at respectively the 4522nd row, In 5253rd row, the 7430th row, the 8542nd row, the 9822nd row, the 10550th row, the 11896th row and the 11988th row.

In submatrix A, when 1 position is limited in the 0th row of each row group, 1 position can be by cyclic shift Q₁To be limited to the position of 1 row being located in other row of each row group, and in submatrix C, when 1 position is defined When in the 0th row of each row group, 1 position can be by cyclic shift Q₂It is located at being limited in other row of each row group 1 Row position.

In aforementioned exemplary, in the 0th row of the 0th row group in submatrix A, 1 positioned at eighth row, the 372nd row and the 841 rows.In this case, due to Q₁=3, therefore the index of 1 row being located at can be 11 in the 1st row of the 0th row group (=8+3), 375 (=372+3) and 844 (=841+3), and in the 2nd row of the 0th row group 1 row being located at index Can be 14 (=11+3), 378 (=375+3) and 847 (=844+3).

Submatrix C the 0th row group the 0th row in, 1 positioned at the 4522nd row, the 5253rd row, the 7430th row, the 8542nd row, 9822nd row, the 10550th row, the 11896th row and the 11988th row.In this case, due to Q₂=33, therefore in the 0th row The index of 1 row being located at can be 4555 (=4522+33), 5286 (=5253+33), 7463 (=7430 in 1st row of group + 33), 8575 (=8542+33), 9855 (=9822+33), 10583 (=10550+33), 11929 (=11896+33) and 12021 (=11988+33), and the index of 1 row being located at can be 4588 (=4555+ in the 2nd row of the 0th row group 33), 5319 (=5286+33), 7496 (=7463+33), 8608 (=8575+33), 9888 (=9855+33), 10616 (= 10583+33), 11962 (=11929+33) and 12054 (=12021+33).

According to the program, the position of 1 row being located at can be defined in all row groups in submatrix A and submatrix C.

Submatrix B is dual-diagonal matrix, and submatrix D is unit matrix, and submatrix Z is null matrix.

As a result, as shown in Figure 2 parity matrix 20 structure can by the submatrix A with above structure, Submatrix B, submatrix C, submatrix D and submatrix Z are limited.

Hereinafter, description is performed into LDPC by LDPC encoder 130 based on parity matrix 20 as shown in Figure 3 The method of coding.

LDPC code can be used for block of information S=(s₀,s₁,...,s_K-1) encoded.In this case, in order to produce length Spend for N=K+M₁+M₂LDPC code word Λ=(λ₀,λ₁,...,λ_N-1), the parity block from block of information SCan systematically it be encoded.

As a result, LDPC code word can be

Here, M₁And M₂Sub-parity check matrices corresponding with double diagonal submatrix B and unit submatrix D are represented respectively Size, wherein, M₁=g and M₂=N-K-g.

Calculating the process of Parity Check Bits can be expressed as followsin.Hereinafter, for convenience of explanation, parity matrix 20 situations for being defined as the table 1 of the above will be described as an example.

Step 1) performs initialization and causes λ_i=s_i(i=0,1 ..., K-1), p_j=0 (j=0,1 ..., M₁+M₂-1)。

Step 2) is by first information bit λ₀It is added to the parity bit addresses limited in the 1st row of the table 1 of the above In.

Step 3) is directed to ensuing L-1 information bit λ_m(m=1,2 ..., L-1), by λ_mIt is added to based on following In the parity bit addresses that equation 6 calculates.

In expression formula 6 more than, x is represented and first information bit λ₀The ground of corresponding Parity Check Bits accumulator Location.In addition, Q₁=M₁/ L and Q₂=M₂/L。

In this case, due to the length of LDPC code word be 16200 and code check be 3/15, therefore M₁=1080, M₂= 11880, Q₁=3, Q₂=33, L=360.

Step 4) is given l-th information bit λ due to the parity bit addresses of the 2nd row of table 1 such as above_L, Similar to aforementioned schemes, calculated by the scheme described in step 3) above for ensuing L-1 information bit λ_m The parity bit addresses of (m=L+1, L+2 ..., 2L-1).In this case, x is represented and information bit λ_LIt is corresponding The address of Parity Check Bits accumulator, and can be obtained based on the 2nd row of table 1 above.

The new row of table 1 above is arranged to Parity Check Bits by step 5) for every group of L new information bits The address of accumulator, and therefore repeat aforementioned process.

Step 6) is from code word bits λ₀To λ_K-1After repeating aforementioned process, following equation 7 is sequentially calculated from i=1 Value.

Step 7) calculates Parity Check Bits λ corresponding with double diagonal submatrix B based on following equation 8_KExtremely

λ_K+L×t+s=p_Q1×s+t(0≤S ＜ L, 0≤t ＜ Q₁)...(8)

Step 8) calculates the L new code word ratios for every group based on the new row of table 1 above and the equation 6 of the above Special λ_KExtremelyParity Check Bits accumulator address.

Step 9) is in code word bits λ_KExtremelyAfter being employed, calculated and submatrix D based on following equation 9 Corresponding Parity Check BitsExtremely

λ_K+M1+L×t+s=p_M1+Q2×s+t(0≤s ＜ L, O≤t ＜ Q₂)...(9)

As a result, Parity Check Bits can be calculated by scheme above.However, this is only an example, and And therefore, the scheme for calculating Parity Check Bits based on parity matrix as shown in Figure 2 can be in a variety of ways It is defined.

In this way, LDPC encoder 130 can perform LDPC codings based on table 1 above to produce LDPC code word.

In detail, LDPC encoder 130 can based on more than table 1 with 3/15 code check to 3240 input bits (i.e., LDPC information bits) LDPC codings are performed to produce 12960 LDPC Parity Check Bits, and export by LDPC information bits The LDPC code word formed with LDPC Parity Check Bits.In this case, LDPC code word can be formed by 16200 bits.

As another example, structure as shown in Figure 4 can be had according to the parity matrix of exemplary embodiment.

Reference picture 4, parity matrix 40 are formed by information submatrix 41 and sub-parity check matrices 42, wherein, information Submatrix 41 be with information bit (that is, LDPC information bits) corresponding to submatrix, sub-parity check matrices 42 are and odd even school Test submatrix corresponding to bit (that is, LDPC Parity Check Bits).

Information submatrix 41 includes K_ldpcIndividual row, sub-parity check matrices 42 include N_{ldpc_parity}=N_inner-K_ldpcIndividual row. The quantity of the row of parity matrix 40 is equal to the quantity N of the row of sub-parity check matrices 42_{ldpc_parity}=N_inner-K_ldpc。

In addition, in parity matrix 40, N_innerRepresent the length of LDPC code word, K_ldpcRepresent the length of information bit Degree, N_{ldpc_parity}=N_inner-K_ldpcRepresent the length of Parity Check Bits.

Hereinafter, by the structure of description information submatrix 41 and sub-parity check matrices 42.

Information submatrix 41 is to include K_ldpcIndividual row (that is, the 0th row to (K_ldpc- 1) arrange) matrix, and depend on down The rule in face.

First, the K of configuration information submatrix 41_ldpcEvery M dependent of dead military hero in individual row is in same group, and the sub- square of configuration information The K of battle array 41_ldpcIndividual row, which are divided into, amounts to K_ldpc/ M row group.The row for belonging to same row group have cyclic shift Q each other_ldpc's Relation.That is, Q_ldpcThe row for the row group that can be considered as in the information submatrix for composition parity matrix 40 follow Ring shift parameters value.

Here, M represents the interval (for example, M=360) that the pattern of the row in information submatrix 41 is repeated, Q_ldpcIt is letter Each arranged in breath submatrix 41 by the size of cyclic shift.M is N_innerAnd K_ldpcCommon divisor and be defined such that Q_ldpc= (N_inner-K_ldpc)/M is established.Here, M and Q_ldpcIt is integer, K_ldpc/ M is also integer.M and Q_ldpcCan be according to LDPC code word Length and code check and there are various values.

For example, as M=360, the length N of LDPC code word_innerIt is 16200, code check is 6/15, Q_ldpcCan be 27.

Second, if the i-th (i=0,1 ..., K_ldpc/ M-1) row group the 0th row degree (here, degree positioned at arrange in The quantity of value 1, and the degree for belonging to all row of same column group is identical) it is arranged to D_i, and 1 in the 0th row of the i-th row group The position (or index) for each row being located at is arranged toThe then jth row in the i-th row group In k-th 1 rows being located at indexDetermined based on following equation 10.

In equation 10 more than, k=0,1,2 ..., D_i-1；I=0,1 ..., K_ldpc/M-1；J=1,2 ..., M-1.

Meanwhile the equation 10 of the above may be expressed as such as following equation 11.

In equation 11 more than, k=0,1,2 ..., D_i-1；I=0,1 ..., K_ldpc/M-1；J=1,2 ..., M-1. In equation 11 more than, due to j=1,2 ..., M-1, therefore (j mod M) can be considered as j.

In these equatioies,Represent the index of k-th 1 rows being located in the jth row in the i-th row group, N_inner Represent the length of LDPC code word, K_ldpcRepresent the length of information bit, D_iThe degree for belonging to the row of the i-th row group is represented, M represents to belong to The quantity of the row of one row group, and Q_ldpcExpression is each arranged by the size of cyclic shift.

As a result, the equation with reference to more than, ifValue is known, then kth during the jth in the i-th row group arranges The index of individual 1 row being located atCan be known.Therefore, when being located at for k-th 1 in the 0th row in each row group When capable index value is stored, in (that is, information of parity matrix 40 of parity matrix 40 of the structure with Fig. 4 Matrix 41) in the positions of 1 columns and rows being located at can be verified.

According to aforementioned rule, the degree (degree) of all row for belonging to the i-th row group is D_i.Therefore, according to aforementioned rule, deposit The LDPC code word of the storage information relevant with parity matrix can be briefly expressed as below.

For example, work as N_innerIt is 30, K_ldpcIt is 15, and Q_ldpcWhen being 3,1 is located in the 0th row group of 3 row groups Capable positional information can be represented by the sequence (being referred to alternatively as " position sequence of weight -1 ") of such as following equation 12.

In equation 12 more than,Represent the index of k-th 1 rows being located in the jth row of the i-th row group.

Represent the position of weight -1 of the equation 12 as more than of the index of 1 row being located in the 0th row of each row group Sequence can be more briefly expressed as following table 2.

[table 2]

Table 2 above represents the position for the element that parity matrix intermediate value is 1, and i-th of position sequence of weight -1 is by belonging to The index of 1 row being located at represents in the 0th row of the i-th row group.

The information submatrix 41 of the parity matrix of exemplary embodiment as described above can be based on following table 3 To limit.

Here, table 3 below represent the i-th row group in information submatrix 41 the 0th row in 1 row being located at rope Draw.That is, information submatrix 41 is formed by multiple row groups, wherein, each row group in the multiple row group includes M Row, and 1 position can be limited by following table 3 in the 0th row of each row group in the multiple row group.

For example, as the length N of LDPC code word_innerIt is 16200, code check is 6/15, and when M is 360, in information submatrix The index such as following table 3 of 1 row being located in 0th row of the i-th row group in 41.

[table 3]

According to another exemplary embodiment, index in the table 3 more than in each sequence corresponding with each row group The parity matrix that order is changed is considered as being directed to the odd even of LDPC code with parity matrix identical described above Check matrix is another example of inventive concept.

According to further example embodiment, the even-odd check being changed that puts in order of the sequence of row group in the table 3 of the above Matrix be also regarded as with parity matrix identical parity matrix described above because they have identical algebraically Characteristic, ring feature and degree such as on code figure are distributed.

According to further example embodiment, by Q_ldpcMultiple with the table 3 of the above sequence corresponding with row group it is all Index be added parity matrix be also regarded as with parity matrix identical parity matrix described above because There is identical ring feature and degree to be distributed on code figure for they.Here, it is noted that, when by by Q_ldpcMultiple with it is given The value that sequence is added and obtained is equal to or more than N_inner-K_ldpcWhen, described value needs to be changed to by N_inner-K_ldpcPerform Modular arithmetic and the value obtained, are then employed.

If 1 row being located in the 0th row of the i-th row group in information submatrix 41 as shown in table 3 more than Position be defined, then it can be by cyclic shift Q_ldpc, and therefore in other row of each row group 1 row being located at position Putting to be defined.

For example, as shown in upper table 3, because the 0th corresponding sequence of row of the 0th row group with information submatrix 41 is “27 430 519 828 1897 1943 2513 2600 2640 3310 3415 4266 5044 5100 5328 5483 5928 6,204 6,392 6,416 6,602 7,019 7,415 7,623 8,112 8,485 8,724 8,994 9,445 9667 ", thus In 0th row of the 0th row group in information submatrix 41,1 positioned at the 27th row, the 430th row, the 519th row ....

In this case, due to Q_ldpc=(N_inner-K_ldpc)/M=(16200-6480)/360=27, therefore the 0th The index of 1 row being located at can be 54 (=27+27), 457 (=430+27), 546 (=519+ in 1st row of row group 27) ..., 81 (=54+27), 484 (=457+27), 573 (=546+27) ....

Scheme more than, the index of 1 row being located in all rows of each row group can be limited.

Hereinafter, will describe to be used for the method for performing LDPC based on parity matrix 40 as shown in Figure 4 and encoding.

First, the information bit being encoded is arranged to i₀, i₁...,And from the code of LDPC coding outputs Bit is arranged to c₀, c₁...,

Further, since LDPC code is systematic, therefore it is directed to k (0≤k ＜ K_ldpc- 1), c_kIt is arranged to i_k.Meanwhile its Complementary bit is arranged to

Hereinafter, description is used to calculate Parity Check Bits p_kMethod.

Hereinafter, q (i, j, 0) represents the jth item of the i-th row in the index list in the table 3 more than such as, for 0 ＜ i ＜ 360, q (i, j, l) are arranged to q (i, j, l)=q (i, j, 0)+Q_ldpc×l(mod N_inner-K_ldpc).It is meanwhile all tired Adding can be realized by the addition in galois field (GF) (2).In addition, in table 3 more than, because the length of LDPC code word is 16200 and code check be 6/15, therefore Q_ldpcIt is 27.

Meanwhile when q (i, j, 0) and q (i, j, 1) is defined as above, calculate the process of Parity Check Bits such as Under.

Parity Check Bits are initialized as " 0 " by step 1).That is, it is directed to 0≤k<N_inner-K_ldpc, p_k=0.

Step 2) is directed to 0≤k ＜ K_ldpcAll k values, i and l are arranged toAnd l:=k (mod 360). HereIt is no more than x maximum integer.

Next, for all i, by i_kIt is added to p_q(i,j,l)In.That is, calculate p_q(i,0,l)=p_q(i,0,l)+i_k, p_q(i,1,l)=p_q(i,1,l)+i_k, p_q(i,2,l)=p_q(i,2,l)+i_k..., p_{q(i,w(i)-1,l)}=p_{q(i,w(i)-1,l)}+i_k。

Here, w (i) represents the quantity of the value (element) of the i-th row in the index list such as table 3 above, and represents strange In even parity check matrix with i_k1 quantity in corresponding row.In addition, in table 3 more than, as the jth item of the i-th row q (i, j, 0) be Parity Check Bits index, and represent in parity matrix with i_kThe position of 1 row being located in corresponding row Put.

In detail, in the table 3 more than, the q (i, j, 0) as the jth item of the i-th row is represented in the odd even school of LDPC code Test the position of 1 row being located in first (i.e. the 0th) row of the i-th row group in matrix.

Q (i, j, 0) can also be considered as being realized for being directed to all i by i according to permission real equipment_kIt is added to p_q(i,j,l) In scheme the index of Parity Check Bits that is generated by LDPC codings of method, and when another coding method is implemented When can also be considered as another form of index.However, this is only an example, and therefore, whatsoever encoding scheme quilt Using it is it will be evident that wherein, LDPC coding results can be from the odd even school of LDPC code to obtain the result being equal with LDPC coding results Matrix acquisition is tested, wherein, parity matrix can be substantially based on q (i, j, the 0) values of the table 3 of the above and produce.

Step 3) passes through for meeting 0<k<N_inner-K_ldpcAll k calculate p_k=p_k+p_k-1To calculate Parity Check Bits p_k。

Correspondingly, all coded-bit c can be obtained₀, c₁...,

As a result, Parity Check Bits can be calculated by scheme above.However, this is only an example, and And therefore, for based on parity matrix as shown in Figure 4 come calculate the scheme of Parity Check Bits can be with various sides Formula is defined.

In this way, LDPC encoder 130 can perform LDPC codings to produce LDPC code word based on table 3 above.

In detail, LDPC encoder 130 can based on more than table 3 with 6/15 code check to 6480 input bits (i.e., LDPC information bits) LDPC codings are performed, to produce 9720 LDPC Parity Check Bits, and export LDPC Parity Check Bits And the LDPC code word formed by LDPC Parity Check Bits.In this case, LDPC code word can compare special-shaped by 16200 Into.

As described above, LDPC encoder 130 can be encoded to produce LDPC with various code checks to LDPC information bits Parity Check Bits.

Specifically, when dispenser 110 is based on K_seg=2352 or K_segDuring=3072 execution segmentation, LDPC encoder 130 can LDPC codings are performed to 3240 LDPC information bits to produce 12960 LDPC odd evens schools with 3/15 code check based on upper table 1 Bit is tested, and exports the LDPC code word that the length formed by LDPC information bits and LDPC Parity Check Bits is 16200.

In addition, when dispenser 110 is based on K_segDuring=6312 execution segmentation, LDPC encoder 130 can be based on upper table 3 with 6/ 15 code check performs LDPC codings to 6480 LDPC information bits to produce 9720 LDPC Parity Check Bits, and export by The LDPC code word that the length that LDPC information bits and LDPC Parity Check Bits are formed is 16200.

However, aforementioned exemplary describes, parity matrix is based on upper table 1 and table 3 is defined, and this is only example.Therefore, Parity matrix can be limited by a variety of schemes.

LDPC code word can be sent to receiver 200 by transmitter 100.

Transmitter 100 can perform repetition and censoring to LDPC code word, and will be by repeating with the LDPC code word of censoring (i.e., The LDPC code word bit of the bit for including repeating in addition to the bit being truncated) it is sent to receiver 200.

First, transmitter 100 is executable repeats.That is, transmitter 100 can be next to the position of LDPC information bits Put at least some bits for the LDPC code word that repetition is formed by LDPC information bits and LDPC Parity Check Bits.

Specifically, transmitter 100 can repeat certain amount of LDPC Parity Check Bits after LDPC information bits. That is transmitter 100 can redundantly add certain amount of LDPC Parity Check Bits after LDPC information bits.Cause This, same bits are by repeating and redundancy, and the bit repeated is located at LDPC information bits in LDPC code word and LDPC is strange Between even parity check bit.

Therefore, because the certain amount of bit in LDPC code word can be repeated and be sent to receiver 200 in addition, therefore Aforementioned operation is referred to alternatively as repeating.In addition, in LDPC code word repeat bit (that is, according to repeat LDPC information bits it The bit being added afterwards) it is referred to alternatively as repetition bits (or the bit repeated).

Meanwhile foregoing repetition can be selectively performed.In detail, when signaling is based on K_seg=2352 are divided and divide When the signaling cut out is encoded with 3/15 code check by LDPC, repetition can be performed.However, when signaling is based on K_seg=3072 and K_seg When=6312 signalings for being divided and being partitioned into are encoded with 3/15 or 6/15 code check by LDPC, repetition can be omitted.

In addition, transmitter 100 can perform censoring.That is, transmitter 100 can be in censoring LDPC Parity Check Bits Some bits.

Here, some in censoring expression LDPC Parity Check Bits are not delivered to receiver 200.In such case Under, transmitter 100 can will be removed the remaining LDPC code word bit left afterwards in the LDPC Parity Check Bits being truncated Receiver 200 is sent to, or only by the remaining bit in LDPC code word in addition to the LDPC Parity Check Bits being truncated It is sent to receiver 200.

Specifically, transmitter 100 can LDPC Parity Check Bits rear portion censoring and certain amount of bit as many Bit.That is, transmitter 100 can be from the last certain amount of bit of LDPC Parity Check Bits censorings.

In this case, because the LDPC code word with repetition is according to LDPC information bits, the LDPC odd evens school repeated Test bit and by LDPC encode caused by the orders of LDPC Parity Check Bits be configured, therefore transmitter 100 can be from passing through Last LDPC Parity Check Bits in LDPC Parity Check Bits caused by LDPC codings play the certain amount of bit of censoring. Therefore, the certain amount of bit to be risen abruptly from the last ratio of LDPC code word can be truncated.

Next, LDPC code word bit can be sent to receiver 200 by transmitter 100, wherein, the LDPC code word bit Be except be added to through repetition and the LDPC code word of censoring (that is, by repeating, the LDPC code word of censoring and reduction (that is, except Outside the bit that is truncated and the bit of reduction according to the LDPC code word bit for repeating to add after bit)) in zero bit Outside by repeating, the LDPC code word bit of censoring and reduction.

In this case, transmitter 100 can be adjusted by QPSK to the LDPC code word by repetition, censoring and reduction The symbol is mapped to the frame for being sent to receiver 200 by system to produce constellation symbols.

Specifically, when signaling is based on K_seg=2352 signalings for being divided and being partitioned into are compiled with 3/15 code check by LDPC During code, transmitter 100 can be modulated by QPSK to the LDPC code word by repetition, censoring and reduction.

However, when repeat be omitted when, transmitter 100 can by QPSK, 16- quadrature amplitude modulation (QAM), 64-QAM or 256-QAM is modulated to produce constellation symbols to the LDPC code word by censoring and reduction, and the symbol is mapped into use In the frame for being sent to receiver 200.

In detail, when signaling is based on K_seg=3072 signalings for being divided and being partitioned into are compiled with 3/15 code check by LDPC During code, transmitter 100 can be modulated by QPSK to the LDPC code word by censoring and reduction.

In addition, when signaling is based on K_seg=6312 signalings for being divided and being partitioned into are encoded with 6/15 code check by LDPC When, transmitter 100 can be by 16-QAM, 64-QAM or 256-QAM to being modulated by censoring and the LDPC code word of reduction.

Meanwhile in these cases, when signaling is modulated by QPSK, 16-QAM, 64-QAM and 256-QAM respectively, Order of modulation η_MODCan be 2,4,6 and 8.

Because signaling includes the signaling information for data, therefore transmitter 100 can be carried out data with being used for data The signaling of processing is mapped to frame together, and the data of mapping are sent into receiver 200.

In detail, transmitter 100 can be handled data according to specified scheme to produce constellation symbols, and will be produced Constellation symbols be mapped to the data symbol of each frame.In addition, transmitter 100 can will be mapped to each data be directed to data Protocol mapping to corresponding frame leading (preamble).For example, transmitter 100 can be by the data for being mapped to the i-th frame The protocol mapping including signaling information to the i-th frame.

As a result, the signaling obtained from frame can be used to receive data from the frame and data are carried out in receiver 200 Processing.

Meanwhile according to exemplary embodiment, it is provided below on by K_segValue is arranged to 2352,3072 or 6312 description.

As described above, signaling is divided and by K_sigThe signaling being partitioned into that individual bit is formed is by Bose-Chaudhuri-Hocquenghem Code, as knot Fruit, M_outerIndividual BCH Parity Check Bits are generated.In addition, the process of signaling and BCH Parity Check Bits including being partitioned into The bit of Bose-Chaudhuri-Hocquenghem Code is input into LDPC encoder 130.That is, form LDPC code (i.e., by the bit of Bose-Chaudhuri-Hocquenghem Code LDPC information bits) input bit.

Here, K_segIt is the maximum of the quantity for the signaling bit being partitioned into, therefore, K_seg+M_outerValue turns into after segmentation LDPC code input bit maximum.

Work as K_seg+M_outerIt is worth hour, (that is, the quantity for the signaling being partitioned into is big) is performed due to more multi-split, because This is by K_segIt is arranged to the K by the length from the input bit for being used as LDPC code_ldpcSubtract the BCH odd evens obtained by Bose-Chaudhuri-Hocquenghem Code The quantity M of check bit_outerAnd the value obtained is effective.

Therefore, K is worked as_ldpc=3240 and M_outerWhen=168, K_ldpc-M_outer=3240-168=3072 and K_seg= 3072, work as K_ldpc=6480 and M_outerWhen=168, K_ldpc-M_outer=6480-168=6312 and K_seg=6312.

However, when repeating to be performed, due to the length length of the input bit of LDPC code, therefore required performance can not be by Meet.In this case, as segmentation threshold value K_segNeed to be set to less than K_ldpc-M_outerValue.

In detail, the K of the maximum i values in the value that can meet required performance_ldpc-M_outer- 360 × i is arranged to During input bit, K_segLess than K_ldpc-M_outerAnd value K can be arranged to_ldpc-M_outer-360×i.Here, i is integer.

That is, when repeating to be performed, due to K_ldpc=3240 and M_outer=168, therefore can not expire when having When (3240-168-360 × i) of maximum i values in the value of performance needed for foot is arranged to input bit, K_segLess than 3072 simultaneously And value (3240-168-360 × i) can be arranged to.Here, i is integer.

In this case, K is being calculated_segThe reason for middle use value 360 is the LDPC code according to the present exemplary embodiment The row of parity matrix have the pre-defined rule of Unit 360 (that is, row group unit).Therefore, when the quantity of input bit is limited When being set to 360 multiple, arrange corresponding with corresponding bits is defined, and can more easily realize coding and decoding.

Meanwhile Fig. 5 is to show the length N according to the bit by Bose-Chaudhuri-Hocquenghem Code according to exemplary embodiment_outer=K_sig+ M_outerMeet FER (FER)=10^-4Signal to noise ratio (SNR) diagram.

Here, transverse axis represents the length of the bit by Bose-Chaudhuri-Hocquenghem Code, and the longitudinal axis represents to meet FER=10^-4SNR.

In addition, dotted line represents and most robust data meets FER=10 in additive white Gaussian noise (AWGN) channel^-4's SNR=-6.23dB values compare the SNR value -7.73dB with 1.5dB gains.In addition, solid line is represented according to by Bose-Chaudhuri-Hocquenghem Code The length of bit meets FER=10^-4SNR value.

In this case, as described above, signaling needs to ensure to compare FER=in the SNR equal to or less than -7.73dB 10^-4Better performance, therefore, solid line need to present in the region below dotted line.

However, work as K_sig+M_outerDuring ＞ 2520, because dotted line is presented in solid line area above, therefore K_seg= (K_ldpc-M_outer- 360 × i)≤2520 need be satisfied and meet (K_ldpc-M_outer- 360 × i)≤2520 maximum i values are 2, therefore, K_seg=(3240-168-360 × 2)=2352.

So, according to exemplary embodiment, in order to according to code check and whether perform repetition to meet the performance of needs, K_seg =2352,3072 or 6312, therefore, segmentation is performed.

Meanwhile aforementioned exemplary describes signaling and is not divided into some, this is only an example.

For example, signaling can also be divided into two parts, i.e. signaling 1 and signaling 2.

In this case, the information that signaling 1 may include according to frame not changed at least two successive frames is (for example, need Information data are demodulated and decoded), the information that signaling 2 may include to be changed according to frame is (for example, on data in data The information of the position for the unit being mapped in symbol).

Hereinafter, when signaling is divided into two parts, reference picture 6 is carried out to the method for being split to signaling It is described in detail.

First, dispenser 110 can calculate the quantity N for the fec frame of signaling based on equation 13 below_{L1D_FECFRAME}。

In above equation 13, K_{L1D_ex_pad}Represent the summation of the quantity of the bit of signaling 1 and the quantity of the bit of signaling 2 Value.

In addition, K_segIt is the threshold value for segmentation, for example, K_seg=2352,3072 or 6312.

In addition, dispenser 110 can calculate the quantity of filling bit.In detail, dispenser 110 can based on equation 14 below come Calculate the quantity K of filling bit_{L1D_PAD}。

K_{L1D_PAD}=K_{L1_D1_PAD}+K_{L1_D2_PAD} …(14)

In above equation 14, K_{L1_D1_PAD}Represent the quantity of the filling bit for signaling 1, K_{L1_D2_PAD}Represent for letter Make the quantity of 2 filling bit.

That is, signaling is divided into signaling 1 and signaling 2, therefore, dispenser 110 is by for the filling bit of signaling 1 Quantity K_{L1_D1_PAD}With the quantity K of the filling bit for signaling 2_{L1_D2_PAD}Summation, is filled out so as to calculate for all of signaling Fill the quantity of bit.

In this case, dispenser 110 can calculate K based on equation 15 below and equation 16_{L1_D1_PAD}And K_{L1_D2_PAD}。

In above equation 15 and equation 16, K_{L1_D1}Represent the quantity of the bit of signaling 1, K_{L1_D2}Represent the bit of signaling 2 Quantity.

In addition, dispenser 110 can fill K in field is filled_{L1D_PAD}Individual zero bit.Therefore, K_{L1D_PAD}Individual zero bit can quilt It is added in signaling so that as shown in fig. 6, all signalings can be formed by signaling 1, signaling 2 and filling bit.

Next, dispenser 110 can calculate the total length of all signalings including zero bit based on equation 17 below K_L1D。

K_L1D=K_{L1D_ex_pad}+K_{L1D_PAD} …(17)

That is, dispenser 110 can be to the quantity of the bit of signaling 1, the quantity of the bit of signaling 2 and filling bit Quantity is summed to calculate the total length of all signalings including filling bit.

In addition, dispenser 110 can calculate the quantity K of the signaling bit in fec frame based on equation 18 below_sig.Namely Say, dispenser 110 can calculate the quantity K for the signaling bit being included in fec frame based on equation 18 below_sig。

Next, dispenser 110 can be based on K_sigTo split to all signalings.In detail, as shown in Figure 6, split Device 110 can be according to K_sigBit is split so that signaling is divided into N to all signalings_{L1D_FECFRAME}Individual block.

In this case, dispenser 110 signaling can be carried out segmentation so that signaling 1 and signaling 2 be included in it is multiple In each block in block.

For example, as shown in Figure 6, dispenser 110 according toThe quantity of individual bit is sequentially right Signaling 1 is split so that signaling 1 is divided into N_{L1D_FECFRAME}Individual sub-block.Therefore, the sub-block in addition to last sub-block can be byIndividual bit is formed, and last sub-block can be by Individual bit is formed.

In addition, dispenser 110 according toThe quantity of individual bit is sequentially divided signaling 2 Cut so that signaling 2 is divided into N_{L1D_FECFRAME}Individual sub-block.Therefore, the sub-block in addition to last sub-block can be byIndividual bit is formed, and last sub-block can be by Individual bit is formed.

In addition, dispenser 110 sequentially can sum to the sub-block split in signaling 1 and the sub-block split in signaling 2 To form multiple pieces, wherein, each block is by K_sigIndividual bit is formed.

In this case, can be by K for last sub-block, dispenser 110_{L1_D1_PAD}Individual zero bit is added in signaling 1 In the last sub-block that is partitioned into, by K_{L1_D2_PAD}Individual zero bit is added to the last sub-block being partitioned into signaling 2, and with The two sub-blocks added with zero bit are summed afterwards to form with K_sigThe final block of individual bit.

By the above method, the signaling including signaling 1 and signaling 2 can be divided into pre-set dimension by dispenser 110 Multiple pieces.Here, each block can be by K_sigIndividual bit is formed.

Meanwhile as described above, signaling is divided into signaling 1 and signaling 2, and when signaling 1 and signaling 2 are split respectively, It can overflow.

In detail, K is worked as_{L1D_ex_pad}=K₁+K₂When, whenValue be more than K_segWhen Overflow.Here, K₁And K₂It is the length for the part being partitioned into respectively.That is, because signaling 1 and signaling 2 are by individually Segmentation, therefore K₁=K_{L1_D1}And K₂=K_{L1_D2}。

Due to K_segIt is the threshold value of the quantity for the signaling bit being partitioned into, therefore is more than K_seg'sThe value quantity of signaling bit that represents to be partitioned into be more than threshold value, thus, it is believed that Overflow.

Therefore, whenWhen, it can avoid overflowing, if metThen It can be represented by following formula 19.

K₁=N_{L1D_FECFRAME}(K_seg1- 1)+i wherein, i=1,2 ..., N_{L1D_FECFRAME}

K₂≤N_{L1D_FECFRAME}(K_seg-K_seg1) ...(19)

From above expression formula 19, following formula 20 can be obtained.

K_{L10_ex_PAD}≤N_{L1D_FECFRAME}(K_seg- 1)+i wherein, i=1,2 ..., N_{L1D_FECFRAME} ...(20)

For all i, meeting the necessary condition of above-mentioned expression formula 20 isKnot Fruit, whenWhen, do not overflow.

Therefore, when signaling is divided into two parts, if segmentation is performed based on above-mentioned equation 13, can avoid Overflow.

When signaling is divided into two parts, dispenser 110 can be based on above-mentioned equation 13 and calculate N_{L1D_FECFRAME}, this is only It is an example.Therefore, dispenser 110 can calculate N by various schemes_{L1D_FECFRAME}.The example below is only calculating N_{L1D_FECFRAME}Method in there is difference, and based on the N calculated_{L1D_FECFRAME}The method split to signaling is identical, Therefore, will be described only for calculating N_{L1D_FECFRAME}Various methods.

For example, dispenser 110 can calculate the quantity N for the fec frame of signaling based on equation 2 below 1_{L1D_FFCFRAMF}。

In above equation 21, K_segCan be 2352,3072 or 6312.

As another example, dispenser 110 can calculate the quantity of the fec frame for signaling based on equation 2 below 2 N_{L1D_FECFRAME}。

In above equation 22, K_segCan be 2352,3072 or 6312.

As another example, dispenser 120 can calculate the quantity of the fec frame for signaling based on equation 2 below 3 N_{L1D_FECFRAME}。

In above-mentioned equation 23, K_segCan be 2351,3071 or 6311.

Above-mentioned example describes signaling and is divided into two parts, and this is only an example.

Signaling can be divided into m part.For example, signaling can also be divided into m part, i.e. signaling 1, signaling 2nd ..., signaling m.

In this case, dispenser 120 can calculate the quantity of the fec frame for signaling based on equation 2 below 4 N_{L1_Dyn_FECFRAME}。

In above-mentioned equation 24, K_{L1D_ex_pad}Represent signaling 1, signaling 2 ... and the summation of the quantity of signaling m bit Value.In above-mentioned equation 24, K_segCan be 2352,3072 or 6312.

When signaling is divided into m part, it is as follows that the reason for splitting is performed based on above-mentioned equation 24.

In detail, K is worked as_{L1D_ex_pad}=K₁+K₂+...+K_mWhen, whenValue be more than K_segShi Fasheng overflows.

Therefore, when When, if metIt can then keep away Exempt to overflow, this can be by the table of equation 2 below 5 not.

K₁=N_{L1D_FECFRAME}(K_seg1-1)+i₁Wherein i₁=1,2 ..., N_{L1D_FECFRAME}(1)

K₂=N_{L1D_FECFRAME}(K_seg2-1)+i₂Wherein i₂=1,2 ..., N_{L1D_FECFRAME}(2)

...

K_m-1=N_{L1D_FECFRAME}(K_seg(m-1)-1)+i_m-1Wherein i_m-1=1,2 ..., N_{L1D_FECFRAME} (m-1)

K_m≤N_{L1D_FECFRAME}(K_seg-K_seg1-K_seg2-...-K_seg(m-1)) (m)

...(25)

From above equation 25, following formula 26 can be obtained.

For all i_j, meeting the necessary condition of above-mentioned expression formula 26 isCause This, ifDo not overflow when signaling is divided into m part then Go out.

Therefore, in order to avoid overflowing, dispenser 120 performs segmentation based on above-mentioned equation 24.

With reference to above-mentioned equation 24, if the m=1 in above-mentioned equation 24, above-mentioned equation 24 is identical with above-mentioned equation 1, because This, when signaling is not divided into some, performs segmentation if based on above-mentioned equation 1, does not then overflow.

In addition, with reference to above-mentioned equation 24, if the m=2 in above-mentioned equation 24, above-mentioned equation 24 and the above-mentioned phase of equation 13 Together, therefore, when signaling is divided into two parts, segmentation is performed if based on above-mentioned equation 13, then is not overflowed.

So, dispenser 110 can be split based on various methods as described above to signaling.

Meanwhile it can be realized according to exemplary embodiment, foregoing signaling by L1- details signaling.Therefore, transmitter 100 can lead to Cross and L1- details signalings are split using preceding method and the L1- details signalings through over-segmentation are sent to receiver 200.

Here, L1- details signaling can be the signaling defined in the standard of Advanced Television Systems Committee (ATSC) 3.0.

L1- details signaling can be processed according to the individual different mode in seven (7).According to the transmitter 100 of exemplary embodiment Can be according to corresponding pattern by K_seg2352,3072 or 6312 are arranged to split to L1- details signalings.

In addition to L1- details signalings, the standards of ATSC 3.0 also define the basic signalings of L1-.Transmitter 100 can be by using Specified scheme handles the basic signalings of L1- and L1- details signalings, and by the basic signalings of treated L1- and L1- details signalings It is sent to receiver 200.The basic signalings of L1- can also be processed according to the individual different mode in seven (7).

The method for handling the basic signalings of L1- and L1- details signalings will be described below.

The basic signalings of L1- and L1- details protocol mapping to the leading of frame and can be mapped the data into frame by transmitter 100 Data symbol, to be sent to receiver 200.

Reference picture 7, frame can be made up of three parts, i.e. guiding (bootstrap) part, leading part and data division.

Leader is used for initial synchronisation and provides receiver 200 L1 signalings are carried out to decode required basic ginseng Number.In addition, leader may include the information relevant with the pattern handled in transmitter 100 the basic signalings of L1-, i.e. The information relevant with the pattern for being used to handle the basic signalings of L1- that transmitter 100 uses.

Leading part includes L1 signalings and can be made up of two parts, i.e. the basic signalings of L1- and L1- details signalings.

Here, the basic signalings of L1- may include the information relevant with L1- details signalings, and L1- details signalings may include and data Relevant information.Here, data are broadcast datas for providing broadcast service and can be by least one physical layer channels (PLP) sent.

In detail, the basic signalings of L1- include the information required for the processing L1- details signalings of receiver 200.The packet Including the information relevant for example with handling the pattern of L1- details signalings in transmitter 100, (that is, what is used with transmitter 100 is used to locate Manage the relevant information of pattern of L1- details signalings), the information relevant with the length of L1- details signalings and additional parity mould The relevant information of formula (that is, is produced using L1B_L1_Detail_additional_parity_mode with transmitter 100 and added very The relevant information of K values used in even parity check bit) (here, work as L1B_L1_Detail_additional_parity_mode Be arranged to ' 00' when, K=0 and additional parity-check bits are not used) and the letter relevant with the length of whole cells Breath.In addition, the basic signalings of L1- may include the basic signaling information relevant with the system including transmitter 100, such as quick Fourier Leaf transformation (FFT) size, protection interval and pilot frequency design.

In addition, L1- details signaling carries out decoding required information including receiver 200 to PLP, for example, being mapped to every The original position of the cell of individual PLP data symbol, PLP identifiers (ID), PLP size, modulation scheme, code check etc..

Therefore, receiver 200 can obtain frame synchronization, from the basic signalings of leading acquisition L1- and L1- details signalings, and make The service data of user's needs is received from data symbol with L1- details signaling.

The side for handling the basic signalings of L1- and L1- details signalings is hereinafter described more fully with reference to the accompanying drawings Method.

Fig. 8 and Fig. 9 is the block diagram for describing the detailed configuration of the transmitter 100 according to exemplary embodiment.

In detail, as shown in Figure 8, in order to handle the basic signalings of L1-, transmitter 100 may include scrambler 211, BCH Encoder 212, zero padding device 213, LDPC encoder 214, even-odd check displacer 215, duplicator 216, puncturer 217, zero Remover 219, bit demultiplexer 219 and constellation mapper 221.

In addition, as shown in Figure 9, in order to handle L1- details signalings, transmitter 100 may include dispenser 311, scrambler 312nd, Bose-Chaudhuri-Hocquenghem Code device 313, zero padding device 314, LDPC encoder 315, even-odd check displacer 316, duplicator 317, puncturer 318th, additional parity generator 319, zero remover 321, bit demultiplexer 322 and bit demultiplexer 323, Yi Jixing Seat mapper 324 and constellation mapper 325.

Here, the component as shown in 8 and Fig. 9 is to be used to perform coding to the basic signalings of L1- and L1- details signaling and adjust The component of system, this is only an example.According to another exemplary embodiment, some groups in the component shown in Fig. 8 and Fig. 9 Part can be omitted or change, and other components can be also added.In addition, the position of some components in component can be changed. For example, the position of duplicator 216 and duplicator 317 can be arranged in after puncturer 217 and puncturer 318.

Executable point by being shown in Fig. 1 of dispenser 311, Bose-Chaudhuri-Hocquenghem Code device 313 and LDPC encoder 315 shown in Fig. 9 The operation that cutter 110, external encoder 120 and LDPC encoder 130 perform.

In the description to Fig. 8 and 9, for convenience, the component for performing common function will be described together.

The basic signalings of L1- and L1- details signaling can be protected by the cascade of BCH foreign keys and LDPC internal codes.So And this is only an example.Therefore, as the external encode that performs before internally being encoded in concatenated coding, except can Outside Bose-Chaudhuri-Hocquenghem Code, another coding of such as CRC codings also can be used.In addition, the basic signalings of L1- and L1- details signalings can Only protected by LDPC internal codes, without foreign key.

First, the basic signalings of L1- and L1- details signaling can be scrambled.In addition, the basic signalings of L1- and L1- details signaling quilts Bose-Chaudhuri-Hocquenghem Code, and therefore, can quilt from the BCH Parity Check Bits of the basic signalings of L1- caused by Bose-Chaudhuri-Hocquenghem Code and L1- details signalings It is respectively added to the basic signalings of L1- and L1- details signalings.In addition, cascade signaling and BCH Parity Check Bits can pass through by The 16K LDPC codes of reduction and censoring are protected with being attached.

In order to provide the various robustness ranks for being suitable for wide signal to noise ratio (SNR) scope, the basic signalings of L1- and L1- details The protection level of signaling is divided into seven (7) kind pattern.That is, the protected level of the basic signalings of L1- and L1- details signalings LDPC code, order of modulation, reduction/censoring parameter (that is, the quantity for the bit that will be truncated and the bit that will be contracted by can be based on Quantity ratio) and by the quantity of the bit being substantially truncated (that is, by base when being 0 by the quantity for the bit being contracted by The quantity for the bit being truncated in sheet) and it is divided into 7 kinds of patterns.In each pattern, LDPC code, order of modulation, constellation with And at least one various combination in reduction/censoring pattern can be used.

The pattern that transmitter 100 handles signaling can be pre-arranged according to system.Therefore, transmitter 100 can be according to setting The pattern put determine for handle signaling parameter (for example, modulation and code check (ModCod) for each pattern, for BCH The parameter of coding, the parameter for zero padding, reduction pattern, code check/code length of LDPC code, by a group intertexture pattern, for repeat Parameter, the parameter for censoring and modulation scheme etc.), and signaling can be handled and will be through based on the parameter of determination The signaling for crossing processing is sent to receiver 200.For such purpose, transmitter 100 can be prestored and be used for according to pattern Handle the parameter of signaling.

For the modulation of 7 kinds of patterns and 7 kinds of patterns for handling L1- details signalings for handling the basic signalings of L1- It is illustrated with code check configuration (ModCod configurations) in following table 4.Transmitter 100 can be according to corresponding pattern based on following The ModCod configurations limited in table 4 are encoded and modulated to signaling.That is, transmitter 100 can be true based on following table 4 The coding and modulation scheme that signaling is directed under each pattern are scheduled on, and signaling can be encoded and adjusted according to the scheme of determination System.In this case, even if when being modulated by identical modulation scheme to L1 signalings, transmitter 100 can also be used Different constellations.

[table 4]

In table 4 more than, K_sigThe quantity of the information bit of presentation code block.That is, because length is K_sig's L1 signaling bits are encoded to produce encoding block, therefore the length of L1 signalings is changed into K in an encoding block_sig.Therefore, size For K_sigL1 signaling bits can be considered as corresponding with a LDPC encoding block.

Table 4 with reference to more than, for the K of the basic signalings of L1-_sigValue is fixed to 200.However, due to L1- details signalings The amount of bit changes, therefore, for the K of L1- details signalings_sigValue changes.

In detail, in the case of L1- details signalings, the quantity of L1- details signaling bits changes, and therefore works as When the quantity of L1- details signaling bits is more than preset value, L1- details signaling can be divided with equal to or less than preset value Length.

In this case, the L1- details signaling block (that is, fragment of L1- details signalings) being partitioned into it is each Big I has the K limited in the table 4 more than_sigValue.In addition, size is K_sigThe L1- details signaling blocks being partitioned into Each it may correspond to a LDPC encoding block.

However, when the quantity of L1- details signaling bits is equal to or less than preset value, L1- details signaling can not be divided. In this case, the big I of L1- details signaling has the K limited in the table 4 of the above_sigValue.In addition, size is K_sig's L1- details signalings may correspond to a LDPC encoding block.

Hereinafter, it will be described in the method for being split to L1- details signalings.

The divisible L1- details signaling of dispenser 311.In detail, because the length of L1- details signalings changes, therefore work as When the length of L1- details signalings is more than preset value, L1- details signalings can be divided into pre- with being equal to or less than by dispenser 311 If the bit of the quantity of value, and each will be output to scrambler 312 in the L1- details signalings being partitioned into.

However, when the length of L1- details signalings is equal to or less than preset value, dispenser 311 does not perform single segmentation Operation.

The method split by dispenser 311 to L1- details is as follows.

The amount of L1- details signaling bits changes and depends primarily on PLP quantity.Therefore, believe to send L1- details All bits of order are, it is necessary at least one forward error correction (FEC) frame.Here, fec frame can represent what L1- details signalings were encoded Form, and therefore, L1- details signalings are added to according to the Parity Check Bits of coding.

In detail, when L1- details signaling is not divided, L1- details signaling is encoded to produce by Bose-Chaudhuri-Hocquenghem Code and LDPC One fec frame, and therefore, L1- details signaling, which is sent, needs a fec frame.On the other hand, when L1- details signalings are divided During at least two, these L1- details signalings being partitioned into are encoded to produce at least two fec frames by Bose-Chaudhuri-Hocquenghem Code and LDPC, Therefore, L1- details signaling, which is sent, needs at least two fec frames.

Therefore, dispenser 311 can calculate the quantity of the fec frame for L1- details signalings based on following equation 27 N_{L1D_FECFRAME}.That is, the quantity N of the fec frame for L1- details signalings_{L1D_FECFRAME}Can based on following equation 27 come It is determined that.

In equation 27 more than,Represent the smallest positive integral equal to or more than x.

In addition, in equation 27 more than, as shown in Figure 10, K_{L1D_ex_pad}Represent in addition to L1 filling bits The length of L1- details signalings, and L1B_L1_Detail_size_bits fields included in the basic signalings of L1- can be passed through Value determine.

In addition, K_segRepresent the quantity based on the information bit (that is, LDPC information bits) for being input to LDPC encoder 315 K_ldpcAnd the number of thresholds for segmentation limited.In addition, K_segBCH odd evens school that can be based on 360 multiple value and Bose-Chaudhuri-Hocquenghem Code The quantity of bit is tested to limit.

K_segIt is determined so that after L1- details signaling is divided, the quantity K of the information bit in encoding block_sigQuilt It is equal to or less than K_ldpc-M_outer.In detail, when L1- details signaling is based on K_segWhen being divided, due to what is be partitioned into Of length no more than K of L1- details signalings_seg, therefore, work as K_segWhen being set as following table 5, the L1- details that is partitioned into The length of signaling is set equal to or less than K_ldpc-M_outer。

Here, M_outerAnd K_ldpcSuch as following table 6 and table 7.For enough robustnesses, for L1- details signaling mode 1 K_segValue can be arranged to K_ldpc-M_outer-720。

For the K of each pattern of L1- details signalings_segIt can be defined as following table 5.In this case, divide Cutter 311 can determine K according to such as the corresponding modes as shown in following table 5_seg。

[table 5]

As shown in Figure 10, whole L1- details signaling can be formed by L1- details signaling and L1 filling bits.

In this case, dispenser 311 can calculate the L1_PADDING of L1- details signalings based on following equation 28 Length (that is, the quantity of L1 filling bits of field_{L1D_PAD})。

However, K is calculated based on following equation 28_{L1D_PAD}An only example.That is, dispenser 311 can Based on K_{L1D_ex_pad}Value and N_{L1D_FECFRAME}To calculate the length of the L1_PADDING fields of L1- details signalings, (that is, L1 is filled value The quantity K of bit_{L1D_PAD}).As an example, K_{L1D_PAD}Value can be obtained based on following equation 28.That is, below Equation 28 be only used for obtain K_{L1D_PAD}One example of the method for value, therefore, based on K_{L1D_ex_pad}Value and N_{L1D_FECFRAME} The another method of value can be employed to obtain equivalent result.

In addition, dispenser 311 can use K_{L1D_PAD}Individual zero bit (that is, the bit with 0 value) fills L1_PADDING words Section.Therefore, as shown in Figure 10, K_{L1D_PAD}Individual zero bit can be filled into L1_PADDING fields.

In this way, by calculating the length of L1_PADDING fields and by zero bit padding of the length calculated to L1_ PADDING fields, when L1- details signaling is divided, L1- details signaling can be divided into what is formed by the bit of identical quantity Multiple pieces.

Next, dispenser 311 can calculate the whole L1- details letter including zero padding bit based on following equation 29 The final lengths K of order_L1D。

K_L1D=K_{L1D_ex_pad}+K_{L1D_PAD} ...(29)

In addition, dispenser 311 can calculate N based on following equation 30_{L1D_FECFRAME}The information in each block in individual block The quantity K of bit_sig。

K_sig=K_LlD/N_{LlD_FECFRAME} ...(30)

Next, dispenser 311 can be according to K_sigIndividual bit is split to L1- details signalings.

In detail, as shown in Figure 10, N is worked as_{L1D_FECFRAME}During more than 1, dispenser 311 can be according to K_sigIndividual bit pair L1- details signalings are split so that L1- details signalings are divided into N_{L1D_FECFRAME}Individual block.

Therefore, L1- details signaling can be divided into N_{L1D_FECFRAME}Individual block, the N_{L1D_FECFRAME}In each block in individual block The quantity of L1- details signaling bits can be K_sig.In addition, the L1- details signalings being each partitioned into are encoded.As coding Result, encoding block (that is, fec frame) is formed so that N_{L1D_FECFRAME}The L1- details in each encoding block in individual encoding block The quantity of signaling bit can be K_sig。

However, when L1- details signaling is not divided, K_sig=K_{L1D_ex_pad}。

The L1- details signaling block being partitioned into can be encoded by following process.

In detail, size K_sigL1- details signaling blocks in all bits of each L1- details signaling block can quilt Scrambling.Next, scrambling after L1- details signaling blocks in it is each can by the cascade of BCH foreign keys and LDPC internal codes and It is encoded.

In detail, it is each by Bose-Chaudhuri-Hocquenghem Code in L1- details signaling block, therefore M_outer(=168) individual BCH even-odd checks Bit can be added to each piece of K_sigIndividual L1- details signaling bit, then, the L1- details signaling bit and BCH of each block The cascade of Parity Check Bits can be encoded by the 16K LDPC codes by reduction and censoring.BCH code and LDPC code it is thin Section will be described below.However, exemplary embodiment only describes M_outer=168 situation, however, it is apparent that M_outerSuitable value can be changed to according to the needs of system.

Scrambler 211 and scrambler 312 can scramble to the basic signalings of L1- and L1- details signalings respectively.In detail To say, scrambler 211 and scrambler 312 can be randomized the basic signalings of L1- and L1- details signaling, and by the L1- bases of randomization This signaling and L1- details signaling export to Bose-Chaudhuri-Hocquenghem Code device 212 and Bose-Chaudhuri-Hocquenghem Code device 313 respectively.

In this case, scrambler 211 and scrambler 312 can be with K_sigInformation bit is scrambled for unit.

That is, because the quantity of the basic signaling bits of the L1- that receiver 200 is sent to by each frame is 200, because This scrambler 211 can be according to K_sig(=200) scramble to the basic signaling bits of L1-.

The quantity of the basic signaling bits of L1- due to being sent to receiver 200 by each frame changes, therefore in some feelings Under condition, L1- details signaling can be split by dispenser 311.In addition, dispenser 311 can will be by K_sigThe L1- details that individual bit is formed Signaling or the L1- details signaling blocks being partitioned into are exported to scrambler 312.As a result, scrambler 312 can be according to every K_sigTo from The L1- details signaling bits that dispenser 311 exports are scrambled.

Bose-Chaudhuri-Hocquenghem Code device 212 and Bose-Chaudhuri-Hocquenghem Code device 313 can perform Bose-Chaudhuri-Hocquenghem Code to produce to the basic signalings of Ll and L1- details signaling Raw BCH Parity Check Bits.

In detail, Bose-Chaudhuri-Hocquenghem Code device 212 and Bose-Chaudhuri-Hocquenghem Code device 313 can be to the Ll from scrambler 211 and the output of scrambler 313 Basic signaling and L1- details signalings perform Bose-Chaudhuri-Hocquenghem Code respectively, to produce BCH Parity Check Bits, and will pass through Bose-Chaudhuri-Hocquenghem Code Bit export respectively to zero padding device 213 and zero padding device 314, wherein, by Bose-Chaudhuri-Hocquenghem Code bit in, BCH odd evens school Test bit be added to it is each in the basic signalings of Ll and L1- details signalings.

For example, Bose-Chaudhuri-Hocquenghem Code device 212 and Bose-Chaudhuri-Hocquenghem Code device 313 can be to the K of input_sigIndividual bit performs Bose-Chaudhuri-Hocquenghem Code to produce M_outer(that is, K_sig=K_payload) individual BCH Parity Check Bits, and will be by N_outer(=K_sig+M_outer) warp that is formed of individual bit The bit for crossing Bose-Chaudhuri-Hocquenghem Code exports to zero padding device 213 and zero padding device 314 respectively.

It can be defined for the parameter of Bose-Chaudhuri-Hocquenghem Code as following table 6.

[table 6]

Meanwhile reference picture 8 and Fig. 9, it will be understood that, LDPC encoder 214 and LDPC encoder 315 can be arranged respectively After Bose-Chaudhuri-Hocquenghem Code device 213 and Bose-Chaudhuri-Hocquenghem Code device 213.

Therefore, the basic signalings of L1- and L1- details signaling can be protected by the cascade of BCH foreign keys and LDPC internal codes Shield.

In detail, the basic signalings of L1- and L1- details signalings be by Bose-Chaudhuri-Hocquenghem Code, and therefore, for the basic signalings of L1- BCH Parity Check Bits can be added to the basic signalings of L1-, can be added for the BCH Parity Check Bits of L1- details signalings To L1- details signalings.In addition, the basic signalings of L1- and BCH Parity Check Bits of cascade can be protected extraly by LDPC code Shield, and the L1- details signaling and BCH Parity Check Bits that cascade can be protected extraly by LDPC code.

Here, suppose that the LDPC code for LDPC codings is 16K LDPC codes, therefore, compiled in Bose-Chaudhuri-Hocquenghem Code device 212 and BCH In code device 213, for N_inner=16200 (that is, the code length of 16K LDPC codes is 16200, by LDPC encode caused by LDPC code Word can be formed by 16200 bits) systematic BCH code can be used for the outside for performing the basic signalings of L1- and L1- details signalings Coding.

Zero padding device 213 and zero padding device 314 fill zero bit.In detail, for LDPC code, it is necessary to according to code check and The LDPC information bits for the predetermined quantity that code length limits, therefore, when the quantity of the bit by Bose-Chaudhuri-Hocquenghem Code is less than LDPC information ratio During the quantity of spy, zero padding device 213 and zero padding device 314 can be directed to LDPC codings zero bit of filling to produce by by BCH volumes The LDPC information bits for the predetermined quantity that the bit and zero bit of code are formed, and caused bit is exported respectively and compiled to LDPC Code device 214 and LDPC encoder 315.When the quantity of the bit by Bose-Chaudhuri-Hocquenghem Code is equal to the quantity of LDPC information bits, zero ratio Spy is not filled.

Here, zero bit filled by zero padding device 213 and zero padding device 314 is encoded and is filled for LDPC, therefore, The bit of filling zero being filled is not delivered to receiver 200 by reducing operation.

For example, when the quantity of the LDPC information bits of 16K LDPC codes is K_ldpcWhen, in order to form K_ldpcIndividual LDPC information ratio Spy, zero bit are filled.

In detail, when the quantity of the bit by Bose-Chaudhuri-Hocquenghem Code is N_outer, the number of the LDPC information bits of 16K LDPC codes Amount is K_ldpc, and No_uter＜ K_ldpcWhen, zero padding device 213 and zero padding device 314 can fill K_ldpc-No_uterIndividual zero bit and By No_uterThe individual bit by Bose-Chaudhuri-Hocquenghem Code is used as the remainder of LDPC information bits to produce by K_ldpcWhat individual bit was formed LDPC information bits.However, work as No_uter=K_ldpcWhen, zero bit is not filled.

For such purpose, LDPC information bits can be divided into multiple bits by zero padding device 213 and zero padding device 314 Group.

For example, zero padding device 213 and zero padding device 314 can be based on following equatioies 31 or equation 32 by K_ldpcIndividual LDPC letters Cease bitIt is divided into N_info__gro_up(=K_ldpc/ 360) individual bit group.That is, zero padding device 213 and zero padding device 314 LDPC information bits can be divided into multiple bit groups so that included bit in each bit group Quantity be 360.

Z_j={ i_k| 360 × j≤k ＜ 360 × (j+1) }, wherein, 0≤j ＜ N_{info_group}…(32)

In equation 31 and equation 32 more than, Z_jRepresent j-th bit group.

For the parameter N for zero padding of the basic signalings of L1- and L1- details signalings_outer、K_ldpcAnd N_{info_group}Can be such as It is defined shown in following table 7.In this case, zero padding device 213 and zero padding device 314 can be such as institutes in following table 7 Show according to corresponding modes to determine the parameter for zero padding.

[table 7]

In addition, it is directed to 0≤j ＜ N_{info_group}, each bit group Z as shown in Figure 11_jIt can be formed by 360 bits.

In detail, Figure 11 shows the data after the basic signalings of L1- and L1- details signalings are each encoded by LDPC Form.In fig. 11, it is added to K_ldpcThe LDPC FEC of individual LDPC information bits represent strange by LDPC caused by LDPC codings Even parity check bit.

Reference picture 11, K_ldpcIndividual LDPC information bits are divided into N_{info_group}Individual bit group, each bit group can be by 360 Individual bit is formed.

When the basic signalings of L1- and the quantity N of the bit by Bose-Chaudhuri-Hocquenghem Code of L1- details signalings_outer(=K_sig+M_outer) Less than K_ldpc(that is, N_outer(=K_sig+M_outer) ＜ K_ldpc) when, encoded for LDPC, K_ldpcIndividual LDPC information bits are available N_outerIndividual bit and K by Bose-Chaudhuri-Hocquenghem Code_ldpc-N_outerThe bit of individual zero padding is filled.In this case, the zero of filling Bit is not sent to receiver 200.

Hereinafter, the reduction process performed by zero padding device 213 and zero padding device 314 will be described in further detail.

Zero padding device 213 and zero padding device 314 can calculate the quantity of zero bit of filling.That is, in order to fill The bit of quantity required for LDPC codings, zero padding device 213 and zero padding device 314 can be calculated the number of zero bit of filling Amount.

In detail, zero padding device 213 and zero padding device 314 can be by the quantity of LDPC information bits with passing through Bose-Chaudhuri-Hocquenghem Code Bit quantity between mathematic interpolation for filling zero bit quantity.That is, for given N_outer, zero padding The quantity of zero bit of filling can be calculated as K by device 213 and zero padding device 314_ldpc-N_outer。

In addition, zero padding device 213 and zero padding device 314 can calculate the quantity for the bit group that all bits are filled.Also It is to say, zero padding device 213 and zero padding device 314 can calculate all bits in bit group by the bit group of zero bit padding Quantity.

In detail, zero padding device 213 and zero padding device 314 can be all to calculate based on following equation 33 or equation 34 The quantity N for the group that bit is filled_pad。

Next, zero padding device 213 and zero padding device 314 can determine zero among multiple bit groups based on reduction pattern The bit group that bit is filled, and can be by all bits in some bit groups in the bit group of zero bit padding to determination With some bits in remaining bits group.

In this case, the reduction pattern of the bit group by filling can be defined as shown in following table 8.At this In the case of kind, zero padding device 213 and zero padding device 314 pattern corresponding to can determine to reduce as shown in following table 8 Pattern.

[table 8]

Here, π_s(j) be jth filling bit group index.That is, π_s(j) the reduction pattern of j-th bit group is represented Sequentially.In addition, N_{info_group}It is the quantity for the bit group for forming LDPC information bits.

In detail, zero padding device 213 and zero padding device 314 can be incited somebody to action based on reduction pattern It is defined as all bits in bit group by the bit group of zero bit padding, and zero Tucker 213 and zero padding device 314 can be by all bits of zero bit padding to the bit group.That is, zero padding device 213 and zero padding device 314 can be based on reduction pattern by the π among zero bit padding to multiple bit groups_s(0) bit group, π_s (1) bit group ..., π_s(N_pad- 1) all bits in bit group.

In this way, work as N_padWhen not being 0, zero padding device 213 and zero padding device 314 can determine N based on table 8 above_padIt is individual The list of bit group is (i.e.,), and the bit by zero bit padding to determination All bits in group.

However, work as N_padWhen being 0, aforementioned process can be omitted.

Simultaneously as the quantity of zero bit of all fillings is K_ldpc-N_outer, and it is filled into N_padThe zero of individual bit group The quantity of bit is 360 × N_pad, therefore zero padding device 213 and zero padding device 314 can be extraly by zero bit paddings to K_ldpc- N_outer-360×N_padIndividual LDPC information bits.

In this case, zero padding device 213 and zero padding device 314 can determine zero bit by extraly based on reduction pattern The bit group of filling, and zero bit can be extraly filled from the head of the bit group of determination.

In detail, zero padding device 213 and zero padding device 314 can be incited somebody to action based on reduction patternIt is defined as extraly Fill the bit group of zero bit, and can be extraly by zero bit padding to being located atHead K_ldpc-N_outer- 360×N_padIndividual bit.Therefore, K_ldpc-N_outer-360×N_padIndividual zero bit can be from π_s(N_pad) bit group first bit Start to be filled.

As a result, it is directed toZero bit can be located at by being extraly filled intoHead K_ldpc- N_bch-360×N_padIndividual bit.

Meanwhile aforementioned exemplary describe fromFirst bit start fill K_ldpc-N_outer-360×N_padIt is individual Zero bit, this is only an example.Therefore, zero bit existsIn the position that is filled can be changed.For example, K_ldpc- N_outer-360×N_padIndividual zero bit can be filled intoCenter section or decline or can also be filled intoAny position.

Next, zero padding device 213 and zero padding device 314 can by by the bit map of Bose-Chaudhuri-Hocquenghem Code to zero bit not by The position of filling is to form LDPC information bits.

Therefore, N_outerThe individual bit by Bose-Chaudhuri-Hocquenghem Code is sequentially mapped to K_ldpcIndividual LDPC information bitsIn do not have fill zero bit bit position, therefore, K_ldpcIndividual LDPC information bits can be by N_outerIt is individual By the bit and K of Bose-Chaudhuri-Hocquenghem Code_ldpc-N_outerIndividual information bit is formed.

Zero bit of filling is not delivered to receiver 200.In this way, the process or zero bit of filling of zero bit of filling are then Zero bit of filling is not sent to the process of receiver 200 can be referred to as reduction.

LDPC encoder 214 and LDPC encoder 315 perform LDPC to the basic signalings of L1- and L1- details signaling respectively and compiled Code.

In detail, LDPC encoder 214 and LDPC encoder 315 can be to defeated from zero padding device 213 and zero padding device 31 The LDPC information bits that go out perform LDPC codings to produce LDPC Parity Check Bits, and will include LDPC information bits and The LDPC code word of LDPC Parity Check Bits exports to even-odd check displacer 215 and even-odd check displacer 316 respectively.

That is, the K exported from zero padding device 213_ldpcIndividual bit may include K_sigThe basic signaling bit of individual L1-, M_outer (=N_outer-K_sig) individual BCH Parity Check Bits and K_ldpc-N_outerZero bit of individual filling, wherein, K_sigIndividual L1- believes substantially Make bit, M_outer(=N_outer-K_sig) individual BCH Parity Check Bits and K_ldpc-N_outerZero bit of individual filling may make up use In the K of LDPC encoder 214_ldpcIndividual LDPC information bits

In addition, the K exported from zero padding device 314_ldpcIndividual bit may include K_sigIndividual L1- details signaling bit, M_outer(= N_outer-K_sig) individual BCH Parity Check Bits and (K_ldpc-N_outer) individual filling zero bit, wherein, K_sigIndividual L1- details letter Make bit, M_outer(=N_outer-K_sig) individual BCH Parity Check Bits and (K_ldpc-N_outer) zero bit of individual filling may make up K for LDPC encoder 315_ldpcIndividual LDPC information bits

In this case, LDPC encoder 214 and LDPC encoder 315 can be systematically to K_ldpcIndividual LDPC information ratio Spy performs LDPC codings to produce by N_innerThe LDPC code word that individual bit is formed

Under L1- basic models and L1- detail modes 1 and 2, LDPC encoder 214 and LDPC encoder 315 can be with 3/ 15 code check is encoded to the basic signalings of L1- and L1- details signalings to produce 16200 LDPC code word bits.In this feelings Under condition, the table 1 that LDPC encoder 214 and LDPC encoder 315 can be based on more than encodes to perform LDPC.

In addition, under L1- detail modes 3,4,5,6 and 7, LDPC encoder 315 can be with 6/15 code check to L1- details Signaling is encoded to produce 16200 LDPC code word bits.In this case, what LDPC encoder 315 can be based on more than Table 3 encodes to perform LDPC.

For the basic signalings of L1- and L1- details signalings code check and code length more than table 5 as shown in, LDPC information ratio As shown in table 8 of the special quantity more than.

Even-odd check displacer 215 and even-odd check displacer 316 perform even-odd check displacement.That is, odd even school Test displacer 215 and even-odd check displacer 316 can be only to the LDPC among LDPC information bits and LDPC Parity Check Bits Parity Check Bits perform displacement.

In detail, even-odd check displacer 215 and even-odd check displacer 316 can be only to from the Hes of LDPC encoder 214 LDPC Parity Check Bits in the LDPC code word that LDPC encoder 315 exports perform displacement, and will be put by even-odd check The LDPC code word changed exports to duplicator 216 and duplicator 317 respectively.Even-odd check displacer 316 can will pass through even-odd check The LDPC code word of displacement is exported to additional parity generator 319.In this case, additional parity generator 319 The LDPC code word by even-odd check displacement exported from even-odd check displacer 316 can be used to produce additional parity ratio It is special.

For such purpose, even-odd check displacer 215 and even-odd check displacer 316 may include that even-odd check interweaves Device (not shown) and by a group interleaver (not shown).

First, the LDPC information bits and LDPC Parity Check Bits that parity interleaver can only to forming LDPC code word Among LDPC Parity Check Bits be interleaved.However, parity interleaver can be only in L1- detail modes 3,4,5,6 and 7 In the case of perform even-odd check interweave.That is, because L1- basic models and L1- detail modes 1 and 2 include conduct The even-odd check of a part for LDPC coded treatments interweaves, therefore under L1- basic models and L1- detail modes 1 and 2, odd even Verification interleaver can not perform even-odd check intertexture.

In the case where performing the pattern that even-odd check interweaves, parity interleaver can be based on following equation 35 to LDPC odd evens Check bit is interleaved.

u_i=c_i, wherein, 0≤i ＜ K_ldpc(information bit is not interleaved)

Wherein, 0≤s ＜ 360,0≤t ＜ 27... (25)

In detail, the equation 35 based on more than, by parity interleaver to LDPC code word Even-odd check intertexture is carried out, and the output of parity interleaver can be by To represent.

Simultaneously as parity interleaver, therefore odd even school is not used in L1- basic models and L1- detail modes 1 and 2 Test the output of interleaverIt may be expressed as following equation 36.

u_i=c_i, wherein, 0≤i<N_inner ...(36)

Output that can be to parity interleaver by group interleaver is performed by group intertexture.

Here, as described above, the output of parity interleaver can carry out odd even school by parity interleaver Test the LDPC code word of intertexture or can be not by parity interleaver carry out even-odd check intertexture LDPC code word.

Therefore, can be to the LDPC code word by even-odd check intertexture by group interleaver when even-odd check, which interweaves, to be performed Perform and interweave by group, and when even-odd check interweaves and is not performed, can be to not by carry out even-odd check intertexture by group interleaver LDPC code word perform by group interweave.

In detail, by group interleaver can be to parity interleaver in units of bit group output be interleaved.

For such purpose, the LDPC code stroke exported from parity interleaver can be divided into by group interleaver multiple Bit group.As a result, the LDPC Parity Check Bits from parity interleaver output are divided into multiple bit groups.

In detail, LDPC can be passed through by what is exported from parity interleaver based on following equation 37 by group interleaver The bit of codingIt is divided into N_group(=N_inner/ 360) individual bit group.

X_j={ u_k| 36O × j≤k ＜ 36O × (j+1), 0≤k ＜ N_inner, wherein, 0≤j ＜ N_group...(37)

In equation 37 more than, X_jRepresent j-th bit group.

Figure 12 shows that the LDPC code stroke that will be exported from parity interleaver is divided into the example of multiple bit groups.

Reference picture 12, LDPC code word are divided into N_group(=N_inner/ 360) individual bit group, each bit group X_jBy 360 Bit is formed, wherein, 0≤j ＜ N_group。

As a result, by K_ldpcThe LDPC information bits that individual bit is formed can be divided into K_ldpc/ 360 bit groups, by N_inner-K_ldpcThe LDPC Parity Check Bits that individual bit is formed are divided into N_inner-K_ldpc/ 360 bit groups.

In addition, the LDPC code word exported from parity interleaver is performed by a group intertexture by group interleaver.

In this case, intertexture is not performed to LDPC information bits by group interleaver, and can be only to LDPC odd evens school Test bit and perform and interweave to change the order for the multiple bit groups for being formed LDPC Parity Check Bits.

As a result, the LDPC information bits among LDPC bits can not be interweaved by group interleaver, but LDPC bits Among LDPC Parity Check Bits can be interweaved by group interleaver.In this case, LDPC Parity Check Bits can be with Group is interleaved for unit.

In detail, LDPC code word that can be based on following equation 38 to being exported from parity interleaver by group interleaver Perform and interweave by group.

Y_j=X_j, 0≤j ＜ K_ldpc/360

Y_j=X_πp(j), K_ldpc/ 360≤j ＜ N_group ...(38)

Here, X_jRepresent to form j-th of bit group among multiple bit groups of LDPC code word (that is, not by by a group intertexture J-th bit group), Y_jRepresent j-th of bit group by interweaving by group.In addition, π_p(j) represent to be directed to the displacement to interweave by group Sequentially.

Replacement sequence can be limited based on following table 9 and table 10.Here, table 9 shows thin in L1- basic models and L1- Section pattern 1 and 2 times parity portions are shown for the strange of L1- detail modes 3,4,5,6 and 7 by a group intertexture pattern, table 10 Press a group intertexture pattern in even parity check part.

In this case, by group interleaver can according to the corresponding modes shown in following table 9 and table 10 come determine by Group intertexture pattern.

[table 9]

[table 10]

Hereinafter, for pressing a group intertexture pattern under L1- detail modes 2 as example, group intertexture is pressed into description The operation of device.

Under L1- detail modes 2, LDPC encoder 315 is performed with 3/15 code check to 3240 LDPC information bits LDPC is encoded to produce 12960 LDPC Parity Check Bits.In this case, LDPC code word can compare special-shaped by 16200 Into.

Each bit group is formed by 360 bits, as a result, the LDPC code word formed by 16200 bits is divided Into 45 bit groups.

Here, because the quantity that the quantity of LDPC information bits is 3240, LDPC Parity Check Bits is 12960, therefore 0th bit group to the 8th bit group corresponds to LDPC information bits, and the 9th bit group to the 44th bit group corresponds to LDPC odd evens school Test bit.

In this case, by group interleaver be not based on the above equation 38 and table 9 to form LDPC information bits ratio Special group (that is, the 0th bit group to the 8th bit group) performs intertexture, but can be in units of group to being formed LPDC even-odd checks ratio Special bit group (that is, the 9th bit group to the 44th bit group) is interleaved to change the suitable of the 9th bit group to the 44th bit group Sequence.

In detail, under the L1- detail modes 2 in the table 9 more than, the equation 28 of the above can be such as Y₀=X₀,Y₁= X₁,...,Y₇=X₇,Y₈=X₈,Y₉=X_πp(9)=X₉,Y₁₀=X_πp(10)=X₃₁,Y₁₁=X_πp(11)=X₂₃,...,Y₄₂=X_πp(42)= X₂₈,Y₄₃=X_πp(43)=X₃₉,Y₄₄=X_πp(44)=X₄₂It is expressed like that.

Therefore, the order of the 0th bit group to the 8th bit group including LDPC information bits is not changed by group interleaver, but It is the order that can change the 9th bit group to the 44th bit group including LDPC Parity Check Bits.

In detail, the order of bit group can be changed from the 9th bit group to the 44th bit group by group interleaver so that the 9th Bit group is located at the 9th position, and the 31st bit group is located at the 10th position, and the 23rd bit group is located at the 11st position ..., the 28th bit group Positioned at the 42nd position, the 39th bit group is located at the 43rd position, and the 42nd bit group is located at the 44th position.

As described below, because puncturer 217 and puncturer 318 perform censoring since last Parity Check Bits, Therefore Parity Check Bits group can be replaced by even-odd check is arranged with the reverse order of censoring pattern.That is, will be by First bit group of censoring is located at last bit group.

Aforementioned exemplary describes only Parity Check Bits and is interleaved, and this is only an example.That is, even-odd check Displacer 215 and even-odd check displacer 316 can be also interleaved to LDPC information bits.In this case, even-odd check Displacer 215 and even-odd check displacer 316 can have and friendship to being interleaved and exporting with tagged LDPC information bits The LDPC information bits of same sequence before knitting so that the order of LDPC information bits is not changed.

Duplicator 216 and duplicator 317 can in the LDPC code word by even-odd check displacement in LDPC information bits At least some bits of opening position afterwards are repeated, and LDPC code word (that is, the LDPC including repetition bits that will be repeated Code word bits) export to puncturer 217 and puncturer 318.Duplicator 317 can also export the LDPC code word repeated to additional strange Even parity check generator 319.In this case, the LDPC code word of repetition can be used to produce in additional parity generator 319 Additional parity-check bits.

In detail, duplicator 216 and duplicator 317 can be repeated after LDPC information bits predetermined quantity LDPC it is strange Even parity check bit.That is, duplicator 216 and duplicator 317 can add the weight of predetermined quantity after LDPC information bits Multiple LDPC Parity Check Bits.Therefore, in LDPC code word, the LDPC Parity Check Bits repeated are located at LDPC information bits Between LDPC Parity Check Bits.

Therefore, because the bit in the predetermined quantity after repetition in LDPC code word can be repeated and extraly sent To receiver 200, therefore aforementioned operation can be referred to as repeating.

Term " addition " represents to arrange repetition bits between LDPC information bits and LDPC Parity Check Bits so that ratio Spy is repeated.

Repetition can be performed only to L1- basic models 1 and L1- detail modes 1, and other patterns can not be performed.At this In the case of kind, duplicator 216 and duplicator 317 do not perform repetition, and can be defeated by the LDPC code word by even-odd check displacement Go out to puncturer 217 and puncturer 318.

Hereinafter, will be described in further detail for performing the method repeated.

Duplicator 216 and duplicator 317 can calculate extraly being sent out for each LDPC code word based on following equation 39 The quantity N of the bit sent_repeat。

In equation 39 more than, C has fixed numerical value, and D can be even number.Equation 39 with reference to more than, it will be appreciated that , can be by the way that C to be multiplied by given N by the quantity of the bit repeated_outerAnd D is added to calculate.

It can be selected for the parameter C and parameter D repeated based on following table 11.That is, duplicator 216 and repetition Device 317 can determine C and D as shown in following table 11 based on corresponding modes.

[table 11]

In addition, duplicator 216 and duplicator 317 can be to N_repeatIndividual LDPC Parity Check Bits are repeated.

In detail, N is worked as_repeat≤N_{ldpc_parity}When, as shown in Figure 13, duplicator 216 and duplicator 317 can will be through The preceding N crossed in the LDPC Parity Check Bits of even-odd check displacement_repeatIndividual bit is added to LDPC information bits.That is, Duplicator 216 and duplicator 317 can add the LDPC even-odd checks ratio by even-odd check displacement after LDPC information bits First LDPC Parity Check Bits among spy, as N_repeatIndividual LDPC Parity Check Bits.

Work as N_repeat＞ N_{ldpc_parity}When, as shown in Figure 14, duplicator 216 and duplicator 317 can will pass through even-odd check The N of displacement_{ldpc_parity}Individual LDPC Parity Check Bits are added to LDPC information bits, and can be by N_repeat-N_{ldpc_parity}It is individual The LDPC Parity Check Bits replaced by even-odd check are additionally added to the N added first_{ldpc_parity}Individual LDPC odd evens Check bit.That is, duplicator 216 and duplicator 317 can add all process odd even schools after LDPC information bits The LDPC Parity Check Bits of displacement are tested, and additionally addition is passed through after the LDPC Parity Check Bits added first The 1st LDPC Parity Check Bits among the LDPC Parity Check Bits of even-odd check displacement are to N_repeat-N_{ldpc_parity}It is individual LDPC Parity Check Bits.

Therefore, under L1- basic models 1 and L1- detail modes 1, additional N_repeatIndividual bit can in LDPC code word quilt Select and sent.

Puncturer 217 and puncturer 318 can be to included from duplicator 216 and the LDPC code word of the output of duplicator 317 LDPC Parity Check Bits in some LDPC Parity Check Bits carry out censoring, and by truncated LDPC code word (that is, the remaining LDPC code word bit in addition to the bit being truncated, and the LDPC code also referred to as after censoring Word) it is output to zero remover 218 and zero remover 321.In addition, puncturer 318 can by with the LDPC even-odd checks ratio that is truncated The information (for example, the quantity for the bit being truncated and position etc.) of peculiar pass is supplied to additional parity generator 319.At this In the case of kind, additional parity generator 319 can be based on this generation additional parity-check bits.

As a result, after even-odd check displacement, some LDPC Parity Check Bits can be truncated.

In this case, the LDPC Parity Check Bits being truncated are not sent out in the frame that L1 signaling bits are sent Send.In detail, the LDPC Parity Check Bits being truncated are not sent in the present frame that L1 signaling bits are sent, one In the case of a little, the LDPC Parity Check Bits being truncated can be sent in the frame before present frame, and this will be with reference to additional parity Check bit generator 319 describes.

For such purpose, puncturer 217 and puncturer 318 can determine that the LDPC that will be truncated of each LDPC code word The size of the quantity of Parity Check Bits and an encoding block.

In detail, it is strange can to calculate the LDPC that will be truncated based on following equation 40 for puncturer 217 and puncturer 318 The provisional number N of even parity check bit_{punc_temp}.That is, for given N_outer, puncturer 217 and puncturer 318 can bases The provisional number N for the LDPC Parity Check Bits that will be truncated is calculated in following equation 40_{punc_temp}。

Equation 40 with reference to more than, the provisional number of the bit that will be truncated can be added by constant integer B from will contracting Subtract length (that is, K_ldpc-N_outer) be multiplied by the integer that the results of preset constant A values obtains and calculate.In the present example embodiment, It is apparent that constant A values with the quantity for the bit that will be truncated with the ratio of the quantity for the bit being contracted by is set, and It can need to be set in a variety of ways according to system.

B values are the values of the length of bit for representing even if foreshortened length also to will be truncated when being 0, and therefore, B values represent The minimum length that the bit being truncated can have.In addition, A values and B values are for adjusting the code check actually sent.That is, it is The situation of the length of length (that is, the length of L1 signalings) to information bit short situation or L1 signalings length is done some preparations, A The code check of value and B values for adjusting the actual transmission that will be reduced.

K above_1dpc, A and B list in the following table 12 for showing the parameter for censoring.Therefore, puncturer 217 The parameter for censoring can be determined with puncturer 318 according to corresponding modes as shown in following table 12.

[table 12]

Puncturer 217 and puncturer 318 can calculate the interim size of an encoding block as shown in following equation 41 N_{FEC_temp}.Here, according to the quantity N of the LDPC Parity Check Bits of corresponding modes_{ldpc_parity}Shown in table 12 as more than.

N_{FEC_temp}=N_outer+N_{Idpc_parity}-N_{punc_temp} ...(41)

In addition, puncturer 217 and puncturer 318 can calculate the size of an encoding block as shown in following equation 42 N_FEC。

In equation 42 more than, η_MoDIt is order of modulation.For example, when the basic signalings of L1- and L1- details signalings are according to phase When answering the pattern to be modulated by QPSK, 16-QAM, 64-QAM or 256-QAM, as shown in the table 12 more than, η_MoDCan be 2, 4th, 6 and 8.Equation 42 more than, NFEC can be the integral multiple of order of modulation.

In addition, puncturer 217 and puncturer 318 can calculate the LDPC odd evens school that will be truncated based on following equation 43 Test the quantity N of bit_punc。

N_punc=N_{punc_temp}-(N_FEC-N_{FEC_temp}) ...(43)

Here, N_puncIt is 0 or positive integer.In addition, N_FECIt is by from by K_sigIndividual information bit performs BCH and compiled The N that code and LDPC are encoded and obtained_outer+N_{1dpc_parity}Individual bit subtracts the N that will be truncated_puncIndividual bit and the block of information obtained Bit quantity.That is, N_FECIt is the number of the bit in addition to repetition bits among the bit actually sent Amount, and the quantity of the LDPC code word bit by reduction and censoring can be referred to as.

With reference to aforementioned processing, the quantity for zero bit that A can be multiplied by filling by puncturer 217 and puncturer 318 (that is, is reduced Length) and result is calculated into the provisional number N for the LDPC Parity Check Bits that will be truncated plus B_{punc_temp}。

In addition, puncturer 217 and puncturer 318 are based on N_{punc_temp}To calculate the LDPC after being formed in censoring and reducing The provisional number N of the LDPC code word bit of code word_{FEC_temp}。

In detail, LDPC information bits are encoded by LDPC, and by LDPC encode caused by LDPC even-odd checks ratio Spy is added to LDPC information bits to construct LDPC code word.Here, LDPC information bits include the basic signalings of L1- and L1- is thin The bit by Bose-Chaudhuri-Hocquenghem Code that section signaling is obtained by Bose-Chaudhuri-Hocquenghem Code, and in some cases, LDPC information bits may also include Zero bit of filling.

In this case, because zero bit of filling is encoded by LDPC, receiver 200 is then not sent to, therefore, LDPC code word (the LDPC code word (that is, the LDPC code word after reduction) i.e. in addition to zero bit of filling) by reduction can be by Formed by the bit and LDPC Parity Check Bits of Bose-Chaudhuri-Hocquenghem Code.

Therefore, the quantity and LDPC Parity Check Bits of puncturer 217 and puncturer 318 from the bit by Bose-Chaudhuri-Hocquenghem Code Quantity sum subtract the provisional numbers of the LDPC Parity Check Bits that will be truncated to calculate N_{FEC_temp}。

By censoring and the LDPC code word of reduction (that is, remaining LDPC code word bit after censoring and reduction) according to corresponding Pattern be mapped to constellation symbol, constellation by various modulation schemes (such as, QPSK, 16-QAM, 64-QAM or 256-QAM) Symbol can be sent to receiver 200 by frame.

Therefore, puncturer 217 and puncturer 318 are based on N_{FEC_temp}To determine the LDPC code after being formed in censoring and reducing The quantity N of the LDPC code word bit of word_FEC(wherein, N_FECIt is the integral multiple of order of modulation), and based on the LDPC after reduction Code word bits determine to need the quantity N of bit being truncated_puncTo obtain N_FEC。

When zero bit is not filled, LDPC code word can be by the bit Jing Guo Bose-Chaudhuri-Hocquenghem Code and LDPC Parity Check Bits shapes Into, and reduce and can be omitted.

In addition, under L1- basic models 1 and L1- detail modes, repetition is performed, and therefore, by reducing and censoring The quantity of LDPC code word is equal to N_FEC+N_repeat。

Puncturer 217 and puncturer 318 can be pair with the quantity that calculates as many LDPC Parity Check Bits delete Cut.

In this case, puncturer 217 and puncturer 318 can be to the rear N in all LDPC code words_puncIndividual bit is carried out Censoring.That is, puncturer 217 and puncturer 318 can since last LDPC Parity Check Bits censoring N_puncIndividual ratio It is special.

In detail, when repeating not to be performed, the LDPC code word by even-odd check displacement only includes compiling by LDPC LDPC Parity Check Bits caused by code.

In this case, puncturer 217 and puncturer 318 can be in all LDPC code words by even-odd check displacement Rear N_puncIndividual bit carries out censoring.Therefore, from last among LDPC Parity Check Bits caused by being encoded by LDPC The N that LDPC Parity Check Bits start_puncIndividual bit can be truncated.

When repeating to be performed, the LDPC code word replaced and repeated by even-odd check includes the LDPC even-odd checks repeated Bit and by LDPC encode caused by LDPC Parity Check Bits.

In this case, as shown in figs. 15 and 16, puncturer 217 and puncturer 318 can be respectively to all processes Rear N in the LDPC code word that even-odd check is replaced and repeated_puncIndividual bit carries out censoring.

In detail, the LDPC Parity Check Bits repeated are located at LDPC information bits and caused by being encoded by LDPC Between LDPC Parity Check Bits, and therefore puncturer 217 and puncturer 318 can be respectively to caused by be encoded by LDPC The N that last LDPC Parity Check Bits among LDPC Parity Check Bits start_puncIndividual bit carries out censoring.

In this way, puncturer 217 and puncturer 318 can be respectively to the N since last LDPC Parity Check Bits_puncIt is individual Bit carries out censoring.

N_puncIt is 0 or positive integer, repetition can be only applied to L1- basic models 1 and L1- detail modes 1.

Aforementioned exemplary describes repetition and is performed, and then censoring is performed, and this is only an example.In certain situation Under, after censoring is performed, repetition can be performed.

Additional parity generator 319 can select bit to produce additional parity from LDPC Parity Check Bits (AP) bit.

In this case, additional parity-check bits can be produced from based on the L1- details signaling sent in the current frame Selected in raw LDPC Parity Check Bits, and receiver is sent to by the frame (that is, previous frame) before present frame 200。

In detail, L1- details signaling is encoded by LDPC, by LDPC encode caused by LDPC Parity Check Bits added L1- details signaling is added to form LDPC code word.

In addition, censoring and reduction can be performed to LDPC code word, and the LDPC code word by censoring and reduction can be mapped To the frame of receiver 200 will be sent to.Here, when performing repetition according to corresponding modes, by censoring and the LDPC of reduction Code word may include the LDPC Parity Check Bits repeated.

In this case, can pass through with L1- details signaling corresponding to each frame together with LDPC Parity Check Bits Each frame is sent to receiver 200.The process censoring of L1- details signaling e.g., including corresponding with (i-1) frame and reduction LDPC code word be mapped to (i-1) frame to be sent to receiver 200, and including L1- details corresponding with the i-th frame The LDPC code word by censoring and reduction of signaling is mapped to the i-th frame to be sent to receiver 200.

Caused LDPC may be selected based on the L1- details signaling sent in the i-th frame in additional parity generator 319 At least some LDPC Parity Check Bits in Parity Check Bits, to produce additional parity-check bits.

In detail, by performing LDPC codings to L1- details signaling and one in caused LDPC Parity Check Bits A little LDPC Parity Check Bits are truncated, and are then not delivered to receiver 200.In this case, additional parity is produced Raw device 319 may be selected to encode and caused LDPC even-odd checks by performing LDPC to the L1- details signaling sent in the i-th frame At least some LDPC Parity Check Bits in the LDPC Parity Check Bits being truncated among bit, it is additional strange so as to produce Even parity check bit.

In addition, additional parity generator 319 may be selected that the LDPC odd evens of receiver 200 will be sent to by the i-th frame At least some LDPC Parity Check Bits in check bit are to produce additional parity-check bits.

In detail, will be mapped to that the i-th frame by LDPC odd evens included in censoring and the LDPC code word of reduction Check bit can be encoded according to corresponding modes only by LDPC caused by LDPC Parity Check Bits form, or by passing through LDPC Parity Check Bits caused by LDPC codings and the LDPC Parity Check Bits repeated are formed.

In this case, additional parity generator 319 may be selected to will be mapped to that the process censoring of the i-th frame and contracting At least some LDPC Parity Check Bits in the LDPC code word subtracted in included LDPC Parity Check Bits, it is additional to produce Parity Check Bits.

Additional parity-check bits can be sent to receiver 200 by the frame (that is, (i-1) frame) before the i-th frame.

Believe that is, transmitter 100 not only can will include L1- details corresponding with (i-1) frame by (i-1) frame The LDPC code word by censoring and reduction of order is sent to receiver 200, can will be also based on by (i-1) frame in the i-th frame The L1- details signaling of transmission and caused additional parity-check bits are sent to receiver 200.

In this case, the frame for sending additional parity-check bits can be present frame before frame among in the time The frame of upper foremost.

For example, additional parity-check bits have among the frame before present frame with the guiding of present frame identical it is main/ Minor release, and can be sent in time in the frame of foremost.

In some cases, additional parity generator 319 can not produce additional parity-check bits.

In this case, the basic signalings of L1- sent by present frame can be used in transmitter 100, are sent out to receiver 200 Send with the additional parity-check bits of the L1- details signalings for next frame whether by present frame by the relevant information of transmission.

For example, for present frame have identical guiding it is main/the L1- details signalings of the next frame of minor release it is attached The use of add parity check bit can pass through the field L1B_L1_Detail_ in the L1- basic parameters of present frame Additional_parity_mode is sent with signal.In detail, the L1B_L1_ in the L1- basic parameters of present frame When Detail_additional_parity_mode is arranged to " 00 ", for the additional parity of the L1- details signalings of next frame Check bit is not sent in the current frame.

In this way, in order to extraly improve the robustness of L1- details signalings, additional parity-check bits can be before present frame Transmission present frame L1- details signalings frame in sent.

Figure 17 shows to be directed to leading middle quilt of the additional parity-check bits in (i-1) frame of the L1- details signalings of the i-th frame The example of transmission.

Figure 17 shows to be divided into M block by segmentation by the L1 details signaling that the i-th frame is sent, and the block being partitioned into In each block encoded by FEC.

Therefore, M LDPC code word (that is, the odd even including LDPC information bit L1-D (i) _ 1 and its for L1-D (i) _ 1 The LDPC code word of check bit odd even ... including LDPC information bit L1-D (i) _ M and its odd even school for L1-D (i) _ M Test the LDPC code word of bit odd even) it is mapped to and will be sent to the i-th frame of receiver 200.

In this case, based on the L1- details signaling sent in the i-th frame and caused additional parity-check bits can Receiver 200 is sent to by (i-1) frame.

In detail, additional parity-check bits (namely based on the L1- details signaling sent in the i-th frame caused pin AP to L1-D (i) _ 1 ..., for L1-D (i) _ M AP) be mapped to and will be sent to (i-1) frame of receiver 200 It is leading.As the result using additional parity-check bits, the diversity gain for L1 signalings can be obtained.

Hereinafter, it will be described in detail the method for producing additional parity-check bits.

Additional parity-check bits generator 319 calculates the interim of additional parity-check bits based on following equation 44 Quantity N_{AP_temp}。

In addition, K represents additional parity-check bits and bit (that is, the structure of the encoded L1- details signaling blocks sent Into by repeating, censoring and the bit for having eliminated the L1- details signaling blocks of zero bit) total quantity half ratio Value.

In this case, K corresponds to the L1B_L1_Detail_additional_parity_mode of the basic signalings of L1- Field.Here, the L1B_L1_Detail_additional_ associated with the L1- details signaling of the i-th frame (that is, frame (#i)) Parity_mode value can be sent in (i-1) frame (that is, frame (#i-1)).

As described above, when L1 detail modes are 2,3,4,5,6 and 7, due to repeating not to be performed, therefore more than etc. In formula 44, N_repeatIt is 0.

In addition, additional parity generator 319 calculates the number of additional parity-check bits based on following equation 45 Measure N_AP.Therefore, the quantity N of additional parity-check bits_APIt can be the integral multiple of order of modulation.

Here,It is no more than x maximum integer.Here, η_MODIt is order of modulation.For example, when L1- details signaling according to When corresponding pattern is modulated by QPSK, 16-QAM, 64-QAM or 256-QAM, η_MODCan be 2,4,6 or 8.

Next, the bit that additional parity generator 319 can be selected and calculated in LDPC Parity Check Bits Quantity bit as many to produce additional parity-check bits.

In detail, when the quantity for the LDPC Parity Check Bits being truncated is equal to or more than the additional parity that will be generated During the quantity of check bit, additional parity generator 319 can be from first among the LDPC Parity Check Bits being truncated Individual LDPC Parity Check Bits start the bit of selection and the quantity calculated as many, to produce additional parity-check bits.

When the quantity for the LDPC Parity Check Bits being truncated is less than the quantity for the additional parity-check bits that will be generated When, additional parity generator 319 can select all LDPC Parity Check Bits being truncated first, and from LDPC code word In first LDPC Parity Check Bits among included LDPC Parity Check Bits start additionally to select with by from The number that the quantity for the additional parity-check bits being generated is subtracted to the quantity for the LDPC Parity Check Bits being truncated and obtained The bit of amount as many, to produce additional parity-check bits.

In detail, when repeating not to be performed, the included LDPC Parity Check Bits in the LDPC code word repeated Be by LDPC encode caused by LDPC Parity Check Bits.

In this case, additional parity generator 319 can select all LDPC even-odd checks being truncated first Bit, and since first LDPC Parity Check Bits among LDPC Parity Check Bits caused by being encoded by LDPC Additionally selection with by from the quantity for the additional parity-check bits being generated to be subtracted to the LDPC even-odd checks ratio being truncated Special quantity and the bit of the quantity that obtains as many, to produce additional parity-check bits.

Here, by LDPC encode caused by LDPC Parity Check Bits be divided into the LDPC even-odd checks not being truncated Bit and the LDPC Parity Check Bits being truncated.As a result, when the LDPC even-odd checks ratio caused by encoded by LDPC When first bit among spy starts have selected bit, according to the LDPC Parity Check Bits that are not truncated and it can be truncated The orders of LDPC Parity Check Bits selects bit.

When repeating to be performed, included LDPC Parity Check Bits are to repeat in the LDPC code word by repetition LDPC Parity Check Bits and by LDPC encode caused by LDPC Parity Check Bits.Here, the LDPC even-odd checks repeated Bit is located at LDPC information bits and encoded by LDPC and between caused LDPC Parity Check Bits.

In this case, additional parity generator 319 can select all LDPC even-odd checks being truncated first Bit, and since repeat LDPC Parity Check Bits among first LDPC Parity Check Bits additionally select with By subtracting the quantity for the LDPC Parity Check Bits being truncated from the quantity of additional parity-check bits the quantity one that obtains Bit more than sample, to produce additional parity-check bits.

Here, can be according to when bit is selected when first bit among the LDPC Parity Check Bits repeated Repetition bits and by LDPC encode and the sequential selection bit of caused LDPC Parity Check Bits.In addition, passing through LDPC Coding and within caused LDPC Parity Check Bits, according to the LDPC Parity Check Bits that are not truncated and can be truncated The orders of LDPC Parity Check Bits selects bit.

Hereinafter, reference picture 18 to Figure 20 is described more fully additional for producing according to exemplary embodiment The method of Parity Check Bits.

Figure 18 to Figure 20 is for describing to produce additional parity when repeating and being performed according to exemplary embodiment The diagram of the method for bit.In this case, the LDPC code word by repeating It can be expressed as shown in Figure 18.

First, N is worked as_AP≤N_puncWhen, as shown in Figure 19, additional parity generator 319 can be from the LDPC being truncated First LDPC Parity Check Bits among Parity Check Bits start to select N_APIndividual bit, to produce additional parity ratio It is special.

Therefore, for additional parity-check bits, the LDPC Parity Check Bits being truncatedIt can be chosen. That is, additional parity generator 319 can compare JP from first among the LDPC Parity Check Bits being truncated Begin selection N_APIndividual bit, to produce additional parity-check bits.

Work as N_AP＞ N_puncWhen, as shown in Figure 20, additional parity generator 319 selects all LDPC being truncated strange Even parity check bit.

Therefore, for additional parity-check bits, all LDPC Parity Check Bits being truncatedIt can be chosen.

In addition, additional parity generator 319 can be compiled from including the LDPC Parity Check Bits repeated and by LDPC Code and among the LDPC Parity Check Bits of caused LDPC Parity Check Bits additionally select before N_AP-N_puncIndividual bit.

That is, encoded due to the LDPC Parity Check Bits of repetition and by LDPC and caused LDPC even-odd checks Bit sequentially arranged, therefore additional parity generator 319 can be from the among the LDPC Parity Check Bits repeated One LDPC Parity Check Bits starts additionally to select N_AP-N_puncIndividual Parity Check Bits.

Therefore, for additional parity-check bits, LDPC Parity Check Bits Select with being attached.

In this case, the bit additionally selected can be added to previous selection by additional parity generator 319 Bit to produce additional parity-check bits.That is, as shown in Figure 20, additional parity generator 319 can incite somebody to action The LDPC Parity Check Bits additionally selected are added to the LDPC Parity Check Bits that are truncated to produce additional parity Bit.

As a result, additional parity-check bits are directed to, Can quilt Selection.

In this way, when the quantity for the bit being truncated is equal to or more than the quantity of additional parity-check bits, base can be passed through Bit is selected to produce additional parity-check bits among the bit being truncated in censoring order.However, in other cases, Can be by selecting all bits and N being truncated_AP-N_puncIndividual Parity Check Bits produce additional parity-check bits.

Due to the N when repeating not to be performed_repeat=0, it thus be accordingly used in and produce additional parity when repeating and not being performed The method of bit and the N in Figure 18 to Figure 20_repeat=0 situation is identical.

Additional parity-check bits can be by Bit Interleave, and is mapped to constellation.In this case, for additional The constellation of Parity Check Bits can pass through the constellation identical method with the L1- details signaling bits for sending in the current frame To produce, wherein, in the current frame, L1- details signaling bit is repeated, censoring and has eliminated zero bit.In addition, such as Shown in Figure 18, after constellation is mapped to, the transmission before additional parity-check bits can be added to present frame is current After L1- details signaling blocks in the frame of the L1- details signalings of frame.

Additional parity generator 319 can export additional parity-check bits to bit demultiplexer 323.

There can be both of which by group intertexture pattern as described above with described in table 9 and table 10, limit replacement sequence：First Pattern and second mode.

In detail, the B values in the equation 40 due to more than represent the minimum for the LDPC Parity Check Bits that will be truncated Length, therefore can be always truncated according to B values, the bit of predetermined quantity, the length without considering incoming signalling.For example, in L1- Under detail modes 2, because B=6036 and bit group are formed by 360 bits, therefore even if when foreshortened length is 0, also extremely It is rareIndividual bit group is always truncated.

In this case, due to performing censoring since last LDPC Parity Check Bits, therefore passed through from forming Cross by the predetermined quantity that starts of last bit group among group multiple bit groups of the LDPC Parity Check Bits to interweave Bit group can be always truncated, without considering foreshortened length.

For example, under L1- detail modes 2,36 bit groups of the LDPC Parity Check Bits by interweaving by group are formed Among last 16 bit groups can always be truncated.

As a result, limit the bit being always truncated by some patterns expression in group intertexture pattern of replacement sequence Group, therefore, both of which is divided into by a group intertexture pattern.In detail, by the restriction in group intertexture pattern except by always It is that the pattern of the remaining bits group outside the bit group being truncated is referred to as first mode, and limits the ratio that will be always truncated The pattern of spy's group is referred to as second mode.

For example, under L1- detail modes 2, due to being defined by group intertexture pattern as in table 9 above, therefore table Show the bit group being located at after by group intertexture in the 9th bit group to the 28th bit group without by group index (that is, the Y to interweave₉ =X_πp(9)=X₉,Y₁₀=X_πp(10)=X₃₁,Y₁₁=X_πp(11)=X₂₃,...,Y₂₆=X_πp(26)=X₁₇,Y₂₇=X_πp(27)=X₃₅,Y₂₈ =X_πp(28)=X₂₁) pattern can be first mode, and represent by group interweave after positioned at the 29th bit group to the 44th ratio Bit group in special group is without by group index (that is, the Y to interweave₂₉=X_πp(29)=X₂₀,Y₃₀=X_πp(30)=X₂₄,Y₃₁=X_πp(31) =X₄₄,...,Y₄₂=X_πp(42)=X₂₈,Y₄₃=X_πp(43)=X₃₉,Y₄₄=X_πp(44)=X₄₂) pattern be referred to as second mode.

As described above, always second mode limits the bit group that will be truncated in the current frame regardless of foreshortened length, And first mode limits the bit group that ground censoring will be attached when foreshortened length is long so that first mode can be used for determining The LDPC Parity Check Bits that will be sent in the current frame after censoring.

In detail, according to the quantity for the LDPC Parity Check Bits that will be truncated, except the LDPC being always truncated is strange Outside even parity check bit, more LDPC Parity Check Bits can be by extraly censoring.

For example, under L1- detail modes 2, when the quantity for the LDPC Parity Check Bits that will be truncated is 7200,20 Bit group needs to be truncated, and therefore in addition to by be always truncated 16 bit groups, it is also necessary to extraly censoring four (4) individual bit group.

In this case, extraly the individual bit group in four (4) of censoring correspond to by group interweave after positioned at the 25th to The bit group of 28th position, and because these bit groups according to first mode determine and (that is, belong to first mode), therefore One pattern can be used for determining the bit group being truncated.

That is, when LDPC Parity Check Bits are truncated the minimum more than the LDPC Parity Check Bits that will be truncated During value, it is located at according to which bit group and the bit group being always truncated is determined which bit group will be deleted extraly later Cut.As a result, it is determined that be truncated bit group when, according to censoring direction, it is contemplated that limit and be located at and will always be truncated The first mode of bit group after bit group.

That is, such as in aforementioned exemplary, when the quantity for the LDPC Parity Check Bits that will be truncated is 7200, remove By outside be always truncated 16 bit groups, extraly the individual bit group of censoring four (4) (that is, is being performed it by a group intertexture It is located at the bit group of the 28th, the 27th, the 26th and the 25th opening position afterwards).Here, it is located at the 25th to the 28th after by group intertexture The bit group put determines according to first mode.

As a result, first mode can be considered for determining the bit group that will be truncated.In addition, except being truncated Remaining LDPC Parity Check Bits outside LDPC Parity Check Bits are sent by present frame, and therefore, first mode can quilt Consider the bit group for determining to be sent in the current frame.

Second mode can be used for determining the additional parity-check bits that will be sent in previous frame.

In detail, because the bit group for being confirmed as always being truncated always is truncated, then not in the current frame Sent, therefore these bit groups only need to be located at the position that bit is always truncated after by group intertexture.Therefore, these compare Where it is unessential that special group after by group intertexture if being located at.

For example, under L1- detail modes 2, by before group interweaving positioned at the 20th, the 24th, the 44th ..., the 28th, the 39th with And the 42nd opening position bit group by group interweave after only need to be located at the 29th bit group to the 44th bit group.Therefore, these Where it is unessential that bit group if being located at.

The second mode for the bit group being always truncated is used to identify the bit group that will be truncated in this way, limiting.Therefore, It is insignificant in censoring operation to limit the order between bit group under the second mode, and therefore, restriction will be always truncated The second mode of bit group can be considered to be not used in censoring.

However, in order to determine additional parity-check bits, the bit group that will be always truncated within these bit groups Position need be considered.

In detail, due to by first bit among the LDPC Parity Check Bits being truncated selection with The bit of predetermined quantity as many produces additional parity-check bits, therefore can be according to the LDPC Parity Check Bits being truncated Quantity and the quantity by the additional parity-check bits being generated, select at least some in the bit group that will always be truncated Included bit in bit group, as at least some additional parity-check bits in additional parity-check bits.

That is, when additional parity-check bits are selected over the quantity of the bit group according to first mode restriction When, due to being sequentially selected additional parity-check bits since the beginning of second mode, therefore with regard to additional parity For the selection of bit, the order for belonging to the bit group of second mode is meaningful.As a result, limiting always to be truncated The second mode of bit group can be considered for determining additional parity-check bits.

For example, under L1- detail modes 2, the total quantity of LDPC Parity Check Bits is 12960, by what is be always truncated The quantity of bit group is 16.

In this case, second mode can be used for according to by from the quantity of all LDPC Parity Check Bits subtract by The quantity of the LDPC Parity Check Bits being truncated and result will be subtracted each other plus the additional parity-check bits that will be generated Whether quantity and the value that obtains more than 7200 produce additional parity-check bits.Here, 7200 be to form LDPC even-odd checks Among the bit group of bit except by the quantity of the LDPC Parity Check Bits in addition to the bit group being always truncated.Namely Say, 7200=(36-16) × 360.

In detail, it is equal to or less than 7200 (that is, 12960-N when subtracting each other and be added the value to obtain more than_punc+ N_AP≤ 7200) when, additional parity-check bits can be produced according to first mode.

However, when the value for subtracting each other and being added to obtain more than is more than 7200 (that is, 12960-N_punc+N_AP＞ 7200) When, additional parity-check bits can be produced according to first mode and second mode.

In detail, 12960-N is worked as_punc+N_APDuring ＞ 7200, for additional parity-check bits, it may be alternatively located at from quilt In the bit group for the 28th opening position that first LDPC Parity Check Bits among the LDPC Parity Check Bits of censoring start Included bit, and may be alternatively located at included bit since the bit group of the pre-position the 29th position.

Here, can be according to the quantity of the LDPC Parity Check Bits being truncated and the additional parity-check bits that will be generated Quantity determine the bit group belonging to first LDPC Parity Check Bits among the LDPC Parity Check Bits being truncated And the bit group of the pre-position is (that is, when strange from first LDPC among the LDPC Parity Check Bits being truncated When even parity check bit starts to be sequentially selected, the bit group belonging to the LDPC Parity Check Bits of final choice).

In this case, determine to be located at from the among the LDPC Parity Check Bits being truncated according to first mode The bit group for the 28th opening position that one LDPC Parity Check Bits starts, determine to be located at from the 29th position according to second mode The bit group of the pre-position of beginning.

As a result, additional parity-check bits are determined according to first mode and second mode.

In this way, first mode can be used for determination that the additional parity-check bits being generated and the LDPC that will be truncated are strange Even parity check bit, no matter can be used for determining will the additional parity-check bits that be generated and will be by puncturer 217 for second mode With the quantity of the Parity Check Bits of the censoring of puncturer 318 how the LDPC Parity Check Bits that will be always truncated.

Aforementioned exemplary describes includes first mode and second mode by group intertexture pattern, and this is being deleted just for the sake of convenient Explanation in terms of cutting with additional parity.That is, a pattern can be considered as without being divided by a group intertexture pattern Into first mode and second mode.In this case, can be considered as being directed to both censoring and additional parity by a group intertexture Performed using a pattern.

The value (quantity for the LDPC Parity Check Bits such as, being truncated) used in aforementioned exemplary is only example Value.

Zero remover 218 and zero remover 321 can be from outputs from the LDPC code word of puncturer 217 and puncturer 318 Bit demultiplexer is output to except zero bit filled by zero padding device 213 and zero padding device 314, and by remaining bit 219 and bit demultiplexer 322.

Here, go division operation be not only remove filling zero bit, and may also include output LDPC code word in except Remaining bits outside zero bit of filling.

In detail, zero remover 218 and zero remover 321 can remove is filled by zero padding device 213 and zero padding device 314 K_ldpc-N_outerIndividual zero bit.Therefore, K_ldpc-N_outerZero bit of individual filling is removed, and therefore can be not delivered to and be connect Receive device 200.

For example, as shown in Figure 21, it is assumed that the first bit group, the 4th ratio among multiple bit groups of composition LDPC code word All bits in special group, the 5th bit group, the 7th bit group and the 8th bit group are by zero bit padding, in the second bit group Some bits by zero bit padding.

In this case, zero remover 218 and zero remover 321, which can remove, is filled into the first bit group, the second bit Group, the 4th bit group, the 5th bit group, zero bit of the 7th bit group and the 8th bit group.

In this way, when zero bit is removed, as shown in Figure 21, can retain by K_sigIndividual information bit (that is, K_sigIndividual L1- Basic signaling bit and K_sigIndividual L1- details signaling bit), 168 BCH Parity Check Bits (that is, BCHFEC) and N_inner- K_ldpc-N_puncOr N_inner-K_ldpc-N_punc+N_repeatThe LDPC code word that individual Parity Check Bits are formed.

That is, when repeating to be performed, the length of all LDPC code words becomes N_FEC+N_repeat.Here, N_FEC= N_outer+N_{ldpc_parity}-N_punc.However, under the pattern for repeating not to be performed, the length of all LDPC code words becomes N_FEC。

Bit demultiplexer 219 and bit demultiplexer 322 can be to from zero remover 218 and the outputs of zero remover 321 Bit is interleaved, and the bit of intertexture is demultiplexed, and then exports them to constellation mapper 221 and constellation mapper 324。

For this purpose, bit demultiplexer 219 and bit demultiplexer 322 may include block interleaver (not shown) and Demultiplexer (not shown).

First, the block interleaving scheme performed in block interleaver figure 22 illustrates.

In detail, the N after zero bit is removed_FECOr N_FEC+N_repeatThe bit of length continuously can be write by row Enter in block interleaver.Here, the quantity of the row of block interleaver is equal to order of modulation, and capable quantity is N_FEC/η_MODOr (N_FEC+ N_repeat)/η_MOD。

In addition, in read operation, the bit of a constellation symbol can be sequentially read along line direction to be input into Demultiplexer.It is described to operate the last column that can continue until row.

That is, N_FECOr (N_FEC+N_repeat) individual bit can be written into since the first row of first row along column direction In multiple row, and bit in a plurality of columns is write along line direction from the first row in multiple row to last column by order Read on ground.In this case, the bit read in the same row may make up a modulation symbol.

Demultiplexer can demultiplex to the bit exported from block interleaver.

In detail, before bit is mapped to constellation, demultiplexer can be to by every in the bit group of block interleaving Individual bit group (that is, the bit exported when being read by bit in same a line in bit group in block interleaver) is solved Multiplexing.

In this case, two kinds of mapping rulers may be present according to order of modulation.

In detail, when QPSK is used to modulate, because the reliability of the bit within constellation symbol is identical, therefore demultiplex De-multiplex operation is not performed to bit group with device.Therefore, the bit group for reading and exporting from block interleaver is mapped to QPSK Symbol, without de-multiplex operation.

However, when high order modulation is by use, demultiplexer can be based on following equation 46 come to being read from block interleaver And the bit group exported performs demultiplexing.That is, bit group can be mapped to qam symbol according to following equation 46.

S_{demux_in(i)}={ b_i(0), b_i(1), b_i..., b (2)_i(η_MOD- 1) },

S_{demux_out(i)}={ c_i(0), c_i(1), c_i..., c (2)_i(η_MOD- 1) },

c_i(0)=b_i(i% η_MOD)c_i(1)=b_i((i+1) % η_MOD) ..., c_i(η_MOD- 1)=b_i((i+η_M0D-1) % η_MOD)

...(46)

In equation 46 more than, % represents modulo operation, η_MODIt is order of modulation.

In addition, i is the corresponding bit group index of line index with block interleaver.That is, it is mapped in qam symbol Each qam symbol output bit group S_{demux_out(i)}Can be according to bit group index i in S_{demux_in(i)}It is middle by cyclic shift.

Figure 23 shows to perform 16- non-uniform constellations (16-NUC) (that is, NUC 16-QAM) example of bit demultiplexing.Institute State operation to be continued, untill all bit groups in block interleaver are read.

Bit demultiplexer 323 can perform to the additional parity-check bits exported from additional parity generator 319 Operation identical with being performed by bit demultiplexer 219 and bit demultiplexer 322 operates, and will pass through block interleaving and conciliate The bit of multiplexing is exported to constellation mapper 325.

Constellation mapper 211, constellation mapper 324 and constellation mapper 325 can will be from bit demultiplexer 219, bits The bit that demultiplexer 322 and bit demultiplexer 323 export is respectively mapped to constellation symbol.

That is, each in constellation mapper 211, constellation mapper 324 and constellation mapper 325 can be according to corresponding Pattern using constellation come by S_{demux_out(i)}It is mapped to cell word.Here, S_{demux_out(i)}Can be by with identical with order of modulation The bit of quantity form.

In detail, constellation mapper 211, constellation mapper 324 and constellation mapper 325 can make according to corresponding pattern It will be demultiplexed with QPSK, 16-QAM, 64-QAM, 256-QAM etc. from bit demultiplexer 219, bit demultiplexer 322 and bit The bit map that device 323 exports is to constellation symbol.

In this case, NUC can be used in constellation mapper 211, constellation mapper 324 and constellation mapper 325.Also To say, constellation mapper 211, constellation mapper 324 and constellation mapper 325 can be used NUC 16-QAM, NUC 64-QAM or NUC 256-QAM.According to table 4 of the corresponding pattern applied to the modulation scheme of the basic signalings of L1- and L1- details signalings more than In be illustrated.

Meanwhile constellation symbol mapped can be sent to receiver 200 by transmitter 100 to frame and by the symbol after mapping.

In detail, transmitter 100 can pair with from constellation mapper 221 and constellation mapper 324 output L1- believe substantially Each corresponding constellation symbol in order and L1- details signalings is mapped, and will be exported from constellation mapper 325 with adding very Leading symbol of the constellation symbol mapped to frame corresponding to even parity check bit.

In this case, transmitter 100 caused based on the L1- details signaling sent in the current frame will can add Parity Check Bits are mapped to the frame before present frame.

That is, transmitter 100 can reflect the LDPC code word bit including the basic signalings of L1- corresponding with the i-th -1 frame The i-th -1 frame is mapped to, by the LDPC code word bit map including L1- details signaling corresponding with the i-th -1 frame to the i-th -1 frame, and Extraly will be by being selected from based on L1- details signaling corresponding with the i-th frame in caused LDPC Parity Check Bits And caused additional parity-check bits are mapped to the i-th -1 frame and the bit after mapping can be sent into receiver 200.

In addition, in addition to L1 signalings, transmitter 100 can also map the data into the data symbol of frame, and will include The frame of L1 signalings and data is sent to receiver 200.

In this case, because L1 signalings include the signaling information relevant with data, therefore each data are mapped to The signaling relevant with data is mapped to the leading of respective frame.For example, transmitter 100 can be by including with being mapped to the i-th frame The L1 protocol mappings of the relevant signaling information of data are to the i-th frame.

As a result, receiver 200 can be used obtains data and processing data from the signaling that frame obtains from corresponding frame.

Figure 24 and Figure 25 is the block diagram for describing the configuration of the receiver according to exemplary embodiment.

In detail, as shown in Figure 24, receiver 200 may include the constellation demapping for handling the basic signalings of L1- Device 2410, multiplexer 2420, log-likelihood ratio (LLR) inserter 2430, LLR combiners 2440, even-odd check solution displacer 2450th, LDPC decoder 2460, zero remover 2470, BCH decoders 2480 and descrambler 2490.

In addition, as shown in Figure 25, receiver 200 may include the constellation de-mapping device 2511 for handling L1 details signalings With 2512, multiplexer 2521 and 2522, LLR inserters 2530, LLR combiners 2540, even-odd check solution displacer 2550, LDPC Decoder 2560, zero remover 2570, BCH decoders 2580, descrambler 2590 and solution dispenser 2595.

Here, the component shown in Figure 24 and Figure 25 is that execution is corresponding with the function of the component shown in Fig. 8 and Fig. 9 respectively Function component, this is only an example, in some cases, some components in component can be omitted and change and Other components can be added.

The guiding of frame can be used to obtain frame synchronization in receiver 200, and is used to handle L1- using included in guiding Leading reception L1- basic signaling of the information of basic signaling from frame.

In addition, receiver 200 can be used in the basic signalings of L1- the included information for being used to handle L1- details signalings from Leading reception L-1 details signalings, and use the broadcast number required for data symbol reception user of the L1- details signaling from frame According to.

Therefore, receiver 200 can determine that transmitter 100 use be used for handle the basic signalings of L1- and L1- details signalings Pattern, the signal received according to the mode treatment of determination from transmitter 100 is to receive the basic signalings of L1- and L1- details signalings. For such purpose, receiver 200 can be prestored with the information of relating to parameters used in transmitter 100 with according to corresponding Pattern handle signaling.

In this way, the basic signalings of L1- and L1- details signaling can sequentially be obtained from leading.In Figure 24 and Figure 25 description In, for the convenience of explanation, the component for performing identical function will be described together.

Constellation de-mapping device 2510, constellation de-mapping device 2611 and constellation de-mapping device 2612 from transmitter 100 to connecing The signal of receipts is demodulated.

In detail, constellation de-mapping device 2510, constellation de-mapping device 2611 and constellation de-mapping device 2612 are difference Constellation mapper 211, constellation mapper 324 and 325 corresponding component of constellation mapper with transmitter 100, and can to from The signal that transmitter 100 receives is demodulated and produces value corresponding with the bit sent from receiver 100.

That is, as described above, transmitter 100 is believed by the LDPC code word including the basic signalings of L1- and including L1- details The LDPC code word of order is mapped to the leading of frame, and the LDPC code word after mapping is sent into receiver 200.In addition, at some In the case of, additional parity-check bits can be mapped to the leading of frame and be sent to the bit after mapping and connect by transmitter 100 Receive device 200.

As a result, constellation de-mapping device 2510 and constellation de-mapping device 2611 can be produced with including the basic signalings of L1- LDPC code word bit and including corresponding to the LDPC code word bit of L1- details signalings value.In addition, constellation de-mapping device 2612 can produce Raw value corresponding with additional parity-check bits.

For this purpose, receiver 200 can prestore basic to L1- according to corresponding pattern with by transmitter 100 Signaling, L1- details signaling and additional parity-check bits are modulated the relevant information of used modulation scheme.Therefore, star Seat de-mapping device 2510, constellation de-mapping device 2611 and constellation de-mapping device 2612 can be according to corresponding patterns to from transmitter 100 signals received are demodulated to produce value corresponding with LDPC code word bit and additional parity-check bits.

Value corresponding with the bit sent from transmitter 100 be the bit based on reception be 0 and 1 probability and calculate Value, alternatively, probability also is used as value corresponding with each bit in itself.As another example, described value can also be seemingly So than (LR) or LLR value.

In detail, LR values can represent from transmitter 100 send bit be 0 probability and the bit be 1 probability Ratio, LLR value can be represented by the bit sent from transmitter 100 being 0 probability and the bit is that 1 probability takes pair The value for counting and obtaining.

Aforementioned exemplary uses LR values or LLR value, and this is only an example.According to another exemplary embodiment, except LR Or the signal received outside LLR value can be used as in itself.

Multiplexer 2520, multiplexer 2621 and multiplexer 2622 are to from constellation de-mapping device 2510, constellation de-mapping device 2611 and constellation de-mapping device 2612 export LLR value perform multiplexing.

In detail, multiplexer 2520, multiplexer 2621 and multiplexer 2622 are demultiplexed with the bit of transmitter 100 Device 219, bit demultiplexer 322 and component corresponding to bit demultiplexer 323, and can perform respectively and bit demultiplexer 219th, operated corresponding to the operation of bit demultiplexer 322 and bit demultiplexer 323.

For such purpose, receiver 200 can prestore is used with the execution of transmitter 100 demultiplexing and block interleaving Relating to parameters information.Therefore, multiplexer 2520, multiplexer 2621 and multiplexer 262 can couple LLRs corresponding with cell word Value oppositely performs the demultiplexing and block interleaving of bit demultiplexer 219, bit demultiplexer 322 and bit demultiplexer 323 Operation, so that bitwise a pair LLR value corresponding with cell word is multiplexed.

LLR value for censoring and the bit of reduction can be inserted into by LLR inserters 2530 and LLR inserters 2630 respectively The LLR value exported from multiplexer 2520 and multiplexer 2621.In this case, LLR inserters 2530 and LLR inserters 2630 Predetermined LLR value can be inserted between the LLR value exported from multiplexer 2520 and multiplexer 2621, or be inserted into from multiplexer 2520 and multiplexer 2621 export LLR value head or afterbody.

In detail, LLR inserters 2530 and LLR inserters 2630 be respectively with zero remover 218 of transmitter 100 and 321 and puncturer 217 and 318 corresponding to component, and can perform respectively and zero remover 218 and 321 and puncturer 217 With 318 operation corresponding to operation.

First, LLR value corresponding with zero bit can be inserted into LDPC code by LLR inserters 2530 and LLR inserters 2630 The position of zero bit is filled in word.In this case, with zero bit (that is, zero bit of reduction) of filling corresponding to LLR value Can be ∞ or-∞.However, ∞ or-∞ is theoretic value, but it can essentially be the LLR value used in receiver 200 Maximum or minimum value.

For such purpose, receiver 200 can be prestored with transmitter 100 according to the corresponding bit of Pattern Fill zero The relevant information of used parameter and/or pattern.Therefore, LLR inserters 2530 and LLR inserters 2630 can be according to corresponding Pattern determines to fill the position of zero bit in LDPC code word, and LLR value corresponding with zero bit of reduction is inserted into pair In the position answered.

In addition, LLR value corresponding with the bit being truncated can be inserted into by LLR inserters 2530 and LLR inserters 2630 Position of the bit being truncated in LDPC code word.In this case, LLR value corresponding with the bit being truncated can be 0.

For such purpose, receiver 200 can prestore performs censoring institute with transmitter 100 according to corresponding pattern The relevant information of the parameter and/or pattern that use.Therefore, LLR inserters 2530 and LLR inserters 2630 can be according to corresponding moulds Formula determines the length of LDPC Parity Check Bits being truncated and corresponding LLR value is inserted into LDPC Parity Check Bits quilts The position of censoring.

When among additional parity-check bits additional parity-check bits be selected from the bit being truncated when, LLR inserters 2630 can be by corresponding with the additional parity-check bits received LLR value (rather than the bit for being truncated LLR value ' 0') be inserted into the position for the bit being truncated.

LLR combiners 2540 and LLR combiners 2640 will can export from LLR inserters 2530 and LLR inserters 2630 LLR value is combined with the LLR value exported from multiplexer 2622 and (that is, is added).However, LLR combiners 2540 and LLR combiners 2640 For the LLR value for specific bit to be updated to more accurate value.However, can also be in no LLR combiners 2540 and LLR groups In the case of clutch 2640, the LLR value for specific bit is decoded from the LLR value received, therefore, in some cases, LLR combiners 2540 and LLR combiners 2640 can be omitted.

In detail, LLR combiners 2540 be with 216 corresponding component of the duplicator of transmitter 100, and it is executable with Operated corresponding to the operation of duplicator 216.Selectively, LLR combiners 2640 are and the duplicator of transmitter 100 317 and attached Component corresponding to add parity verification generator 319, and it is executable with duplicator 317 and additional parity generator 319 Operated corresponding to operation.

First, LLR combiners 2540 and LLR combiners 2640 can will LLR value corresponding with repetition bits and other LLR values Combination.Here, other LLR values can be the basic bit that repetition bits are produced as transmitter 100, i.e. be selected as repeating The LLR value of the LDPC Parity Check Bits of object.

That is, as described above, transmitter 100 selects bit from LDPC Parity Check Bits and in LDPC information Bit and by LDPC encode caused by the bit of selection is repeated between LDPC Parity Check Bits, and repetition bits are sent To receiver 200.

As a result, can be by the LDPC Parity Check Bits for repeating for the LLR value of LDPC Parity Check Bits LLR value and for non-repetitive LDPC Parity Check Bits (that is, by LDPC encode caused by LDPC Parity Check Bits) LLR value is formed.Therefore, LLR combiners 2540 and LLR combiners 2640 can be by for the LLR of identical LDPC Parity Check Bits Value combination.

For such purpose, receiver 200, which can prestore to be performed according to corresponding pattern with transmitter 100, repeats institute The information of the relating to parameters used.As a result, LLR combiners 2540 and LLR combiners 2640 can determine that the LDPC of repetition is strange The length of even parity check bit, the position of the basic bit of repetition is determined as, and by for the LDPC even-odd checks of repetition The LLR value of bit with for as repeat basic and by LDPC encode caused by LDPC Parity Check Bits LLR value group Close.

For example, as shown in figures 26 and 27, LLR combiners 2540 and LLR combiners 2640 can be by for repetitions The LLR value of LDPC Parity Check Bits with for as repeat basic and by LDPC encode caused by LDPC even-odd checks ratio Special LLR value combination.

When LDPC Parity Check Bits are repeated n times, LLR combiners 2540 and LLR combiners 2640 can will be directed to place Combined n times in the LLR value of the bit of same position or less secondary.

For example, Figure 26 shows some LDPC odd evens schools in the LDPC Parity Check Bits in addition to the bit being truncated Test the situation that bit is repeated once.In this case, LLR combiners 2540 and LLR combiners 2640, which will can be directed to, repeats The LLR values of LDPC Parity Check Bits combined with for the LLR value of LDPC Parity Check Bits caused by being encoded by LDPC, Then the LLR value of combination is exported, or output is directed to the LLR value of the LDPC Parity Check Bits of the repetition received or for connecing Receive by LDPC encode caused by LDPC Parity Check Bits LLR value, without they are combined.

As another example, Figure 27 shows situations below：One in the LDPC Parity Check Bits not being truncated sent A little LDPC Parity Check Bits are repeated twice, and remainder is repeated once, and the LDPC Parity Check Bits being truncated It is repeated once.

In this case, LLR combiners 2540 and LLR combiners 2640 can by with scheme identical described above Scheme is handled the remainder being repeated once and the LDPC Parity Check Bits being truncated.However, LLR is combined Device 2540 and LLR combiners 2640 can following article the part being repeated twice is handled like that.In this case, in order to retouch The convenience stated, by the way that some LDPC Parity Check Bits in LDPC Parity Check Bits are repeated twice and caused two portions / mono- is referred to as Part I, and another part in described two parts is referred to as Part II.

In detail, LLR combiners 2540 and LLR combiners 2640 can be by for every in Part I and Part II The LLR value of individual part combines with the LLR value for LDPC Parity Check Bits.Alternatively, LLR combiners 2540 and LLR combinations Device 2640 will can combine for the LLR value of Part I with the LLR value for LDPC Parity Check Bits, will be directed to Part II LLR value combine with for the LLR values of LDPC Parity Check Bits, or by for the LLR value of Part I with being directed to second Partial LLR value combination.Selectively, LLR combiners 2540 and the exportable LLR for Part I of LLR combiners 2640 Value, for the LLR value of Part II, for remainder and the LLR value for the bit being truncated, without individually combination.

In addition, LLR combiners 2640 will can combine with LLR value corresponding to additional parity-check bits with other LLR values.This In, other LLR values can be as the basic LDPC odd evens school that additional parity-check bits are produced by transmitter 100 Test bit, i.e. for the LLR value of the LDPC Parity Check Bits for producing additional parity-check bits and selecting.

That is, as described above, transmitter 100 can be by for the additional strange of the L1- details signalings that are sent in present frame Even parity check bit map is sent to receiver 200 to previous frame and by the bit after mapping.

In this case, the LDPC that additional parity-check bits may include to be truncated and not sent in the current frame is strange Even parity check bit, and in some cases, may also include the LDPC Parity Check Bits sent in the current frame.

As a result, LLR combiners 2640 can be by for the LLR of the additional parity-check bits received by present frame The LLR for being worth and being inserted into the position of the LDPC Parity Check Bits being truncated in the LDPC code word received by next frame The LLR value of value and the LDPC Parity Check Bits for being received by the next frame combines.

For such purpose, receiver 200 can be prestored to be produced according to corresponding pattern with transmitter 100 and added very Parameter used in even parity check bit and/or the relevant information of pattern.Added very as a result, LLR combiners 2640 can determine that The length of even parity check bit, the position for the basic LDPC Parity Check Bits for producing additional parity-check bits is determined as, And will be strange as the basic LDPC for producing additional parity-check bits with being directed to for the LLR value of additional parity-check bits The LLR value combination of even parity check bit.

Even-odd check solution displacer 2550 and even-odd check solution displacer 2650 can be respectively to from the Hes of LLR combiners 2540 The LLR value that LLR combiners 2640 export carries out solution displacement.

In detail, even-odd check solution displacer 2550 and even-odd check solution displacer 2650 are strange with transmitter 100 Component corresponding to even parity check displacer 215 and even-odd check displacer 316, and can perform respectively and even-odd check displacer 215 and even-odd check displacer 316 operation corresponding to operate.

For such purpose, receiver 200 can prestore performs by a group friendship with transmitter 100 according to corresponding pattern Knit parameter used in interweaving with even-odd check and/or the relevant information of pattern.Therefore, even-odd check solution displacer 2550 and strange Even parity check solution displacer 2650 can a pair LLR value corresponding with LDPC code word bit inversely perform even-odd check displacer 215 and Interweaving by group for even-odd check displacer 316 (that is, is performed and handed over by group deinterleaving and even-odd check solution with the operation of even-odd check intertexture Knit operation), the displacement of even-odd check solution is performed with a pair LLR value corresponding with LDPC code word bit respectively.

LDPC decoder 2560 and LDPC decoder 2660 can be based respectively on from even-odd check solution displacer 2550 and odd even The LLR value that verification solution displacer 2650 exports performs LDPC decodings.

In detail, LDPC decoder 2560 and LDPC decoder 2660 be with the LDPC encoder of transmitter 100 214 and Component corresponding to LDPC encoder 315, and the operation pair with LDPC encoder 214 and LDPC encoder 315 can be performed respectively The operation answered.

For such purpose, receiver 200 can prestore performs LDPC volumes with transmitter 100 according to corresponding pattern The information of relating to parameters used in code.Therefore, LDPC decoder 2560 can be based on from even-odd check solution according to corresponding pattern The LLR value that displacer 2550 and even-odd check solution displacer 2650 export decodes to perform LDPC.

It is based on for example, LDPC decoder 2560 and LDPC decoder 2660 can be based on sum-product algorithm by iterative decoding from strange Even parity check solution displacer 2550 and even-odd check solution displacer 2650 export LLR value to perform LDPC decodings, and according to LDPC Decode to export the bit after error correction.

Zero remover 2570 and zero remover 2670 can be respectively from outputs from LDPC decoder 2560 and LDPC decoder 2660 bit removes zero bit.

In detail, zero remover 2570 and zero remover 2670 are the zero padding device 213 and zero padding with transmitter 100 Component corresponding to device 314, and operation corresponding with the operation of zero padding device 213 and zero padding device 314 can be performed respectively.

For such purpose, receiver 200 can be prestored with transmitter 100 according to the corresponding bit of Pattern Fill zero The relevant information of used parameter and/or pattern.As a result, zero remover 2570 and zero remover 2670 can be respectively from defeated The bit for coming from LDPC decoder 2560 and LDPC decoder 2660 removes what is filled by zero padding device 213 and zero padding device 314 Zero bit.

BCH decoders 2580 and BCH decoders 2680 can be respectively to exporting from zero remover 2570 and zero remover 2670 Bit perform BCH decoding.

In detail, BCH decoders 2580 and BCH decoders 2680 are the Bose-Chaudhuri-Hocquenghem Code device 212 and BCH with transmitter 100 Component corresponding to encoder 313, and behaviour corresponding with the operation of Bose-Chaudhuri-Hocquenghem Code device 212 and Bose-Chaudhuri-Hocquenghem Code device 313 can be performed respectively Make.

For such purpose, receiver 200 can prestore performs parameter used in Bose-Chaudhuri-Hocquenghem Code with transmitter 100 Relevant information.As a result, BCH decoders 2580 and BCH decoders 2680 can be by going from zero remover 2570 and zero Carry out error correction except the bit that device 2670 exports performs BCH decodings, and export the bit after error correction.

Descrambler 2590 and descrambler 2690 can be respectively to the ratios from BCH decoders 2580 and the output of BCH decoders 2680 Spy is descrambled.

In detail, descrambler 2590 and descrambler 2690 are right with the scrambler of transmitter 100 211 and scrambler 312 The component answered, and executable operation corresponding with the operation of scrambler 211 and scrambler 312.

For such purpose, receiver 200 can prestore performs relating to parameters used in scrambling with transmitter 100 Information.As a result, descrambler 2590 and descrambler 2690 can be respectively to from BCH decoders 2580 and BCH decoders 2680 The bit of output is descrambled and it is exported.

As a result, the basic signalings of L1- sent from transmitter 100 can be resumed.In addition, when transmitter 100 is not to L1- When details signaling performs segmentation, the L1- details signaling sent from transmitter 100 can be also resumed.

However, when transmitter 100 is performed to L1- details signaling and split, solution dispenser 2695 can be to from descrambler 2690 The bit of output performs solution segmentation.

In detail, solution dispenser 2695 be with 311 corresponding component of the dispenser of transmitter 100, and it is executable with Operated corresponding to the operation of dispenser 311.

For such purpose, receiver 200 can prestore performs relating to parameters used in segmentation with transmitter 100 Information.As a result, solution dispenser 2695 can be by the bit exported from descrambler 2690 (that is, the fragment of L1- details signaling) Combine to recover the L1- details signalings before segmentation.

The information relevant with the length of L1 signalings is provided as shown in Figure 28.Therefore, it is thin can to calculate L1- for receiver 200 Save the length of signaling and the length of additional parity-check bits.

Reference picture 28, because the basic signalings of L1- provide the information relevant with the total cell of L1- details, therefore receiver 200 needs Calculate the length of L1- details signalings and the length of additional parity-check bits.

In detail, when the L1B_L1_Detail_additional_parity_mode of the basic signalings of L1- is not 0, Due to the information relevant with given L1B_L1_Detail_total_cells represent total cell length (= N_{L1_detail_total_cells}), therefore receiver 200 can calculate the length of L1- details signalings based on following equation 47 to equation 50 Spend N_{L1_detail_cells}With the length N of additional parity-check bits_{AP_total_cells}。

N_{L1_FEC_cells}=(N_outer+N_repeat+N_{ldpc_parity}-N_punc)/η_MoD=N_FEC/η_MOD...(47)

N_{L1_detail_cells}=N_{L1D_FECFRAME}×N_{L1_FEC_cells}...(48)

N_{AP_total_cells}=N_{L1_detail_total_cells}-N_{L1_detail_cells}...(49)

In this case, based on equation 47 above to equation 49, N_{AP_total_cells}Value can be based on can be from basic with L1- The N of the information acquisition relevant L1B_L1_Detail_total_cells of signaling_{L1_detail_total_cells}、N_FEC、N_{L1D_FECFRAME}、 And order of modulation η_MODTo obtain.As an example, N_{AP_total_cells}It can be calculated based on following equation 50.

N_{AP_total_cells}=N_{L1_detail_total_cells}-N_{L1D_FECFRAME}×N_FEC/η_MOD...(50)

Meanwhile for example following table 13 of grammer and field semantics of the basic signaling fields of L1-.

[table 13]

As a result, receiver 200 can be based on the N being sent among the L1 details cells of reception_{AP_total_cells}Individual cell Additional parity-check bits perform operation of the receiver for the additional parity-check bits in next frame.

Figure 29 is the flow chart for describing the dividing method of the transmitter according to exemplary embodiment.

First, information bit is divided into multiple pieces (S2710) based on one of multiple preset reference values.

Next, the first Parity Check Bits (S2720) are produced by being encoded to the multiple piece, and by right The multiple piece and the first Parity Check Bits are encoded to produce the code word (S2730) including the second Parity Check Bits.

In S2710 is operated, based on code check and whether can perform in repetition at least a portion code word in code word At least one of determine one of multiple preset reference values.

For example, preset reference value may include 2352,3072 and 6312.

In S2710 is operated, when code check be 3/15 and second Parity Check Bits by repeat when, can be based on 2352 pairs letter Breath bit is split.

In S2710 is operated, when code check be 3/15 and second Parity Check Bits by repeat when, can be based on 3072 pairs Information bit is split.

In S2710 is operated, when code check be 6/15 and second Parity Check Bits by repeat when, can be based on 6312 pairs Information bit is split.

The method detailed for producing additional parity-check bits is the foregoing described, therefore, repeated description is omitted.

According to exemplary embodiment, it is possible to provide a kind of non-transitory computer-readable medium, wherein, perform described above The program of various methods is stored in the non-transitory computer-readable medium.The non-transitory computer-readable medium It is not the medium (such as, register, cache, internal memory etc.) of temporary transient data storage wherein, and refers at least semipermanent Ground wherein data storage and can by device (such as, microprocessor) read medium.In detail, kind described above Using or program can be in non-transitory computer-readable medium (such as, compact disk (CD), digital universal disc (DVD), hard disk, indigo plant CD, USB (USB), storage card, read-only storage (ROM) etc.) in stored and provided.

According to exemplary embodiment, the component represented by square frame, element, module as shown in Fig. 1,8,9,24 and 25 or At least one in unit is implemented as performing the hardware of the various quantity of each function described above, software and/or solid Part structure.For example, in these components, element, module or unit it is at least some can be used can pass through one or more micro- places Reason device or other control devices control come perform the direct circuit structure of each function (such as, memory, processor, Logic circuit, look-up table etc.).In addition, at least one in these components, element, module or unit can be by comprising for performing The module of one or more executable instructions of specific logical function, a part for journey logic bomb are next specially to be realized, and It can be performed by one or more microprocessors or other control devices.In addition, in these components, element, module or unit It is at least one may also include the processor (such as, central processing unit (CPU)) for performing each function, microprocessor etc., or Realized by processor, microprocessor etc..Two or more in these components, element, module or unit can be combined into Perform two or more components, element, module or all operations of unit or single component, element, the mould of function of combination Block or unit.In addition, at least a portion function of at least one function in these components, element, module or unit can be by Another in these components, element, module or unit performs.In addition, though bus has been not shown in block diagram more than, But the communication between component, element, module or unit can be performed by bus.In terms of the function of exemplary embodiment above It can be realized according to the algorithm performed on one or more processors.In addition, the component represented by frame or processing step, member Part, module or unit can be used for any amount of existing of electrical arrangement, signal transacting and/or control, data processing etc. Technology.

Although hereinbefore having been shown and describing the exemplary embodiment of inventive concept, inventive concept is not limited to Above-mentioned example embodiment, but can be in the case of the scope and spirit for not departing from the present inventive concept disclosed in claim Changed in a variety of ways by present inventive concept those skilled in the art.For example, exemplary embodiment, which is described, is related to BCH volumes Code and decoding and LDPC coding and decodings.Conciliate however, present inventive concept is not limited only to specific coding by these embodiments Code, on the contrary, can be used necessary modification that present inventive concept is applied into different types of coding and decoding.These modifications also should It is understood to fall within the scope of present inventive concept.

Industrial usability

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Sequence list text none

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Claims

1. a kind of transmitter, including：

Dispenser, it is configured as being divided into information bit based on a preset reference value in multiple preset reference values multiple Block；

External encoder, it is configured as encoding each block in the multiple piece with generation and the multiple piece Corresponding first Parity Check Bits of each block；And

Low-density checksum (LDPC) encoder, is configured as to each block in the multiple piece and the first even-odd check Bit is encoded to produce the second Parity Check Bits,

Wherein, the multiple preset reference value is used with to each block in the multiple piece and according to by LDPC encoder Whether at least a portion in code check and the second Parity Check Bits that one Parity Check Bits are encoded is repeated and is had There is different values.

2. transmitter as claimed in claim 1, wherein, each preset reference value in the multiple preset reference value is to make The bit that can have according at least one in the code check and the repetition for each root tuber in the multiple piece The threshold value of maximum quantity.

3. transmitter as claimed in claim 2, wherein, information bit is divided into the multiple piece so that described more by dispenser Each block in individual block is formed by the bit of identical quantity, wherein, the bit of the identical quantity is entered by LDPC encoder Row is encoded to produce the unit of LDPC code word.

4. transmitter as claimed in claim 3, wherein, the identical quantity of bit is expressed by the following equation：

K_sig=K_L1D/N_{L1D_FECFRAME},

Wherein, K_sigIt is the identical quantity of bit, K_L1DIt is to include filling bit to cause K_sigIt is the number of the information bit of integer Amount, N_{L1D_FECFRAME}It is the multiple piece of quantity and is integer.

5. transmitter as claimed in claim 4, wherein, each preset reference value in the multiple preset reference value meets Below equation：

Wherein,Represent the smallest positive integral equal to or more than x, K_{L1D_ex_pad}It is the length of the information bit in addition to filling bit Degree.

6. transmitter as claimed in claim 1, wherein, the multiple preset reference value includes 2352,3072 and 6312.

7. transmitter as claimed in claim 2, wherein, when the code check be 3/15 and second Parity Check Bits in LDPC When being repeated in code word, dispenser is split based on 2352 pairs of information bits.

8. transmitter as claimed in claim 2, wherein, when the code check be 3/15 and second Parity Check Bits in LDPC When not repeated in code word, dispenser is split based on 3072 pairs of information bits.

9. transmitter as claimed in claim 2, wherein, when the code check be 6/15 and second Parity Check Bits in LDPC When not repeated in code word, dispenser is split based on 6312 pairs of information bits.

10. transmitter as claimed in claim 1, wherein, information bit is divided into described more by dispenser by following operation Individual block：At least two parts are divided information bits into, are last block bag by each partial segmentation in described two parts The block of the identical quantity of filling bit is included, and adds the block of described two parts respectively,

Wherein, each block in the block of the identical quantity is formed by the bit of identical quantity, wherein, the ratio of the identical quantity Spy is encoded by LDPC encoder to produce the unit of LDPC code word.

11. a kind of dividing method of transmitter, methods described include：

Information bit is divided into multiple pieces based on a preset reference value in multiple preset reference values；

Each block in the multiple piece is encoded to produce and each block corresponding first in the multiple piece Parity Check Bits；And

Each block in the multiple piece and the first Parity Check Bits are encoded to produce the second Parity Check Bits,

Wherein, the multiple preset reference value is according to for each block and the first Parity Check Bits in the multiple piece Whether at least a portion in the code check and the second Parity Check Bits that are encoded is repeated and has different values.

12. method as claimed in claim 11, wherein, each preset reference value in the multiple preset reference value is to make The bit that can have according at least one in the code check and the repetition for each root tuber in the multiple piece The threshold value of maximum quantity.

13. method as claimed in claim 12, wherein, the segmentation step is done so that each in the multiple piece Block is formed by the bit of identical quantity, wherein, the bit of the identical quantity is to carry out the coding to produce the unit of code word.

14. method as claimed in claim 13, wherein, the identical quantity of bit is expressed by the following equation：

K_sig=K_L1D/N_{L1D_FECFRAME},

15. method as claimed in claim 14, wherein, each preset reference value in the multiple preset reference value meets Below equation：