CN107567691B - Transmission device for processing input bit - Google Patents

Abstract

The transmitter includes a divider configured to divide information bits into a plurality of blocks based on one of a plurality of preset reference values, an outer encoder configured to encode each of the plurality of blocks and the first parity bits to generate first parity bits, and a low density parity check (L DPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate a L DPC codeword including second parity bits, wherein the one of the plurality of preset reference values is determined according to at least one of a code rate for encoding each of the plurality of blocks and the first parity bits and whether repetition is performed on at least a portion of the L DPC codeword among L DPC codewords.

Description

Transmission device for processing input bit

Technical Field

Apparatuses and methods consistent with exemplary embodiments relate to a transmitter and a segmentation method thereof, and more particularly, to a transmitter capable of segmenting signaling and a segmentation method thereof.

Background

Broadcast communication services in the information-oriented society of the 21 st century are entering the era of digitization, multi-channelization, bandwidth broadening, and high quality. In particular, due to the wide spread of high definition digital Televisions (TVs) and portable broadcasting devices, the demand for digital broadcasting services for the support of various signal reception schemes is increasing.

According to such a demand, the standard group sets various standards to provide various services that meet the needs of users. Therefore, a method for providing a better service to a user with more excellent performance is required.

Disclosure of Invention

Technical problem

Exemplary embodiments of the inventive concept may overcome the disadvantages of the related art signal transmitter and receiver and the method thereof. However, these embodiments are not required to overcome such disadvantages or may not overcome such disadvantages.

Exemplary embodiments provide a transmitter capable of dividing information bits such that the number of divided information bits is equal to or less than a certain number, and a dividing method thereof.

Technical scheme

According to an aspect of an exemplary embodiment, there is provided a transmitter, which may include a divider configured to divide information bits into a plurality of blocks based on one of a plurality of preset reference values, an outer encoder configured to encode each of the plurality of blocks and first parity bits to generate first parity bits, and a low density parity check (L DPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate a L DPC codeword including second parity bits, wherein the one of the plurality of preset reference values is determined according to at least one of a code rate for encoding each of the plurality of blocks and the first parity bits and whether repetition is performed on at least a portion of the L DPC codeword among the L DPC codewords.

According to an aspect of another exemplary embodiment, there is provided a segmentation method of a transmitter, which may include: dividing the information bits into a plurality of blocks based on one of a plurality of preset reference values; encoding each of the plurality of blocks to generate first parity bits; and encoding each of the plurality of blocks and the first parity bits to generate a codeword including second parity bits, wherein the one of the plurality of preset reference values is determined according to at least one of: a code rate for encoding each of the plurality of blocks and the first parity bits and a repetition of at least a portion of the codewords.

Advantageous effects

As described above, according to various exemplary embodiments, information bits may be divided to be equal to or less than a certain number to satisfy performance required for encoding the information bits.

Drawings

The above and/or other aspects of the inventive concept will be described below with reference to the accompanying drawings, in which:

fig. 1 is a block diagram for describing a configuration of a transmitter according to an exemplary embodiment;

FIG. 2 is a diagram for describing a segmentation method according to an exemplary embodiment;

fig. 3 and 4 are diagrams for describing a parity check matrix according to an exemplary embodiment;

fig. 5 is a diagram for describing a method for setting a preset reference value according to an exemplary embodiment;

FIG. 6 is a diagram for describing a segmentation method according to an exemplary embodiment;

fig. 7 is a diagram for describing a frame structure according to an exemplary embodiment;

fig. 8 and 9 are block diagrams for describing detailed configurations of a transmitter according to an exemplary embodiment;

fig. 10 to 23 are diagrams for describing a method for processing signaling according to an exemplary embodiment;

fig. 24 and 25 are block diagrams for describing a configuration of a receiver according to an exemplary embodiment;

fig. 26 and 27 are diagrams for describing examples of combining log likelihood ratio (LL R) values of a receiver according to an exemplary embodiment;

fig. 28 is a diagram illustrating an example of providing information on the length of L1 signaling according to an exemplary embodiment;

fig. 29 is a flowchart for describing a segmentation method according to an exemplary embodiment.

Best mode for carrying out the invention

Detailed Description

Hereinafter, exemplary embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings.

Fig. 1 is a block diagram for describing a configuration of a transmitter according to an exemplary embodiment.

Referring to fig. 1, a transmitter 100 includes a slicer 110, an outer encoder 120, and a low density parity check (L DPC) encoder 130.

The divider 110 divides information bits input to the transmitter 100 into a plurality of blocks (or bit blocks).

Here, the information bits may be signaling (alternatively referred to as "signaling bits" or "signaling information"). The information bits may include information required for the receiver 200 (as shown in fig. 24 or 25) to receive and process data or service data (e.g., broadcast data) transmitted from the transmitter 100.

Hereinafter, for convenience of explanation, a case where the information bits are signaling will be described.

In detail, the transmitter 100 may perform outer-coding on signaling to generate parity bits (or parity bits), and perform inner-coding on outer-coded bits including the signaling and the parity bits generated by the outer-coding.

Here, outer coding is a coding operation performed before inner coding in a concatenated coding operation, and various coding schemes such as Bose, Chaudhuri, Hocquenghem (BCH) coding, and/or Cyclic Redundancy Check (CRC) coding may be used, in which case, as an inner code for inner coding such as L DPC coding, L DPC code may be used.

For L DPC encoding, a certain number of L DPC information bits depending on the code rate and code length are required, however, when the number of signaling bits changes, the number of bits subjected to outer encoding may be greater than the number of L DPC information bits used for L DPC encoding.

Therefore, when the number of signaling bits is greater than the preset value, the divider 110 may divide the signaling into a plurality of blocks to avoid the number of outer-coded bits from being greater than the required number of L DPC information bits.

Hereinafter, a detailed method for segmenting signaling will be described with reference to fig. 2.

As described above, when the number of signaling bits changes, it is necessary in some cases to divide and the signaling is encoded to be transmitted to the receiver 200, so that at least one Forward Error Correction (FEC) frame is required to transmit all the signaling bits. Here, the FEC frame may mean that the signaling is encoded in a form to which parity bits are added.

However, when the signaling is split into at least two, these split signaling are both outer coded and L DPC coded to produce at least two FEC frames, thus requiring at least two FEC frames for signaling transmission.

Accordingly, the slicer 110 calculates the number N of FEC frames for signaling based on the following equation 1 or 2_{L1D_FECFRAME}。

In the above-described equations 1 and 2,

represents the smallest integer equal to or greater than x. Furthermore, K_{L1D_ex_pad}Indicating the length of the signaling (i.e., the number of signaling bits) except for the padding bits.

K_segRepresents a threshold defined for the segmentation, and the number of bits of the segmented signaling (i.e., the segments of the signaling) does not exceed K_seg。

In this case, K_segMay be set to a plurality of preset reference values.

Here, a plurality of preset values may be determined according to the L DPC code rate and whether bit repetition is performed_segMay be set to 2352, 3072 or 6312 repetition represents that parity bits generated by L DPC encoding (i.e., L DPC parity bits) are repeated in the L DPC codeword when repetition is performed, the L DPC codeword with repetition may be formed from L DPC information bits, parity bits generated by L DPC encoding, and repeated parity bits.

Thus, the segmenter 110 mayOne of a plurality of preset reference values is selected and the signaling is partitioned based on the selected preset reference value. That is, the slicer 110 may calculate the number N of FEC frames for signaling based on the selected preset reference value_{L1D_FECFRAME}。

When the L DPC rate is 3/15 and L DPC parity bits are repeated, the slicer 110 may be based on K_segThe signaling is split 2352.

When the L DPC rate is 3/15 and L DPC parity bits are not repeated, the slicer 110 may be based on K_seg3072 the signaling is split.

When the code rate is 6/15 and L DPC parity bits are not repeated, the slicer 110 may be based on K_segThe signaling is partitioned 6312.

Meanwhile, a mode in which the transmitter 100 processes signaling may be previously set. That is, K for partitioning signaling_segThe value, the code rate of L DPC code, whether repetition is performed, etc. may be set in advance.

In addition, the divider 110 calculates the number of padding bits (or the length of the padding field). In detail, the divider 110 may calculate the number K of padding bits for signaling based on the following equation 3_{L1D_PAD}。

In addition, the segmenter 110 may use K_{L1D_PAD}A number of zero bits (i.e., bits having a value of 0) to fill the pad field. Thus, K_{L1D_PAD}Zero bits may be added to the signaling so that all signaling may be formed of signaling and padding bits as shown in fig. 2.

In this way, the number of pad bits is calculated and as many zero bits as the calculated number are padded to the pad field, and thus signaling (i.e., a plurality of signaling blocks) may be formed of the same number of bits each.

Next, the divider 110 may calculate the total length K of all signaling including the padding bits based on the following equation 4_L1D。

K_L1D＝K_{L1D_ex_pad}+K_{L1D_PAD}…(4)

That is, the divider 110 may sum the number of signaling bits and the number of padding bits to calculate the total length of all signaling including the padding bits.

Further, the segmenter 110 may calculate N based on equation 5 below_{L1D_FECFRAME}Number K of signaling bits in each of the signaling blocks_sig。

K_sig＝K_L1D/N_{L1D_FECFRAME}…(5)

Next, the segmenter 110 may be based on K_sigThe signaling is partitioned. In detail, as shown in fig. 2, the splitter 110 may split the signaling into and K_sigAs many bits as there are to split the signaling into N_{L1D_FECFRAME}And (4) blocks.

In detail, since the zero bit is arranged at the tail of the signaling, the signaling follows K_sigThe number of bits is successively divided to constitute first to (N) th blocks_{L1D_FECFRAME}-1) blocks. Furthermore, in the signaling according to K_sigThe signaling part remaining after the number of bits is consecutively divided forms Nth together with padding bits_{L1D_FECFRAME}And (5) blocking.

In this way, the divider 110 may divide the signaling into a plurality of blocks based on one of a plurality of preset reference values.

That is, the segmenter 110 may be based on K_seg＝2352、K_seg3072 and K_segCalculating N as one of 6132_{L1D_FECFRAME}Based on N_{L1D_FECFRAME}Calculating K_sigAnd dividing the signaling into N_{L1D_FECFRAME}Blocks such that each block consists of K_sigA bit is formed.

The outer encoder 120 encodes the plurality of blocks to generate parity bits (or parity bits). In this case, the outer encoder 120 may encode the plurality of blocks respectively to generate parity bits corresponding to the plurality of blocks respectively.

For example, outer encoder 120 may encode a signal represented by K_sigEach of the blocks formed by the bits performs outer coding to generate M_outerA plurality of parity bits, and adding the parity bits to bits constituting each block to output a parity bit composed of N_outer(＝K_sig+M_outer) The bits form outer coded bits.

However, for convenience of explanation, the outer coding will be described below under the assumption that the outer coding is performed by the BCH code.

That is, the BCH encoder 120 may perform encoding (i.e., BCH encoding) on the plurality of blocks, respectively, to generate parity bits, i.e., BCH parity bits (or BCH parity bits), corresponding to the plurality of blocks, respectively.

For example, the BCH encoder 120 can systematically correct all K_sigEncoding a block of bits to produce M_outerA BCH parity bit, and adding the BCH parity bit to bits constituting each block to output a BCH parity bit consisting of N bits_outer(＝K_sig+M_outer) A number of bits forming BCH coded bits. Here, M_outer＝168。

L the DPC encoder 130 performs encoding (i.e., L DPC encoding) on the plurality of blocks and the parity bits to generate parity bits, i.e., L DPC parity bits, that is, the L DPC encoder 130 may perform L DPC encoding on BCH-encoded bits including the BCH parity bits in each of the plurality of blocks to generate L DPC parity bits corresponding to each of the plurality of blocks.

Thus, when the number of BCH-encoded bits generated by performing BCH encoding on signaling or divided signaling is less than the required number of L DPC information bits, the transmitter 100 may fill an appropriate number of zero bits (i.e., bits having a value of 0) to obtain the required number of L DPC information bits_ldpcIs 3240 or 6480.

For example, the number of bits N when BCH encoded_outer(＝K_sig+M_outer) SmallL DPC information bits K in L DPC code_ldpcThe transmitter 100 may then send K_ldpc-N_outerZero bits are padded into some of the L DPC information bits to produce a binary K_ldpcL DPC information bits formed of one bit therefore K_ldpcThe L DPC information bits can be composed of N_outerA BCH coded bit sum K_ldpc-N_outerThe zero bits are formed.

Here, the number K of L DPC information bits of the L DPC code_ldpcMay be 3240 or 6480.

Since the padded zero bits are the bits required to obtain a certain number of bits for L DPC encoding, the padded zero bits are removed after being L DPC encoded so that the zero bits are not transmitted to the receiver 200.

However, when the number of BCH-encoded bits generated by performing BCH encoding on the signaling or the divided signaling is equal to the required number of L DPC information bits, the transmitter 100 may not pad zero bits and L DPC information bits may be formed of only the BCH-encoded bits without zero bits.

Meanwhile, the foregoing examples describe performing BCH encoding on signaling. Here, the BCH code is only an example of the outer code. That is, the transmitter 100 may also encode signaling using various codes, such as a BCH code and/or a CRC code.

That is, the information bits may not be outer-encoded to constitute L DPC information bits together with padded zero bits or only the information bits may constitute L DPC information bits without being padded.

That is, since the zero bits are bits having a value preset by the transmitter 100 and the receiver 200 and are padded only for forming L DPC information bits together with information bits including information to be subsequently transmitted to the receiver 200, bits having another value (e.g., 1) preset by the transmitter 100 and the receiver 200 instead of the zero bits may be padded for reduction.

The L DPC encoder 130 may systematically encode the L DPC information bits to generate L0 DPC parity bits, and output L DPC codewords formed of L1 DPC information bits and L2 DPC parity bits (or bits subjected to L DPC encoding) — that is, the L DPC code is a systematic code, and thus, L DPC codewords may be formed of L DPC information bits before being DPC encoded by L and L DPC parity bits generated by L DPC encoding.

For example, L DPC encoder 130 may be paired with K_ldpcL DPC information bits

Performing L DPC encoding to produce N_{ldpc_parity}L DPC parity bits (p)₀,p₁,...,

) And output from N_inner(＝K_ldpc+N_{ldpc_parity}) L DPC code words formed by bits

In this case, the L DPC encoder 130 may perform L DPC encoding on the input bits (i.e., L DPC information bits) at various code rates to generate L DPC codewords having a predetermined length.

For example, the L DPC encoder 130 may perform L DPC encoding on 3240 DPC information bits L at a code rate of 3/15 to generate L DPC codewords formed of 16200 bits as another example, the L DPC encoder 130 may perform L DPC encoding on 6480L DPC information bits at a code rate of 6/15 to generate L DPC codewords formed of 16200 bits.

Meanwhile, the process of performing L DPC encoding is to generate L DPC codesWord to satisfy H.C^TProcessing of 0, therefore, the L DPC encoder 130 may perform L DPC encoding using a parity check matrix where H denotes the parity check matrix and C denotes the L DPC codeword.

Hereinafter, a structure of a parity check matrix according to various exemplary embodiments will be described with reference to the accompanying drawings. In the parity check matrix, elements of the portion other than 1 are 0.

As one example, the parity check matrix according to an exemplary embodiment may have a structure as shown in fig. 3.

Referring to fig. 3, the parity check matrix 20 may be composed of five sub-matrices A, B, C, Z and D. Hereinafter, in order to describe the structure of the parity check matrix 20, each matrix structure will be described.

The sub-matrix A is formed by K columns and g rows, and the sub-matrix C is formed by K + g columns and N-K-g rows. Here, K (or K)_ldpc) Indicating the length, N (or N), of L DPC information bits_inner) Indicating the length of L DPC codeword.

In addition, in the submatrices a and C, when the length of the L DPC codeword is 16200 and the code rate is 3/15, the index of a row in which 1 is located in the 0 th column in the ith column group may be defined based on table 1.

[ Table 1]

Hereinafter, the positions of rows (alternatively, referred to as "indexes" or "index values") in which 1 is located in the submatrices a and C will be described in detail with reference to, for example, table 1.

When the length of the L DPC codeword is 16200 and the code rate is 3/15, the coding parameter M based on the parity check matrix 200₁Encoding parameter M₂Encoding parameter Q₁And a coding parameter Q ₂1080, 11880, 3, and 33, respectively.

Here, Q₁Denotes the size of cyclically shifted columns belonging to the same column group in the submatrix A, Q₂In the expression submatrix CColumns belonging to the same column group are cyclically shifted by the size.

In addition, Q₁＝M₁/L，Q₂＝M₂/L，M₁＝g，M₂N-K-g, L denotes an interval at which the pattern of columns is repeated in each of the submatrices a and C, that is, the number of columns belonging to the same column group (e.g., 360).

The indices of the rows in which 1 is located in submatrix A and submatrix C, respectively, may be based on M₁A value is determined.

For example, in Table 1 above, since M₁Thus, the position of the row in which 1 is located in the 0 th column of the ith column group in the submatrix a may be determined based on a value less than 1080 among the above index values of table 1, and the position of the row in which 1 is located in the 0 th column of the ith column group in the submatrix C may be determined.

Specifically, the sequence corresponding to the 0 th column group in table 1 above is "837284145225253743085429822105501189611988". Thus, in the 0 th column of the 0 th column group in the submatrix a, 1 may be located in the 8 th, 372 nd, and 841 th rows, respectively, and in the 0 th column of the 0 th column group of the submatrix C, 1 may be located in the 4522 th, 5253 th, 7430 th, 8542 th, 9822 th, 10550 th, 11896 th, and 11988 th rows, respectively.

In the submatrix a, when the position of 1 is defined in the 0 th column of each column group, the position of 1 may be cyclically shifted by Q₁To define the position of the row in which 1 is located in the other columns of each column group, and in the submatrix C, when the position of 1 is defined in the 0 th column of each column group, the position of 1 may be cyclically shifted by Q₂To define the position of the row in which 1 is located in the other columns of each column group.

In the foregoing example, in the 0 th column of the 0 th column group in the submatrix a, 1 is located at the 8 th row, the 372 th row, and the 841 th row. In this case, Q is due to₁Thus, the index of the row in which 1 is located in column 1 of column group 0 may be 11(═ 8+3), 375(═ 372+3), and 844(═ 841+3), and the index of the row in column 2 of column group 0 in which 1 is located may be 14(═ 11+3), 378(═ 375+3)And 847(═ 844+ 3).

In column 0 of the column 0 group of the submatrix C, 1 is located at row 4522, row 5253, row 7430, row 8542, row 9822, row 10550, row 11896, and row 11988. In this case, Q is due to₂Thus, the index of the row in column 1 of column group 0 in which 1 is located may be 4555 (4522 +33), 5286 (5253 +33), 7463 (7430 +33), 8575 (8542 +33), 9855 (9822 +33), 10583 (10550 +33), 11929 (11896 +33), and 12021 (11988 +33), and the index of the row in column 2 of column group 0 in which 1 is located may be 4588 (4555 +33), 5319 (5286 +33), 7496 (7463 +33), 8608 (8575 +33), 9888 (9855 +33), 10616 (10583 +33), 11962 (11929 +33), and 12054 (12021 + 33).

According to this scheme, the position of the row in which 1 is located in all column groups in the submatrices a and C may be defined.

The submatrix B is a dual diagonal matrix, the submatrix D is an identity matrix, and the submatrix Z is a zero matrix.

As a result, the structure of the parity check matrix 20 as shown in fig. 2 may be defined by the sub-matrix a, the sub-matrix B, the sub-matrix C, the sub-matrix D, and the sub-matrix Z having the above structure.

Hereinafter, a method of performing L DPC encoding by the L DPC encoder 130 based on the parity check matrix 20 as shown in fig. 3 will be described.

L DPC codes can be used to match information block S ═ (S)₀,s₁,...,s_K-1) And (6) coding is carried out. In this case, to generate a length of N-K + M₁+M₂L DPC codeword Λ ═ (λ)₀,λ₁,...,λ_N-1) Parity check block from information block S

May be systematically encoded.

As a result, the L DPC codeword may be

Here, M₁And M₂Respectively representing the sizes of parity-check sub-matrices corresponding to the dual diagonal sub-matrix B and the unit sub-matrix D, wherein M₁G and M₂＝N-K-g。

The process of calculating the parity bits can be expressed as follows. Hereinafter, for convenience of explanation, a case where the parity check matrix 20 is defined as the above table 1 will be described as one example.

Step 1) initialization is performed such that λ_i＝s_i(i＝0,1,...,K-1)，p_j＝0(j＝0,1,...,M₁+M₂-1)。

Step 2) converting the first information bit lambda₀To the parity bit address defined in row 1 of table 1 above.

Step 3) for the next L-1 information bits λ_m(m ═ 1, 2.., L-1), mixing lambda_mAnd is accumulated into the parity bit address calculated based on equation 6 below.

In expression 6 above, x represents the first information bit λ₀The address of the corresponding parity bit accumulator. In addition, Q₁＝M₁/L and Q₂＝M₂/L。

In this case, since the length of the L DPC codeword is 16200 and the code rate is 3/15, M is₁＝1080，M₂＝11880，Q₁＝3，Q₂＝33，L＝360。

Step 4) the L nd information bit λ is given due to the parity bit address of row 2 of Table 1 as above_LSimilarly to the previous scheme, the calculation for the next L-1 information bits λ is performed by the scheme described in step 3) above_mA parity bit address of (m-L +1, L + 2.., 2L-1), in which case x represents the information bit λ_LThe address of the corresponding parity bit accumulator and may be obtained based on row 2 of table 1 above.

Step 5) the new row of table 1 above is set to the address of the parity bit accumulator for the L new information bits of each group, and the foregoing process is repeated accordingly.

Step 6) in the slave code word bit lambda₀To lambda_K-1After repeating the foregoing process, the value of equation 7 below is sequentially calculated from i ═ 1.

Step 7) calculates parity bits λ corresponding to the dual diagonal submatrix B based on the following equation 8_KTo

λ_K+L×t+s＝p_Q1×s+t(0≤s＜L，0≤t＜Q₁)...(8)

Step 8) L new codeword bits λ are calculated for each group based on the new line of Table 1 above and equation 6 above_KTo

The address of the parity bit accumulator.

Step 9) at codeword bit λ_KTo

After being applied, parity bits corresponding to the submatrix D are calculated based on the following equation 9

To

λ_K+M1+L×t+s＝p_M1+Q2×s+t(0≤S＜L，0≤t＜Q₂)...(9)

As a result, the parity bits may be calculated by the above scheme. However, this is only one example, and thus, a scheme for calculating parity bits based on a parity check matrix as shown in fig. 2 may be defined in various ways.

As such, L DPC encoder 130 may perform L DPC encoding based on table 1 above to generate L DPC codewords.

In detail, the L DPC encoder 130 may perform L DPC encoding on 3240 input bits (i.e., L DPC information bits) at a code rate of 3/15 based on table 1 above to generate 12960L DPC parity bits and output a L DPC codeword formed of L DPC information bits and L DPC parity bits, in which case the L DPC codeword may be formed of 16200 bits.

As another example, the parity check matrix according to an exemplary embodiment may have a structure as shown in fig. 4.

Referring to fig. 4, the parity check matrix 40 is formed of an information sub-matrix 41 and a parity sub-matrix 42, wherein the information sub-matrix 41 is a sub-matrix corresponding to information bits (i.e., L DPC information bits), and the parity sub-matrix 42 is a sub-matrix corresponding to parity bits (i.e., L DPC parity bits).

The information submatrix 41 comprises K_ldpcA column, parity check submatrix 42 comprising N_{ldpc_parity}＝ N_inner-K_ldpcAnd (4) columns. The number of rows of the parity check matrix 40 is equal to the number of columns N of the sub-parity check matrix 42_{ldpc_parity}＝N_inner-K_ldpc。

In addition, in the parity check matrix 40, N_innerDenotes the length, K, of L DPC code words_ldpcIndicating the length of the information bits, N_{ldpc_parity}＝N_inner-K_ldpcIndicating the length of the parity bits.

Hereinafter, the structures of the information submatrix 41 and the parity submatrix 42 will be described.

The information submatrix 41 is a matrix comprising K_ldpcColumns (i.e., 0 th column to (K) th column_ldpc1) columns) and depends on the following rules.

First, K constituting the information submatrix 41_ldpcIn a columnEach M columns belong to the same group and constitute K of the information submatrix 41_ldpcThe columns are divided into a total of K_ldpcand/M column groups. Columns belonging to the same column group have a cyclic shift of Q from each other_ldpcThe relationship (2) of (c). That is, Q_ldpcWhich may be considered as cyclic shift parameter values for columns of column groups in the information submatrix constituting the parity check matrix 40.

Here, M denotes an interval (for example, M is 360) at which the pattern of columns in the information submatrix 41 is repeated, Q_ldpcIs the size of each column in the information submatrix 41 that is cyclically shifted. M is N_innerAnd K_ldpcAnd is determined such that Q is_ldpc＝(N_inner-K_ldpc) the/M is established. Here, M and Q_ldpcIs an integer, K_ldpcand/M is also an integer. M and Q_ldpcMay have various values according to the length and code rate of the L DPC codeword.

For example, when M is 360, the length N of the L DPC codeword_innerIs 16200, code rate is 6/15, Q_ldpcMay be 27.

Second, if the ith (i ═ 0, 1., K_ldpc/M-1) column group of the 0 th column (here, the degree is the number of values 1 located in the column, and the degrees of all columns belonging to the same column group are the same) is set to D_iAnd the position (or index) of each row in which 1 is located in the 0 th column of the ith column group is set to

The index of the row in which the kth 1 is located in the jth column in the ith column group

Determined based on equation 10 below.

In equation 10 above, k is 0,1,2_i-1；i＝0,1,...,K_ldpc/M-1；j＝1,2,..., M-1。

Meanwhile, equation 10 above may be expressed as equation 11 below.

In equation 11 above, k is 0,1,2_i-1；i＝0,1,...,K _ldpc1/M-1; j-1, 2. In equation 11 above, (j mod M) may be considered to be j, since j is 1, 2.

In the context of these equations, the equation,

denotes an index of a row in which the kth 1 is located in the jth column in the ith column group, N_innerDenotes the length, K, of L DPC code words_ldpcIndicating the length of the information bits, D_iDenotes the degree of columns belonging to the ith column group, M denotes the number of columns belonging to one column group, and Q_ldpcIndicating the size of each column that is cyclically shifted.

As a result, refer to the above equation if

The value is known, the index of the row in which the kth 1 is located in the jth column in the ith column group

May be known. Accordingly, when the index value of the row in which the kth 1 is located in the 0 th column of each column group is stored, the positions of the column and row in which the 1 is located in the parity check matrix 40 having the structure of fig. 4 (i.e., the information submatrix 41 of the parity check matrix 40) may be checked.

According to the aforementioned rule, the degree (degree) of all columns belonging to the ith column group is D_iTherefore, the L DPC codeword storing information about the parity check matrix can be briefly expressed as follows according to the aforementioned rule.

For example, when N is_innerIs 30, K_ldpcIs 15, and Q_ldpcIf 3, the position information of the row in which 1 is located in the 0 th column group of the 3 column groupsCan be represented by a sequence (which may be referred to as a "weight-1 position sequence") as in equation 12 below.

In the above equation 12 of the above,

indicates an index of a row in which the kth 1 is located in the jth column of the ith column group.

The weight-1 position sequence of equation 12 as above, which represents the index of the row in which 1 is located in the 0 th column of each column group, can be more briefly represented as table 2 below.

[ Table 2]

Table 2 above shows the positions of elements whose value in the parity check matrix is 1, and the ith weight-1 position sequence is represented by the index of the row in which 1 is located in column 0 belonging to the ith column group.

The information submatrix 41 of the parity check matrix according to the above-described exemplary embodiment may be defined based on the following table 3.

Here, table 3 below shows the index of the row in which 1 is located in the 0 th column of the i-th column group in the information submatrix 41. That is, the information submatrix 41 is formed of a plurality of column groups, wherein each of the plurality of column groups includes M columns, and a position of 1 in the 0 th column of each of the plurality of column groups may be defined by table 3 below.

For example, when L DPC code word length N_innerIs 16200, the code rate is 6/15, and M is 360, the index of the row where 1 is located in the 0 th column of the ith column group in the information submatrix 41 is as in table 3 below.

[ Table 3]

According to another exemplary embodiment, a parity check matrix in which the order of indexes in each sequence corresponding to each column group is changed in table 3 above is regarded as a parity check matrix for L DPC code identical to the parity check matrix described above is another example of the inventive concept.

According to still another exemplary embodiment, the parity check matrix in which the arrangement order of the sequences of the column groups in table 3 above is changed is also regarded as the same parity check matrix as the above-described parity check matrix because they have the same algebraic characteristics, such as the ring characteristics and the degree distribution on the code pattern.

According to yet another exemplary embodiment, Q is_ldpcThe parity check matrix in which the multiples of (a) are added to all indexes of the sequences corresponding to the column groups in table 3 above is also considered to be the same parity check matrix as the above-described parity check matrix because they have the same ring characteristics and degree distribution on the code pattern. Here, it is to be noted that when Q is turned on by turning on Q_ldpcIs added to a given sequence to obtain a value equal to or greater than N_inner-K_ldpcWhen the value needs to be changed to pass through to N_inner-K_ldpcThe value obtained by performing the modulo operation is then applied.

If the position of the row in which 1 is located in the 0 th column of the ith column group in the information submatrix 41 is defined as shown in table 3 above, it may be cyclically shifted by Q_ldpcAnd thus the position of the row in which 1 is located in the other columns of each column group can be defined.

For example, as shown in the above table 3, since the sequence corresponding to the 0 th column of the 0 th column group of the information submatrix 41 is "2743051982818971943251326002640331034154266504451005328548359286204639264166602701974157623811284858724899494459667", in the 0 th column of the 0 th column group in the information submatrix 41, 1 is located at the 27 th row, the 430 th row, the 519 th row, ….

In this case, Q is due to_ldpc＝(N_inner-K_ldpc) Where M is (16200-The index of the row in which 1 in column 1 is located may be 54(═ 27+27), 457(═ 430+27), 546(═ 519+27), …, 81(═ 54+27), 484(═ 457+27), 573(═ 546+27), ….

Through the above scheme, the index of the row in which 1 is located among all the rows of each column group can be defined.

Hereinafter, a method for performing L DPC encoding based on the parity check matrix 40 as shown in fig. 4 will be described.

First, information bits to be encoded are set to i₀，i₁，…，

And the code bit output from L DPC coding is set to c₀，c₁，…，

In addition, since the L DPC code is systematic, it is directed to K (0. ltoreq. K < K)_ldpc-1)，c_kIs set as i_k. At the same time, the remaining code bits are set to

Hereinafter, a method for calculating the parity bit p will be described_kThe method of (1).

Hereinafter, q (i, j,0) denotes the jth entry of the ith row in the index list as in table 3 above, for 0<i<360, Q (i, j, l) is set to Q (i, j, l) ═ Q (i, j,0) + Q_ldpc×l(mod N_inner-K_ldpc) In addition, in Table 3 above, since the length of L DPC codeword is 16200 and the code rate is 6/15, Q is_ldpcIs 27.

Meanwhile, when q (i, j,0) and q (i, j,1) are defined as above, the process of calculating parity bits is as follows.

Step 1) initializes the parity bit to "0". That is, for 0 ≦ k<N_inner-K_ldpc， p_k＝0。

Step 2) aiming at k being more than or equal to 0<K_ldpcAll k values of (a), set i and l to

And l ═ k (mod 360). Here, the

Is the largest integer no greater than x.

Next, for all i, i is defined_kAdd up to p_q(i,j,l)In (1). That is, p is calculated_q(i,0,l)＝ p_q(i,0,l)+i_k，p_q(i,1,l)＝p_q(i,1,l)+i_k，p_q(i,2,l)＝p_q(i,2,l)+i_k，...，p_{q(i,w(i)-1,l)}＝p_{q(i,w(i)-1,l)}+i_k。

Here, w (i) denotes the number of values (elements) of the ith row in the index list of table 3 as above, and denotes the number of parity check matrix and i_kThe number of 1's in the corresponding column. In addition, in table 3 above, q (i, j,0) as the j-th entry of the i-th row is an index of a parity bit and indicates the parity bit in the parity check matrix with i_kThe position of the row in which 1 is located in the corresponding column.

In detail, in table 3 above, q (i, j,0) as the j-th item of the i-th row indicates the position of the row where 1 is located in the first (i.e., 0-th) column of the i-th column group in the parity check matrix of the L DPC code.

q (i, j,0) can also be considered to be a function of allowing real device implementation for all i to use i_kAdd up to p_q(i,j,l)However, this is only one example, and thus, it is apparent that obtaining a result equivalent to L DPC encoding results is possible regardless of what encoding scheme is applied, wherein L DPC encoding results may be obtained from a parity check matrix of L DPC codes, wherein the parity check matrix may be substantially based on the above tableA q (i, j,0) value of 3.

Step 3) by aiming at satisfying 0<k<N_inner-K_ldpcAll k of (2) calculate p_k＝p_k+p_k-1To calculate the parity bit p_k。

Accordingly, all coded bits c are available₀，c₁，…，

As a result, the parity bits may be calculated by the above scheme. However, this is only one example, and thus, a scheme for calculating parity bits based on a parity check matrix as shown in fig. 4 may be defined in various ways.

As such, L DPC encoder 130 may perform L DPC encoding based on table 3 above to generate L DPC codewords.

In detail, the L DPC encoder 130 may perform L DPC encoding on 6480 input bits (i.e., L DPC information bits) at a code rate of 6/15 based on table 3 above to generate 9720L DPC parity bits and output L DPC parity bits and a L DPC codeword formed of L DPC parity bits, in which case the L DPC codeword may be formed of 16200 bits.

As described above, the L DPC encoder 130 may encode L DPC information bits at various code rates to generate L DPC parity bits.

Specifically, when the segmenter 110 is based on K_seg2352 or K_segWhen performing segmentation 3072, the L DPC encoder 130 may perform L DPC encoding on 3240 DPC information bits at a code rate of 3/15 based on table 1 above to generate 12960L DPC parity bits and output a L DPC codeword of 16200 length formed of L DPC information bits and L DPC parity bits.

In addition, when the segmenter 110 is based on K_segWhen the segmentation is performed 6312, the L DPC encoder 130 may perform L DPC encoding on 6480 DPC information bits at a code rate of 6/15 based on table 3 above to generate 9720L DPC parity bits, and output a data stream formed of L DPC information bits and L DPC parity bitsL DPC code words of length 16200.

However, the foregoing examples describe that the parity check matrix is defined based on table 1 and table 3 above, which are merely examples. Thus, the parity check matrix may be defined by various different schemes.

The transmitter 100 may transmit L DPC codewords to the receiver 200.

The transmitter 100 may perform repetition and puncturing on the L DPC codeword and transmit the repeated and punctured L DPC codeword (i.e., L DPC codeword bits including repeated bits except for the punctured bits) to the receiver 200.

That is, the transmitter 100 may repeat at least some bits of the L DPC codeword formed of L DPC information bits and L DPC parity bits at positions immediately adjacent to the L DPC information bits.

Specifically, the transmitter 100 may repeat a certain number of L DPC parity bits after L DPC information bits-that is, the transmitter 100 may redundantly add a certain number of L DPC parity bits after L DPC information bits-thus, the same bits are redundant by repetition and the repeated bits are located between L DPC information bits and L DPC parity bits within the L DPC codeword.

In addition, the bits that are repeated in the L DPC codeword (i.e., the bits that are added after the L DPC information bits according to the repetition) may be referred to as repeated bits (or repeated bits).

Meanwhile, the foregoing repetition may be selectively performed. In detail, when the signaling is based on K_segRepetition may be performed when 2352 is partitioned and the partitioned signaling is L DPC encoded at a code rate of 3/15_seg3072 and K_segWhen 6312 is split and the split signaling is DPC encoded through L at code rate of 3/15 or 6/15, repetition may be omitted.

In addition, the transmitter 100 may perform puncturing-that is, the transmitter 100 may puncture L some of the DPC parity bits.

Here, some of the punctured representation L DPC parity bits are not transmitted to the receiver 200 in this case, the transmitter 100 may transmit the remaining L DPC codeword bits left after the punctured L DPC parity bits are removed to the receiver 200, or transmit only the remaining bits of the L DPC codeword, excluding the punctured L DPC parity bits, to the receiver 200.

Specifically, the transmitter 100 may puncture as many bits as a certain number of bits behind the L DPC parity bits, that is, the transmitter 100 may puncture the certain number of bits from the last L DPC parity bits.

In this case, since the L DPC codeword having repetition is constructed in the order of L DPC information bits, repeated L DPC parity bits, and L DPC parity bits generated through L DPC encoding, the transmitter 100 may puncture a certain number of bits from the last L DPC parity bits among L DPC parity bits generated through L DPC encoding, and thus, a certain number of bits from the last bits of the L DPC codeword may be punctured.

Next, the transmitter 100 may transmit L DPC codeword bits to the receiver 200, wherein the L DPC codeword bits are repeated, punctured, and reduced L DPC codeword bits except for zero bits added to the repeated and punctured L DPC codeword (i.e., repeated, punctured, and reduced L DPC codeword (i.e., L DPC codeword bits after adding bits according to repetition except for punctured bits and reduced bits)).

In this case, the transmitter 100 may modulate the repeated, punctured and reduced L DPC codeword by QPSK to generate constellation symbols, which are mapped to a frame for transmission to the receiver 200.

In particular, when the signaling is based on K_seg2352 is divided and the divided signaling is L DPC encoded at a code rate of 3/15, the transmitter 100 may modulate the repeated, punctured and reduced L DPC codeword by QPSK.

However, when repetition is omitted, the transmitter 100 may modulate the punctured and reduced L DPC codeword by QPSK, 16-Quadrature Amplitude Modulation (QAM), 64-QAM, or 256-QAM to produce constellation symbols that are mapped to a frame for transmission to the receiver 200.

In detail, when the signaling is based on K_seg3072 and the split signaling is L DPC encoded at a code rate of 3/15, the transmitter 100 may modulate the punctured and reduced L DPC codeword by QPSK.

In addition, when the signaling is based on K_segWhen 6312 is divided and the divided signaling is L DPC encoded at a code rate of 6/15, the transmitter 100 may modulate the punctured and reduced L DPC codeword by 16-QAM, 64-QAM, or 256-QAM.

Also in these cases, modulation order η is when the signaling is modulated by QPSK, 16-QAM, 64-QAM, and 256-QAM, respectively_MODMay be 2, 4, 6 and 8.

Since the signaling includes signaling information for the data, the transmitter 100 may map the data to a frame together with the signaling for processing the data and transmit the mapped data to the receiver 200.

In detail, the transmitter 100 may process data according to a specific scheme to generate constellation symbols and map the generated constellation symbols to data symbols of each frame. In addition, the transmitter 100 may map signaling for data mapped to each data to a preamble of a corresponding frame. For example, the transmitter 100 may map signaling including signaling information for data mapped to the ith frame.

As a result, receiver 200 may use signaling obtained from a frame to receive and process data from the frame.

Meanwhile, according to an exemplary embodiment, the following is provided with respect to K_segThe value is set to 2352, 3072 or 6312.

As described above, the signaling is split and divided by K_sigThe divided signaling formed of the individual bits is BCH coded, as a result of which M_outerSeveral BCH parity bits are generated. In addition, a channel including divided signaling and BCH parity bitsThe over-BCH-encoded bits are input to the L DPC encoder 130-that is, the BCH-encoded bits constitute input bits of the L DPC code (i.e., L DPC information bits).

Here, K_segIs the maximum value of the number of divided signaling bits, thus, K_seg+M_outerThe value becomes the maximum value of the input bits of the L DPC code after division.

When K is_seg+M_outerWhen the value is small, K will be used since more segmentation is performed (i.e. the amount of segmented signalling is large)_segSet to K by length from input bit as L DPC code_ldpcSubtracting the number M of BCH parity bits obtained by BCH coding_outerAnd the obtained value is valid.

Therefore, when K _ldpc3240 and M_outerWhen 168, K_ldpc-M_outer3240-_seg3072 when K_ldpc6480 and M_outerWhen 168, K_ldpc-M_outer6480-_seg＝6312。

However, when repetition is performed, since the length of the input bits of the L DPC code is long, the required performance may not be satisfied_segNeeds to be set to be less than K_ldpc-M_outerThe value of (c).

In detail, when K having the largest value of i among values that can satisfy the required performance_ldpc-M_outerWhen-360 × i is set to the input bit, K_segLess than K_ldpc-M_outerAnd may be set to a value of K_ldpc-M _outer360 × i here, i is an integer.

That is, when repetition is performed, since K is_ldpc3240 and M_outer168, so when (3240-_segLess than 3072 and may be set to a value (3240-168-360 × i) where i is an integer.

In this caseAt the calculation of K_segThe reason why the value 360 is used in (b) is that the columns of the parity check matrix of the L DPC code according to the present exemplary embodiment have a predetermined rule of 360 elements (i.e., column group elements.) therefore, when the number of input bits is defined as a multiple of 360, columns corresponding to the corresponding bits are defined, and encoding and decoding can be more easily implemented.

Meanwhile, FIG. 5 is a block diagram illustrating a length N according to BCH-encoded bits according to an exemplary embodiment_outer＝K_sig+M_outerSatisfy Frame Error Rate (FER) of 10^-4Signal to noise ratio (SNR) diagram.

Here, the horizontal axis indicates the length of BCH-coded bits, and the vertical axis indicates that FER 10 is satisfied^-4SNR of (d).

In addition, the dotted line indicates that FER 10 is satisfied with the most robust data in an Additive White Gaussian Noise (AWGN) channel^-4The SNR of-6.23 dB value compares to an SNR value of-7.73 dB with a 1.5dB gain. In addition, the solid line indicates that FER 10 is satisfied according to the length of BCH-coded bits^-4The SNR value of (d).

In this case, as described above, the signaling needs to guarantee that FER is 10 compared to SNR equal to or less than-7.73 dB^-4Better performance, therefore, the solid line needs to be present in the area below the dashed line.

However, when K_sig+M_outer>2520, K since the dotted line is present in the area above the solid line_seg＝(K_ldpc-M_outer-360 × i ≦ 2520 need to be satisfied and satisfy (K)_ldpc-M_outerThe maximum value of i of-360 × i) ≦ 2520 is 2, so that K_seg＝(3240-168-360×2)＝2352。

Thus, according to an exemplary embodiment, in order to satisfy required performance according to a code rate and whether repetition is performed, K_segAccordingly, segmentation is performed 2352, 3072, or 6312.

Meanwhile, the foregoing example describes that the signaling is not divided into a plurality of parts, which is only one example.

For example, the signaling may also be divided into two parts, signaling 1 and signaling 2.

In this case, the signaling 1 may include information that does not change according to frames (e.g., information that requires demodulation and decoding of data) in at least two consecutive frames, and the signaling 2 may include information that changes according to frames (e.g., information about the location of a unit to which data is mapped in a data symbol).

Hereinafter, when the signaling is divided into two parts, a method for dividing the signaling will be described in detail with reference to fig. 6.

First, the slicer 110 may calculate the number N of FEC frames for signaling based on equation 13 below_{L1D_FECFRAME}。

In equation 13 above, K_{L1D_ex_pad}A sum value representing the number of bits of signaling 1 and the number of bits of signaling 2.

Furthermore, K_segIs a threshold value for segmentation, e.g. K_seg2352, 3072 or 6312.

In addition, the divider 110 may calculate the number of padding bits. In detail, the divider 110 may calculate the number of padding bits K based on the following equation 14_{L1D_PAD}。

K_{L1D_PAD}＝K_{L1_D1_PAD}+K_{L1_D2_PAD}…(14)

In equation 14 above, K_{L1_D1_PAD}Indicates the number of padding bits, K, for Signaling 1_{L1_D2_PAD}Indicating the number of padding bits for signaling 2.

That is, the signaling is divided into signaling 1 and signaling 2, and thus, the divider 110 divides the number K of padding bits for signaling 1_{L1_D1_PAD}And the number of padding bits K for Signaling 2_{L1_D2_PAD}And summing up to calculate the number of all padding bits for the signaling.

In this case, the divider 110 may calculate K based on the following equations 15 and 16_{L1_D1_PAD}And K_{L1_D2_PAD}。

In the above equations 15 and 16, K_{L1_D1}Number of bits, K, representing signalling 1_{L1_D2}Indicating the number of bits of signaling 2.

In addition, the segmenter 110 may pad K in the pad field_{L1D_PAD}And zero bits. Thus, K_{L1D_PAD}Zero bits may be added to the signaling so that all signaling may be formed of signaling 1, signaling 2, and padding bits as shown in fig. 6.

Next, the divider 110 may calculate the total length K of all signaling including zero bits based on the following equation 17_L1D。

K_L1D＝K_{L1D_ex_pad}+K_{L1D_PAD}…(17)

That is, the divider 110 may sum the number of bits of signaling 1, the number of bits of signaling 2, and the number of padding bits to calculate the total length of all signaling including the padding bits.

Further, the slicer 110 may calculate the number K of signaling bits in the FEC frame based on equation 18 below_sig. That is, the slicer 110 may calculate the number K of signaling bits included in the FEC frame based on the following equation 18_sig。

Next, the segmenter 110 may be based on K_sigTo split all signaling. In detail, as shown in fig. 6, the divider 110 may be in accordance with K_sigBits to divide all signaling into N_{L1D_FECFRAME}And (4) blocks.

In this case, the divider 110 may divide the signaling such that signaling 1 and signaling 2 are both included in each of the plurality of blocks.

For example, as shown in FIG. 6, the segmenter 110 is according to

Number of bits sequentially divides signaling 1 to divide signaling 1 into N_{L1D_FECFRAME}And (4) sub-blocks. Thus, the sub-blocks other than the last sub-block may be composed of

One bit is formed and the last sub-block may be formed of

A bit is formed.

Further, the divider 110 is according to

Number of bits sequentially divides signaling 2 to divide signaling 2 into N_{L1D_FECFRAME}And (4) sub-blocks. Thus, the sub-blocks other than the last sub-block may be composed of

One bit is formed and the last sub-block may be formed of

A bit is formed.

Further, the divider 110 may sequentially sum the sub-block divided in signaling 1 and the sub-block divided in signaling 2 to constitute a plurality of blocks, wherein each block is composed of K_sigA bit is formed.

In this case, the divider 110 may divide K for the last sub-block_{L1_D1_PAD}A zero bit is added to the last subblock divided in Signaling 1, K_{L1_D2_PAD}Adding zero bits to the last subblock divided in Signaling 2 and then summing the two subblocks with zero bits added to constitute a subblock with K_sigThe final block of bits.

Through the method, the divider110 may divide signaling including signaling 1 and signaling 2 into a plurality of blocks having a preset size. Here, each block may be represented by K_sigA bit is formed.

Meanwhile, as described above, the signaling is divided into signaling 1 and signaling 2, and overflow occurs when signaling 1 and signaling 2 are divided, respectively.

In detail, when K_{L1D_ex_pad}＝K₁+K₂When, when

A value of greater than K_segOverflow occurs. Here, K₁And K₂Is the length of the divided parts, respectively. That is, since signaling 1 and signaling 2 are separately divided, K₁＝K_{L1_D1}And K₂＝K_{L1_D2}。

Due to K_segIs a threshold value for the number of divided signalling bits and is therefore greater than K_segIs/are as follows

A value of (d) indicates that the number of divided signaling bits is greater than a threshold value, and thus, overflow may be considered to occur.

Therefore, when

In time, overflow can be avoided if satisfied

It can be represented by the following expression 19.

K₁＝N_{L1D_FECFRAME}(K_seg1-1) + i wherein i ═ 1,2_{L1D_FECFRAME}

K₂≤N_{L1D_FECFRAME}(K_seg-K_seg1)...(19)

From the above expression 19, the following expression 20 can be obtained.

K_{L1D_ex_PAD}≤N_{L1D_FECFRAME}(K_seg-1) + i wherein i ═ 1,2, …, N_{L1D_ECFRAME}...(20)

For all i, the necessary condition for satisfying the above expression 20 is

As a result, when

No overflow occurs.

Therefore, when the signaling is divided into two parts, if the division is performed based on equation 13 described above, it is possible to avoid the occurrence of overflow.

When the signaling is divided into two parts, the divider 110 may calculate N based on equation 13 above_{L1D_FECFRAME}This is only one example. Thus, the segmenter 110 may calculate N through various schemes_{L1D_FECFRAME}. The following example is only in calculating N_{L1D_FECFRAME}Has a difference in the method (2) and is based on the calculated N_{L1D_FECFRAME}The method of splitting the signaling is the same, and therefore, only the method for calculating N will be described_{L1D_FECFRAME}In the above-described manner.

For example, the slicer 110 may calculate the number N of FEC frames for signaling based on equation 21 below_{L1D_FECFRAME}。

In equation 21 above, K_segMay be 2352, 3072 or 6312.

As another example, the slicer 110 may calculate the number N of FEC frames for signaling based on equation 22 below_{L1D_FECFRAME}。

In equation 22 above, K_segMay be 2352, 3072 or 6312.

As another example, the slicer 120 may calculate the number N of FEC frames for signaling based on equation 23 below_{L1D_FECFRAME}。

In the above equation 23, K_segMay be 2351, 3071 or 6311.

The above example describes that the signalling is divided into two parts, which is just one example.

The signaling may be divided into m parts. For example, the signaling may also be divided into m parts, i.e., signaling 1, signaling 2, …, signaling m.

In this case, the divider 120 may calculate the number N of FEC frames for signaling based on the following equation 24_{Ll_Dyn_FECFRAME}。

In the above equation 24, K_{L1D_ex_pad}A sum value representing the number of bits of signaling 1, signaling 2, …, and signaling m. In the above equation 24, K_segMay be 2352, 3072 or 6312.

The reason why the division is performed based on the above equation 24 when the signaling is divided into m parts is as follows.

In detail, when K_{L1D_ex_pad}＝K₁+K₂+…+K_mWhen, when

A value of greater than K_segOverflow occurs.

Therefore, when

When it is satisfied

The occurrence of overflow can be avoided, which can be represented by the following equation 25.

K₁＝N_{L1D_FECFRAME}(K_seg1-1)+i₁Wherein i₁＝1，2，...，N_{L1D_FECFRAME}(1)

K₂＝N_{L1D_FECFRAME}(K_seg2-1)+i₂Wherein i₂＝1，2，...，N_{L1D_FECFRAME}(2)

…

K_m-1＝N_{L1D_FECFRAME}(K_seg(m-1)-1)+i_m·1Wherein i_m·1＝1，2，...，N_{L1D_FECFRAME}(m-1) K_m≤N_{L1D_FECFRAME}(K_seg-K_seg1-K_seg2-…-K_seg(m-1)) (m)

…(25)

From the above equation 25, the following expression 26 can be obtained.

Wherein i_j＝1，2，...，K_{L1D_FECFRAME}…(26)

For all i_jThe requirement for satisfying the above expression 26 is

Therefore, if

No overflow occurs when the signaling is divided into m parts.

Therefore, in order to avoid the occurrence of overflow, the divider 120 performs division based on the above equation 24.

Referring to the above equation 24, if m is 1 in the above equation 24, the above equation 24 is the same as the above equation 1, and thus, when signaling is not divided into a plurality of parts, if segmentation is performed based on the above equation 1, overflow does not occur.

Further, referring to the above equation 24, if m is 2 in the above equation 24, the above equation 24 is the same as the above equation 13, and thus, when signaling is divided into two parts, if division is performed based on the above equation 13, overflow does not occur.

As such, the partitioner 110 may partition signaling based on various methods as described above.

Meanwhile, according to an exemplary embodiment, the aforementioned signaling may be implemented by L-detail signaling, and thus, the transmitter 100 may divide L-detail signaling and transmit the divided L1-detail signaling to the receiver 200 by using the aforementioned method.

Here, the L1-detail signaling may be signaling defined in the Advanced Television Systems Committee (ATSC)3.0 standard.

L1-detail signaling may be processed according to seven (7) different modes transmitter 100 according to an example embodiment may combine K according to respective modes_segSet to 2352, 3072 or 6312 to segment L1-detail signaling.

In addition to L1-detail signaling, the ATSC 3.0 standard defines L1-basic signaling the sender 100 can process L1-basic signaling and L1-detail signaling using a particular scheme and send processed L1-basic signaling and L1-detail signaling to the receiver 200. L1-basic signaling can also be processed according to seven (7) different modes.

A method for processing L1-basic signaling and L1-detail signaling will be described below.

The transmitter 100 may map L1-basic signaling and L1-detail signaling to a preamble of a frame and map data to data symbols of the frame to transmit to the receiver 200.

Referring to fig. 7, a frame may be composed of three parts, i.e., a bootstrap (bootstrap) part, a preamble part, and a data part.

The pilot part is used for initial synchronization and provides basic parameters required for the receiver 200 to decode L1 signaling in addition, the pilot part may include information on the mode in which L1-basic signaling is processed at the transmitter 100, i.e., information on the mode used by the transmitter 100 to process L1-basic signaling.

The preamble part includes L1 signaling and may be composed of two parts, i.e., L1-basic signaling and L1-detail signaling.

Here, L1-basic signaling may include information related to L1-detailed signaling, and L1-detailed signaling may include information related to data, here, data is broadcast data for providing a broadcast service and may be transmitted through at least one physical layer channel (P L P).

In Detail, L1-basic signaling includes information required for the receiver 200 to process L1-Detail signaling, which includes, for example, information about a mode in which L1-Detail signaling is processed at the transmitter 100 (i.e., information about a mode used by the transmitter 100 to process L1-Detail signaling), information about a length of L1-Detail signaling, information about an additional parity pattern (i.e., information about a K value used by the transmitter 100 to generate additional parity bits using L1B _ L1 _ Detail _ additional _ parity _ mode) (here, when L1B _ L1 _ Detail _ additional _ parity _ mode is set to '00', K is 0 and additional parity bits are not used), and information about the length of all cells. L1-basic signaling may include basic signaling information about a system including the transmitter 100, such as a Fast Fourier Transform (FFT) size, a guard interval, and a pilot cell pattern.

In addition, the L1-detail signaling includes information required for the receiver 200 to decode the P L P, e.g., a start position of a cell mapped to a data symbol of each P L P, a P L P Identifier (ID), a size of the P L P, a modulation scheme, a code rate, etc.

Accordingly, the receiver 200 may acquire frame synchronization, acquire L1-basic signaling and L1-detail signaling from the preamble, and receive service data required by a user from data symbols using L1-detail signaling.

Methods for processing L1-basic signaling and L1-detail signaling will be described in more detail below with reference to the accompanying drawings.

Fig. 8 and 9 are block diagrams for describing a detailed configuration of the transmitter 100 according to an exemplary embodiment.

In detail, as shown in fig. 8, to process L1-basic signaling, the transmitter 100 may include a scrambler 211, a BCH encoder 212, a zero padding 213, a L DPC encoder 214, a parity permuter 215, a repeater 216, a puncturer 217, a zero remover 219, a bit demultiplexer 219, and a constellation mapper 221.

In addition, as shown in fig. 9, to process L1-detail signaling, the transmitter 100 may include a divider 311, a scrambler 312, a BCH encoder 313, a zero padding 314, a L DPC encoder 315, a parity permuter 316, a repeater 317, a puncturer 318, an additional parity generator 319, a zero remover 321, a bit demultiplexer 322 and a bit demultiplexer 323, and a constellation mapper 324 and a constellation mapper 325.

Here, the components shown in fig. 8 and 9 are components for performing coding and modulation on L1-basic signaling and L1-detail signaling, which are just one example, according to another exemplary embodiment, some of the components shown in fig. 8 and 9 may be omitted or changed, and other components may also be added.

The divider 311, BCH encoders 313 and L DPC encoder 315 shown in fig. 9 may perform the operations performed by the divider 110, outer encoder 120 and L DPC encoder 130 shown in fig. 1.

In the description of fig. 8 and 9, components for performing common functions will be described together for convenience.

L1-basic signaling and L1-detail signaling can be protected by concatenation of BCH outer code and L DPC inner code, however, this is only one example, thus, as outer coding performed before inner coding in concatenated coding, in addition to BCH coding, another coding such as CRC coding can be used, in addition, L1-basic signaling and L1-detail signaling can be protected by L DPC inner code only, without the need for outer code.

First, L1-basic signaling and L1-detail signaling may be scrambled.A L1-basic signaling and a L1-detail signaling are BCH encoded, and thus BCH parity bits of a L1-basic signaling and a L1-detail signaling generated from the BCH encoding may be added to a L1-basic signaling and a L1-detail signaling, respectively.A concatenated signaling and parity bits may be additionally protected by a reduced and punctured 16K L DPC code.

In order to provide various levels of robustness suitable for a wide signal-to-noise ratio (SNR) range, the protection levels of L-basic signaling and L-detail signaling may be divided into seven (7) modes, that is, the protection levels of L-basic signaling and L-detail signaling may be divided into 7 modes based on a L DPC code, a modulation order, a reduction/puncturing parameter (i.e., a ratio of the number of bits to be punctured to the number of bits to be punctured), and the number of bits to be substantially punctured (i.e., the number of bits to be substantially punctured when the number of bits to be punctured is 0).

Accordingly, the transmitter 100 may determine parameters for processing signaling (e.g., modulation and code rate (ModCod) for each mode, parameters for BCH encoding, parameters for zero padding, reduced mode, code rate/code length of L DPC code, interleaving by group mode, parameters for repetition, parameters for puncturing, and modulation scheme, etc.) according to the set mode, and may process signaling based on the determined parameters and transmit the processed signaling to the receiver 200.

Modulation and code rate configurations (ModCod configurations) for 7 modes for processing L1-basic signaling and 7 modes for processing L1-detail signaling are shown in table 4 below the transmitter 100 may encode and modulate signaling based on the ModCod configurations defined in table 4 below according to the corresponding modes, that is, the transmitter 100 may determine a coding and modulation scheme for signaling in each mode based on table 4 below and may encode and modulate signaling according to the determined scheme, in this case, the transmitter 100 may use different constellations even when L1 signaling is modulated by the same modulation scheme.

[ Table 4]

In Table 4 above, K_sigRepresenting the number of information bits of the coded block. That is, since the length is K_sigL1 signaling bits are encoded to generate encoded blocks, so that the length of L1 signaling becomes K in one encoded block_sig. Thus, the size is K_sigThe L1 signaling bits of (a) may be considered to correspond to one L DPC encoded block.

Referring to Table 4 above, K for L1-basic signaling_sigThe value is fixed to 200. however, since the amount of L1-detail signaling bits changes, K for L1-detail signaling_sigThe value changes.

In detail, in the case of L1-detail signaling, the number of L1-detail signaling bits is changed, and thus when the number of L1-detail signaling bits is greater than a preset value, L1-detail signaling may be split to have a length equal to or less than the preset value.

In this case, each size of the divided L1-detail signaling block (that is, L1-detail signaling fragment) may have K defined in table 4 above_sigThe value is obtained. In addition, the size is K_sigMay correspond to one L DPC coding block.

However, when the number of L1-detail signaling bits is equal to or less than a preset value, L1-detail signaling may not be split in this case, the size of L1-detail signaling may have K defined in Table 4 above_sigThe value is obtained. In addition, the size is K_sigL1-detail signaling of (1) may correspond to one L DPC encoded block.

Hereinafter, a method for segmenting the L1-detail signaling will be described in detail.

In detail, since the length of L1-detail signaling is changed, when the length of L1-detail signaling is greater than a preset value, the divider 311 may divide L1-detail signaling into bits having a number equal to or less than the preset value and output each of the divided L-detail signaling to the scrambler 312.

However, when the length of the L1-detail signaling is equal to or less than a preset value, the slicer 311 does not perform a separate slicing operation.

The method of segmenting L1-details by the segmenter 311 is as follows.

L1-the amount of detail signaling bits varies and depends primarily on the number of P L P-thus, to send all bits of L1-detail signaling, at least one Forward Error Correction (FEC) frame is required-here, an FEC frame may represent the form in which L1-detail signaling is encoded, and thus, parity bits according to the encoding are added to L1-detail signaling.

In detail, when L1-detail signaling is not divided, L1-detail signaling is BCH-encoded and L DPC-encoded to generate one FEC frame, and thus, L1-detail signaling transmission requires one FEC frame, on the other hand, when L1-detail signaling is divided into at least two, these divided L1-detail signaling are both BCH-encoded and L DPC-encoded to generate at least two FEC frames, and thus, L1-detail signaling transmission requires at least two FEC frames.

Thus, the slicer 311 may calculate the number N of FEC frames for L1-detail signaling based on equation 27 below_{L1D_FECFRAME}That is, the number of FEC frames N for L1-detail signaling_{L1D_FECFRAME}May be determined based on equation 27 below.

In the above equation 27, in the above equation,

represents the smallest integer equal to or greater than x.

In addition, in equation 27 above, as shown in fig. 10, K_{L1D_ex_pad}Represents the length of L1-Detail signaling except for L1 padding bits, and may be determined by the value of the L1B _ L1 _ Detail _ size _ bits field included in L1-basic signaling.

In addition, K_segRepresents information bits based on the input to L DPC encoder 315 (i.e., L DPC information)Bits) of the number K_ldpcBut a defined threshold number for segmentation. In addition, K_segMay be defined based on a multiple value of 360 and the number of BCH parity bits of the BCH encoding.

K_segIs determined such that after L1-detail signaling is partitioned, the number of information bits K in the encoded block_sigIs set equal to or less than K_ldpc-M_outerIn detail, when L1-detail signaling is based on K_segWhen being divided, since the length of the divided L1-detail signaling does not exceed K_segTherefore, when K_segSet as table 5 below, the length of the split L1-detail signaling is set equal to or less than K_ldpc-M_outer。

Here, M_outerAnd K_ldpcSee tables 6 and 7 below for sufficient robustness, K for L1-detail signaling mode 1_segThe value can be set to K_ldpc-M_outer-720。

K for L1-each mode of detail signaling_segMay be defined as in table 5 below. In this case, the splitter 311 may determine K according to the corresponding mode as shown in table 5 below_seg。

[ Table 5]

As shown in fig. 10, the entire L1-detail signaling may be formed of L1-detail signaling and L1 padding bits.

In this case, the divider 311 may calculate L1 the length of the L1 _ PADDING field (i.e., the number of L1 PADDING bits) of the detail signaling based on equation 28 below_{L1D_PAD})。

However, K is calculated based on the following equation 28_{L1D_PAD}But merely as an example. That is, the segmenter 311 may be based on K_{L1D_ex_pad}Value and N_{L1D_FECFRAME}The value to calculate L1 the length of the L1 _ PADDING field of the detail signaling (i.e., the number of L1 pad bits, K)_{L1D_PAD}). As an example，K_{L1D_PAD}The value may be obtained based on equation 28 below. That is, the following equation 28 is only for obtaining K_{L1D_PAD}An example of a method of value, therefore, based on K_{L1D_ex_pad}Value and N_{L1D_FECFRAME}Another method of values may be applied to obtain equivalent results.

In addition, the segmentor 311 may use K_L1D__PADL1 _ PADDING field is filled with zero bits (i.e., bits having a value of 0.) thus, as shown in FIG. 10, K_L1D__PADA zero bit may be padded into L1 _ PADDING field.

As such, by calculating L1 the length of the 1_ PADDING field and PADDING zero bits of the calculated length into the L1 _ PADDING field, when L1-detail signaling is split, L1-detail signaling can be split into a plurality of blocks formed of the same number of bits.

Next, the splitter 311 may calculate the final length K of the entire L1-detail signaling including zero padding bits based on equation 29 below_L1D。

K_L1D＝K_{L1D_ex_pad}+K_{L1D_PAD}...(29)

In addition, the divider 311 may calculate N based on equation 30 below_{L1D_FECFRAME}Number of information bits in each of the blocks, K_sig。

K_sig＝K_L1D/N_{L1D_FECFRAME}...(30)

Next, the segmenter 311 may follow K_sigThe individual bits divide L1-detail signaling.

In detail, as shown in FIG. 10, when N is_{L1D_FECFRAME}When greater than 1, the divider 311 may be according to K_sigSplitting L1-detail signaling in order to split L1-detail signaling into N_{L1D_FECFRAME}And (4) blocks.

Thus, L1-detail signaling may be split into N_{L1D_FECFRAME}Block, said N_{L1D_FECFRAME}The number of L1-detail signaling bits in each of the blocks may be K_sigAs a result of the encoding, the encoded blocks (i.e., FEC frames) are formed such that N_{L1D_FECFRAME}The number of L1-detail signaling bits in each of the plurality of coding blocks may be K_sig。

However, when L1-detail signaling is not partitioned, K_sig＝K_{L1D_ex_pad}。

The split L1-detail signaling block may be encoded by the following process.

In detail, the size is K_sigL1-detail signaling blocks L1 all bits of each of the detail signaling blocks may be scrambled next, each of the scrambled L1-detail signaling blocks may be encoded by a concatenation of a BCH outer code and a L DPC inner code.

In detail, L1-each of the detail signaling blocks is BCH encoded, so M_outer(168) BCH parity bits may be added to K for each block_sigL-detail signaling bits, then a concatenation of L-detail signaling bits and BCH parity bits for each block may be encoded by a reduced and punctured 16K L DPC code_outer168, but, obviously, M_outerCan be changed to an appropriate value according to the needs of the system.

The scramblers 211 and 312 can scramble L1-basic signaling and L1-detail signaling, respectively in detail, the scramblers 211 and 312 can randomize L1-basic signaling and L1-detail signaling and output the randomized L1-basic signaling and L1-detail signaling to the BCH encoder 212 and 313, respectively.

In this case, the scrambler 211 and 312 may be in K_sigThe information bits are scrambled in units.

That is, since the L1-basic signaling bit number transmitted to the receiver 200 through each frame is 200, the scrambler 211 may be in accordance with K_sig(-200) scrambles L1-basic signaling bits.

Since the number of L1-basic signaling bits sent to receiver 200 over each frame changes, in some cases L1-detail signaling may be split by splitter 311. additionally, splitter 311 may be divided by K_sigThe L1-detail signaling formed by the bits or the divided L1-detail signaling block is output to the scrambler 312. as a result, the scrambler 312 may be configured to perform every K_sigThe L1-detail signaling bits output from the slicer 311 are scrambled.

The BCH encoder 212 and 313 may perform BCH encoding on L l basic signaling and L1-detail signaling to generate BCH parity bits.

In detail, the BCH encoder 212 and 313 may perform BCH encoding on L l basic signaling and L1-detail signaling output from the scrambler 211 and 313, respectively, to generate BCH parity bits, in which the BCH parity bits are added to each of L l basic signaling and L1-detail signaling, and output the BCH-encoded bits to the zero filler 213 and the zero filler 314, respectively.

For example, BCH encoder 212 and BCH encoder 313 can be applied to input K_sigPerforming BCH encoding on the bits to generate M_outer(i.e., K)_sig＝K_payload) BCH parity bits, and will be represented by N_outer(＝K_sig+M_outer) The BCH-coded bits formed of the bits are output to the zero padder 213 and the zero padder 314, respectively.

The parameters for BCH encoding may be defined as in table 6 below.

[ Table 6]

Meanwhile, referring to fig. 8 and 9, it can be understood that L DPC encoders 214 and L DPC encoder 315 may be disposed after the BCH encoder 213 and BCH encoder 213, respectively.

Thus, L1-basic signaling and L1-detail signaling can be protected by concatenation of the BCH outer code and the L DPC inner code.

In detail, L1-basic signaling and L1-detail signaling are BCH-encoded, and thus, BCH parity bits for L1-basic signaling may be added to L1-basic signaling, and BCH parity bits for L1-detail signaling may be added to L1-detail signaling, in addition, concatenated L1-basic signaling and BCH parity bits may be additionally protected by L DPC code, and concatenated L1-detail signaling and BCH parity bits may be additionally protected by L DPC code.

Here, it is assumed that the L DPC code for L DPC encoding is a 16K L DPC code, and therefore, in the BCH encoder 212 and the BCH encoder 213, for N_innerA systematic BCH code of 16200 (i.e., the code length of the 16K L DPC code is 16200, and the L DPC codeword generated by L DPC encoding may be formed of 16200 bits) may be used to perform outer coding of L1-basic signaling and L1-detail signaling.

In detail, for the L DPC code, a predetermined number of L DPC information bits defined according to a code rate and a code length are required, and therefore, when the number of BCH-encoded bits is less than the number of L DPC information bits, the zero padder 213 and the zero padder 314 may pad zero bits for L DPC encoding to generate a predetermined number of L DPC information bits formed of BCH-encoded bits and zero bits and output the generated bits to the L DPC encoder 214 and the L DPC encoder 315, respectively, when the number of BCH-encoded bits is equal to the number of L DPC information bits, the zero bits are not padded.

Here, the zero bits padded by the zero padder 213 and the zero padder 314 are padded for L DPC encoding, and thus, the padded zero bits are not transmitted to the receiver 200 through the reduction operation.

For example, when the number of L DPC information bits of the 16K L DPC code is K_ldpcTo form K_ldpcL DPC information bits, zero bits are padded.

In detail, when the number of BCH-encoded bits is N_outerIn the 16K L DPC code, the number of L DPC information bits is K_ldpcAnd N is_outer<K_ldpcWhile, zero padder 213 and zero padder 314 may pad K_ldpc-N_outerIs zero bit and will be N_outerThe BCH-encoded bits are used as the remainder of L DPC information bits to produce a BCH-encoded BCH signal_ldpcL DPC information bits formed of one bit however, when N_outer＝K_ldpcZero bits are not padded.

For this purpose, the zero padders 213 and 314 may divide the L DPC information bits into a plurality of bit groups.

For example, the zero padders 213 and 314 may apply K based on equation 31 or equation 32 below_ldpcL DPC information bits (i)₀,i₁,...,

) Is divided into N_{info_group}(＝K_ldpcThat is, the zero padder 213 and the zero padder 314 may divide L DPC information bits into a plurality of bit groups such that the number of bits included in each bit group is 360.

Z_j＝{i_kI 360 × j ≦ k < 360 × (j +1) }, wherein j is 0 ≦ N < N_{info_group}…(32)

In equations 31 and 32 above, Z_jRepresenting the jth group of bits.

Parameter N for zero padding for L1-basic signaling and L1-detail signaling_outer、K_ldpcAnd N_{info_group}May be defined as shown in table 7 below. In this case, the zero padders 213 and 314 may determine parameters for zero padding according to the respective modes as shown in table 7 below.

[ Table 7]

In addition, for j < N > 0 ≦ j_{info_group}Each bit group Z as shown in fig. 11_jMay be formed of 360 bits.

In detail, fig. 11 shows a data format after L1-basic signaling and L1-detail signaling are each L DPC encoded, in fig. 11, added to K_ldpcL DPC FEC of L DPC information bits represents L DPC parity bits generated by L DPC encoding.

Referring to FIG. 11, K_ldpcThe L DPC information bits are divided into N_{info_group}And each bit group may be formed of 360 bits.

Number N of BCH encoded bits when L1-basic signaling and L1-detail signaling_outer(＝ K_sig+M_outer) Less than K_ldpc(i.e., N)_outer(＝K_sig+M_outer)＜K_ldpc) For L DPC, K_ldpcThe L DPC information bits can utilize N_outerA BCH coded bit sum K_ldpc-N_outerPadded with zero padded bits. In this case, the padded zero bits are not transmitted to the receiver 200.

Hereinafter, the reduction process performed by the zero padder 213 and the zero padder 314 will be described in more detail.

The zero padders 213 and 314 may calculate the number of padded zero bits, that is, in order to pad the number of bits required for L DPC encoding, the zero padders 213 and 314 may calculate the number of zero bits to be padded.

In detail, the zero padders 213 and 314 may calculate the difference between the number of L DPC information bits and the number of BCH-encoded bits as the number of padded zero bits_outerThe zero padders 213 and 314 may calculate the number of padded zero bits as K_ldpc-N_outer。

In addition, the zero padders 213 and 314 may calculate the number of bit groups in which all bits are padded. That is, the zero padders 213 and 314 may calculate the number of bit groups in which all bits within the bit group are zero-bit-padded.

In detail, the zero padders 213 and 314 may calculate the number N of groups in which all bits are padded based on the following equation 33 or 34_pad。

Next, the zero padders 213 and 314 may determine bit groups in which zero bits are padded among the plurality of bit groups based on the reduction pattern, and may pad the zero bits to all bits within some of the determined bit groups and some bits within the remaining bit groups.

In this case, a reduction pattern of the padded bit group may be defined as shown in table 8 below. In this case, the zero padders 213 and 314 may determine the reduced mode according to the corresponding mode as shown in table 8 below.

[ Table 8]

Here,. pi._s(j) Is the index of the jth group of padding bits. That is to say, pi_s(j) Indicating the reduced mode order of the jth bit group. In addition, N_{info_group}Is the number of groups of bits that constitute L DPC information bits.

In detail, the zero padders 213 and 314 may be based on a reduced mode

Is determined as a bit group in which all bits within the bit group are zero-bit-padded, and zero-paddingThe charger 213 and the zero charger 314 may fill zero bits to all bits of the bit group. That is, the zero padders 213 and 314 may pad the zero bits to the pi-th among the plurality of bit groups based on the reduction pattern_s(0) Bit group, [ pi ], [ phi ]_s(1) Bit group …, pi_s(N_pad-1) all bits in the group of bits.

Thus, when N is_padWhen not 0, zero padders 213 and 314 may determine N based on Table 8 above_padA list of groups of bits (i.e.,

) And padding zero bits to all bits within the determined bit group.

However, when N is_padWhen it is 0, the foregoing process may be omitted.

At the same time, since the number of all padded zero bits is K_ldpc-N_outerAnd is filled to N_padThe number of zero bits of a bit group is 360 × N_padTherefore, the zero padders 213 and 314 may additionally pad the zero bits to K_ldpc-N_outer-360×N_padL DPC information bits.

In this case, the zero padders 213 and 314 may determine a bit group in which zero bits are additionally padded based on the reduced mode, and may additionally pad the zero bits from the head of the determined bit group.

In detail, the zero padders 213 and 314 may be based on a reduced mode

Bit groups determined to be additionally padded with zero bits and zero bits may be additionally padded to be located at positions

K of head_ldpc-N_outer-360×N_padAnd (4) a bit. Thus, K_ldpc-N_outer-360×N_padThe zero bit can be from the pi-th_s(N_pad) The first bit of the group of bits starts to be padded.

As a result, for

The zero bits may be additionally padded to be located at

K of head_ldpc-N_bch-360×N_padAnd (4) a bit.

Also, the foregoing examples describe a slave

Begins to fill K with the first bit of_ldpc-N_outer-360×N_padA zero bit, which is just an example. Therefore, the zero bit is at

The location of the padding may be changed. For example, K_ldpc-N_outer-360×N_padZero bits can be padded to

Or may be filled to

Any position of (a).

Next, the zero padders 213 and 314 may map the BCH-encoded bits to positions where the zero bits are not padded to constitute L DPC information bits.

Thus, N_outerThe BCH coded bits are sequentially mapped to K_ldpcL DPC information bits (i)₀,i₁,...,

) Has no bit position filled with zero bits, and thus, K_ldpcThe L DPC information bits can be composed of N_outerA pass throughBCH coded bits and K_ldpc-N_outerIndividual information bits are formed.

The padded zero bits are not transmitted to the receiver 200. As such, the process of padding zero bits or the process of padding zero bits and then not transmitting the padded zero bits to the receiver 200 may be referred to as puncturing.

L DPC encoder 214 and L DPC encoder 315 perform L DPC encoding on L1-basic signaling and L1-detail signaling, respectively.

In detail, the L DPC encoders 214 and L DPC encoder 315 may perform L DPC encoding on the L DPC information bits output from the zero padder 213 and the zero padder 31 to generate L DPC parity bits, and output L DPC codewords including L DPC information bits and L DPC parity bits to the parity permutator 215 and the parity permutator 316, respectively.

That is, K output from the zero padder 213_ldpcOne bit may include K_sigL1-basic signaling bits, M_outer(＝N_outer-K_sig) A BCH parity bit, and K_ldpc-N_outerA padded zero bit, wherein K_sigL1-basic signaling bits, M_outer(＝N_outer-K_sig) A BCH parity bit, and K_ldpc-N_outerThe padded zero bits may constitute K for the L DPC encoder 214_ldpcL DPC information bits

In addition, K output from the zero filler 314_ldpcOne bit may include K_sigL1-detail signaling bit, M_outer(＝N_outer-K_sig) A BCH parity bit, and (K)_ldpc-N_outer) A padded zero bit, wherein K_sigL1-detail signaling bit, M_outer(＝N_outer-K_sig) A BCH parity bit, and (K)_ldpc-N_outer) The padded zero bits may constitute K for L DPC encoder 315_ldpcL DPC information bits

In this case, L DPC encoders 214 and L DPC encoder 315 may systematically pair K_ldpcThe L DPC information bits are processed to L DPC encoding to generate a code composed of N_innerL DPC code words formed by bits

In L1-basic mode and L1- detail mode 1 and 2, the L DPC encoder 214 and L DPC encoder 315 may encode L1-basic signaling and L1-detail signaling at a code rate of 3/15 to generate 16200 bits of L DPC codewords in this case, the L DPC encoder 214 and L DPC encoder 315 may perform L DPC encoding based on table 1 above.

In addition, under L1- detail modes 3, 4, 5, 6, and 7, L DPC encoder 315 may encode L1-detail signaling at a code rate of 6/15 to generate 16200L DPC codeword bits in which case L DPC encoder 315 may perform L DPC encoding based on Table 3 above.

The code rate and code length for L1-basic signaling and L1-detail signaling are as shown in table 5 above, and the number of L DPC information bits is as shown in table 8 above.

That is, the parity permutator 215 and the parity permutator 316 may perform permutation on only L DPC parity bits among L DPC information bits and L DPC parity bits.

In detail, the parity permutator 215 and the parity permutator 316 may perform permutation on only L DPC parity bits among L DPC codewords output from the L DPC encoders 214 and L DPC encoder 315 and output parity permutated L DPC codewords to the repeater 216 and the repeater 317, respectively, the parity permutator 316 may output parity permutated L DPC codewords to the additional parity generator 319, in this case, the additional parity generator 319 may generate additional parity bits using the parity permutated L DPC codewords output from the parity permutator 316.

For this purpose, the parity permuters 215 and 316 may include a parity interleaver (not shown) and a group-wise interleaver (not shown).

First, the parity interleaver may interleave only L DPC parity bits among L DPC information bits and L DPC parity bits constituting an L DPC codeword, however, the parity interleaver may perform parity interleaving only in the case of L1- detail modes 3, 4, 5, 6 and 7, that is, since L1-basic mode and L1- detail modes 1 and 2 include parity interleaving as part of L DPC encoding processing, the parity interleaver may not perform parity interleaving in the case of L1-basic mode and L1- detail modes 1 and 2.

In a mode of performing parity interleaving, the parity interleaver may interleave L DPC parity bits based on equation 35 below.

u_i＝c_iWherein i is more than or equal to 0 and less than K_ldpc(information bits are not interleaved)

Wherein s is more than or equal to 0 and less than 360, t is more than or equal to 0 and less than 27 … (25)

In detail, L DPC codeword (c) is paired by the parity interleaver based on equation 35 above₀,c₁,...,

) Parity interleaving is performed, and the output of the parity interleaver may be represented by U ═ U (U)₀,u₁,...,

) To indicate.

Meanwhile, since L1-basic mode and L1- detail modes 1 and 2 do not use the parity interleaver, the parity interleaverIs (U) output₀,u₁,...,

) Can be expressed as the following equation 36.

u_i＝c_iWherein, 0 is less than or equal to i<N_inner…(36)

The group-wise interleaver may perform group-wise interleaving on the output of the parity interleaver.

Here, as described above, the output of the parity interleaver may be L DPC codeword parity interleaved by the parity interleaver or may be L DPC codeword parity interleaved by the parity interleaver.

Accordingly, the group-wise interleaver may perform the group-wise interleaving on the L DPC codewords that have undergone parity interleaving when parity interleaving is performed, and may perform the group-wise interleaving on the L DPC codewords that have not undergone parity interleaving when parity interleaving is not performed.

In detail, the group-by-group interleaver may interleave the output of the parity interleaver in units of bit groups.

The L DPC codeword output from the parity interleaver may be divided into a plurality of bit groups by a group-wise interleaver for such a purpose.As a result, L DPC parity bits output from the parity interleaver may be divided into a plurality of bit groups.

In detail, the per-group interleaver may output L DPC-encoded bits (u) output from the parity interleaver based on equation 37 below₀,u₁,...,

) Is divided into N_group(＝N_inner360) bit groups.

X_j＝{u_k|360×j≤k＜360×(j+1)，0≤k＜N_inner) Wherein j is more than or equal to 0 and less than N_group...(37)

In equation 37 above, X_jRepresenting the jth group of bits.

Fig. 12 shows an example of dividing L DPC codewords output from the parity interleaver into a plurality of bit groups.

Referring to FIG. 12, L DPC codewords are divided into N_group(＝N_inner/360) bit groups, each bit group X_jIs formed by 360 bits, wherein j is more than or equal to 0 and less than N_group。

As a result, from K_ldpcL DPC information bits formed by one bit can be divided into K_ldpcA/360 bit group consisting of N_inner-K_ldpcL DPC parity bits formed of a plurality of bits may be divided into N_inner-K_ldpcA/360 bit group.

In addition, the group-by-group interleaver performs group-by-group interleaving on the L DPC codeword output from the parity interleaver.

In this case, the per-group interleaver does not perform interleaving on L DPC information bits, and may perform interleaving on only L DPC parity bits to change the order of a plurality of bit groups constituting L DPC parity bits.

As a result, L DPC information bits among L DPC bits may not be interleaved by the group-wise interleaver, but L DPC parity bits among L DPC bits may be interleaved by the group-wise interleaver, in which case L DPC parity bits may be interleaved in units of groups.

In detail, the group-by-group interleaver may perform group-by-group interleaving on L DPC codewords output from the parity interleaver based on equation 38 below.

Y_j＝X_j，0≤j＜K_ldpc/360

Y_j＝X_πp(j)，K_ldpc/360≤j＜N_group...(38)

Here, X_jRepresents the jth bit group (i.e., jth bit group not interleaved by group), Y, among a plurality of bit groups constituting the L DPC codeword_jIndicating the jth bit group that has undergone interleaving by groups. In addition,. pi._p(j) Indicating the permutation order for interleaving by group.

Here, table 9 shows a group-wise interleaving pattern of the parity part under L1-basic mode and L1- detailed mode 1 and 2, and table 10 shows a group-wise interleaving pattern of the parity part for L1- detailed mode 3, 4, 5, 6 and 7.

In this case, the group-by-group interleaver may determine the group-by-group interleaving mode according to the respective modes shown in the following tables 9 and 10.

[ Table 9]

[ Table 10]

Hereinafter, the operation of the group-wise interleaver will be described with respect to the group-wise interleaving mode at L1-detail mode 2 as an example.

In L1-detail mode 2, the L DPC encoder 315 performs L DPC encoding on 3240L DPC information bits at a code rate of 3/15 to generate 12960L DPC parity bits in this case, the L DPC codeword may be formed of 16200 bits.

Each bit group is formed of 360 bits, and as a result, L DPC codewords formed of 16200 bits are divided into 45 bit groups.

Here, since the number of L DPC information bits is 3240 and the number of L DPC parity bits is 12960, the 0 th to 8 th bit groups correspond to L DPC information bits and the 9 th to 44 th bit groups correspond to L DPC parity bits.

In this case, the group-by-group interleaver does not perform interleaving on the bit groups (i.e., the 0 th bit group to the 8 th bit group) constituting the L DPC information bits based on equation 38 and table 9 above, but may interleave the bit groups (i.e., the 9 th bit group to the 44 th bit group) constituting the L PDC parity bits in a group unit to change the order of the 9 th bit group to the 44 th bit group.

In detail, at L1-detail mode 2 in Table 9 above, equation 28 above may be as Y₀＝X₀,Y₁＝X₁,...,Y₇＝X₇,Y₈＝X₈,Y₉＝X_πp(9)＝X₉,Y₁₀＝X_πp(10)＝X₃₁,Y₁₁＝X_πp(11)＝X₂₃,...,Y₄₂＝X_πp(42)＝X₂₈,Y₄₃＝X_πp(43)＝X₃₉,Y₄₄＝X_πp(44)＝X₄₂That is shown.

Accordingly, the group-by-group interleaver does not change the order of the 0 th bit group to the 8 th bit group including L DPC information bits, but may change the order of the 9 th bit group to the 44 th bit group including L DPC parity bits.

In detail, the group interleaver may change the order of bit groups from the 9 th bit group to the 44 th bit group such that the 9 th bit group is located at the 9 th position, the 31 th bit group is located at the 10 th position, the 23 th bit group is located at the 11 th position, …, the 28 th bit group is located at the 42 th position, the 39 th bit group is located at the 43 th position, and the 42 th bit group is located at the 44 th position.

As described below, since the puncturers 217 and 318 perform puncturing starting from the last parity bit, the parity bit groups may be arranged in the reverse order of the puncturing pattern by parity permutation. That is, the first bit group to be punctured is located at the last bit group.

In this case, the parity permuter 215 and the parity permuter 316 may interleave the L DPC information bits with the identification and output L DPC information bits having the same order as before the interleaving, so that the order of the L DPC information bits is not changed.

The repeater 216 and the repeater 317 may repeat at least some bits at positions following the L DPC information bits in the parity permuted L DPC codeword and output the repeated L DPC codeword (i.e., L DPC codeword bits including the repeated bits) to the puncturer 217 and the puncturer 318 the repeater 317 may also output the repeated L DPC codeword to the additional parity generator 319.

In detail, the repeater 216 and the repeater 317 may repeat a predetermined number of L DPC parity bits after L DPC information bits, that is, the repeater 216 and the repeater 317 may add a predetermined number of repeated L DPC parity bits after L DPC information bits, and thus, within L DPC codewords, the repeated L DPC parity bits are located between L DPC information bits and L DPC parity bits.

Accordingly, the foregoing operation may be referred to as repetition since a predetermined number of bits within the L DPC codeword may be repeated and additionally transmitted to the receiver 200 after the repetition.

The term "adding" means that repetition bits are arranged between L DPC information bits and L DPC parity bits so that the bits are repeated.

The repetition may be performed only on L1-basic mode 1 and L1-detail mode 1, and may not be performed on the other modes in which case the repeater 216 and the repeater 317 perform no repetition and may output the parity permuted L DPC codeword to the puncturer 217 and the puncturer 318.

Hereinafter, a method for performing repetition will be described in more detail.

The repeater 216 and the repeater 317 may calculate the number N of additionally transmitted bits per L DPC codeword based on equation 39 below_repeat。

In equation 39 above, C has a fixed value and D may be an even number. Referring to equation 39 above, it can be appreciated that the number of bits to be repeated can be determined by multiplying C by a given N_outerAnd add D to calculate.

The parameters C and D for the repetitions may be selected based on table 11 below. That is, the repeater 216 and the repeater 317 may determine C and D based on the respective patterns as shown in table 11 below.

[ Table 11]

In addition, the repeaters 216 and 317 may be paired with N_repeatThe L DPC parity bits are repeated.

In detail, when N is_repeat≤N_{ldpc_parity}In time, as shown in fig. 13, the repeaters 216 and 317 may repeat the first N of the parity permuted L DPC parity bits_repeatThat is, the repeater 216 and the repeater 317 may add the first L DPC parity bit among the parity-permuted L DPC parity bits as the Nth DPC parity bit after the L DPC information bit_repeatL DPC parity bits.

When N is present_repeat＞N_{ldpc_parity}In time, as shown in FIG. 14, the repeaters 216 and 317 may permute the parity-permuted N_{ldpc_parity}L DPC parity bits are added to the L DPC information bits, and N may be added_repeat-N_{ldpc_parity}Parity permutated L DPC parity bits are additionally added to the N added first_{ldpc_parity}That is, the repeater 216 and the repeater 317 may add all parity permuted L DPC parity bits after L DPC information bits, and additionally add 1 st L DPC parity bit to Nth L DPC parity bit among parity permuted L DPC parity bits after L DPC parity bits that are added first_repeat-N_{ldpc_parity}L DPC parity bits.

Thus, at L1-basic mode 1 and L1-detail mode 1, additional N_repeatThe individual bits may be selected and transmitted within L DPC codewords.

Puncturers 217 and 318 may puncture some L DPC parity bits among the L DPC parity bits included in the L DPC codeword output from repeaters 216 and 317 and output the punctured L DPC codeword (that is, the remaining L DPC codeword bits except for the punctured bits and also referred to as L DPC codeword after puncturing) to zero remover 218 and zero remover 321. in addition, puncturers 318 may provide information (e.g., the number and positions of punctured bits, etc.) about the punctured L DPC parity bits to additional parity generator 319. in this case, additional parity generator 319 may generate additional parity bits based thereon.

As a result, some L DPC parity bits may be punctured after undergoing parity permutation.

In particular, the punctured L DPC parity bits are not transmitted in the current frame where the L1 signaling bits are transmitted, and in some cases, the punctured L DPC parity bits may be transmitted in a frame before the current frame, which will be described with reference to the additional parity bit generator 319.

For this purpose, the puncturers 217 and 318 may determine the number of L DPC parity bits to be punctured and the size of one coding block per L DPC codeword.

In detail, the puncturers 217 and 318 may calculate the temporary number N of the L DPC parity bits to be punctured based on the following equation 40_{punc_temp}. That is, for a given N_outerThe puncturers 217 and 318 may calculate a temporary number N of L DPC parity bits to be punctured based on equation 40 below_{punc_temp}。

Referring to equation 40 above, the temporary number of bits to be punctured may be reduced in length (i.e., K) by a constant integer B plus_ldpc-N_outer) Is calculated by an integer obtained as a result of multiplying by a preset constant A value. In the present exemplary embodiment, it is apparent that the constant a value is set in a ratio of the number of bits to be punctured to the number of bits to be reduced, and may be set in various ways according to the needs of the system.

In addition, the A value and the B value are used to adjust a code rate of actual transmission, that is, to prepare for a case where the length of information bits (i.e., the length of L1 signaling) is short or a case where the length of L1 signaling is long, the A value and the B value are used to adjust a code rate of actual transmission to be reduced.

K above_ldpcA and B are listed in Table 12 below showing parameters for puncturing. Accordingly, the puncturers 217 and 318 may determine parameters for puncturing according to the respective modes as shown in the following table 12.

[ Table 12]

The puncturers 217 and 318 may calculate a temporary size N of one coding block as shown in the following equation 41_{FEC_temp}Here, the number N of L DPC parity bits according to the corresponding mode_{ldpc_parity}As shown in table 12 above.

N_{FEC_temp}＝N_outer+N_{ldpc_parity}-N_{punc_temp}...(41)

In addition, the puncturers 217 and 318 may calculate the size N of one coding block as shown in the following equation 42_FEC。

In equation 42 above, η_MODIs a modulation order, for example, when L1-basic signaling and L1-detail signaling are modulated by QPSK, 16-QAM, 64-QAM, or 256-QAM according to the corresponding modes, as shown in the above table 12,η_MODmay be 2, 4, 6 and 8. NFEC may be an integer multiple of the modulation order according to equation 42 above.

In addition, the puncturers 217 and 318 may calculate the number N of the L DPC parity bits to be punctured based on the following equation 43_punc。

N_punc＝N_{punc_temp}-(N_FEc-N_{FEC_temp})...(43)

Here, N_puncIs 0 or a positive integer. In addition, N_FECIs obtained by passing through the pair K_sigN obtained by performing BCH coding and L DPC coding on information bits_outer+N_{1dpc_parity}One bit minus N to be punctured_puncThe number of bits of the information block obtained by one bit. That is, N_FECIs the number of bits other than the repetition bits among the bits actually transmitted, and may be referred to as the number of reduced and punctured L DPC codeword bits.

Referring to the foregoing process, the puncturers 217 and 318 may multiply a by the number of padded zero bits (i.e., a reduced length) and add the result to B to calculate a temporary number N of L DPC parity bits to be punctured_{punc_temp}。

In addition, puncturers 217 and 318 are based on N_{punc_temp}To calculate a temporary number N of L DPC codeword bits constituting the L DPC codeword after puncturing and reduction_{FEC_temp}。

In detail, L DPC information bits are DPC-encoded by L and L DPC parity bits generated through L DPC encoding are added to L DPC information bits to construct L DPC code words, here, L DPC information bits include BCH-encoded bits resulting from BCH-encoding of L1-basic signaling and L1-detail signaling, and in some cases, L DPC information bits may further include padded zero bits.

In this case, since the padded zero bits are DPC-encoded by L and then are not transmitted to the receiver 200, a reduced L DPC codeword, i.e., a L DPC codeword (i.e., a reduced L DPC codeword) excluding the padded zero bits, may be formed of BCH-encoded bits and L DPC parity bits.

Accordingly, the puncturers 217 and 318 calculate N by subtracting a temporary number of L DPC parity bits to be punctured from the sum of the number of BCH-encoded bits and the number of L DPC parity bits_{FEC_temp}。

The punctured and reduced L DPC codeword (i.e., the L DPC codeword bits remaining after puncturing and reduction) is mapped to constellation symbols according to a corresponding mode through various modulation schemes, such as QPSK, 16-QAM, 64-QAM, or 256-QAM, and the constellation symbols may be transmitted to the receiver 200 through a frame.

Thus, puncturers 217 and 318 are based on N_{FEC_temp}To determine the number N of L DPC codeword bits constituting the L DPC codeword after puncturing and reduction_FEC(wherein, N is_FECIs an integer multiple of the modulation order) and determines the number N of bits that need to be punctured based on the reduced L DPC codeword bits_puncTo obtain N_FEC。

When zero bits are not padded, the L DPC codeword may be formed of BCH-encoded bits and L DPC parity bits, and the reduction may be omitted.

In addition, in L1-basic mode 1 and L1-detail mode, repetition is performed, and thus, the number of reduced and punctured L DPC codewords is equal to N_FEC+N_repeat。

The puncturers 217 and 318 may puncture L DPC parity bits as many as the calculated number.

In this case, puncturers 217 and 318 may puncture the last N of all L DPC codewords_puncThat is, the puncturers 217 and 318 may puncture N starting from the last L DPC parity bits_puncAnd (4) a bit.

In detail, when repetition is not performed, the parity-permuted L DPC codeword includes only L DPC parity bits generated by L DPC encoding.

In this case, the puncturers 217 and 318 may puncture the last N of all the parity permuted L DPC codewords_puncThus, N starting from the last L DPC parity bit among L DPC parity bits generated by L DPC encoding_puncOne bit may be punctured.

When repetition is performed, the parity permuted and repeated L DPC codeword includes repeated L DPC parity bits and L DPC parity bits generated by L DPC encoding.

In this case, as shown in fig. 15 and 16, the puncturers 217 and 318 may respectively perform parity permutation and repetition on the last N DPC codewords of all L DPC codewords_puncThe bits are punctured.

In detail, the repeated L DPC parity bits are located between the L DPC information bits and the L DPC parity bits generated through L DPC encoding, and thus the puncturer 217 and the puncturer 318 may respectively perform puncturing for N starting from the last L DPC parity bits among the L DPC parity bits generated through L DPC encoding_puncThe bits are punctured.

Thus, puncturers 217 and 318 may each pair N starting from the last L DPC parity bit_puncThe bits are punctured.

N_puncIs 0 or a positive integer, repetition is applicable only to L1-basic mode 1 and L1-detailed mode 1.

The foregoing example describes that repetition is performed and then puncturing is performed, which is just one example. In some cases, after puncturing is performed, repetition may be performed.

The additional parity generator 319 may select bits from the L DPC parity bits to generate Additional Parity (AP) bits.

In this case, the additional parity bits may be selected from L DPC parity bits generated based on L1-detail signaling transmitted in the current frame and transmitted to the receiver 200 through a frame (i.e., a previous frame) before the current frame.

In detail, L1-detail signaling is DPC encoded by L, and L DPC parity bits generated through L DPC encoding are added to L1-detail signaling to constitute L DPC codeword.

Further, puncturing and reduction may be performed on the L DPC codeword, and the punctured and reduced L DPC codeword may be mapped to a frame to be transmitted to the receiver 200. here, when repetition is performed according to a corresponding mode, the punctured and reduced L DPC codeword may include repeated L DPC parity bits.

In this case, L1-detail signaling corresponding to each frame may be transmitted to the receiver 200 through each frame along with L DPC parity bits, for example, a punctured and reduced L DPC codeword including L1-detail signaling corresponding to the (i-1) th frame may be mapped to the (i-1) th frame to be transmitted to the receiver 200, and a punctured and reduced L DPC codeword including L1-detail signaling corresponding to the i-th frame may be mapped to the i-th frame to be transmitted to the receiver 200.

The additional parity generator 319 may select at least some L DPC parity bits of L DPC parity bits generated based on L1-detail signaling transmitted in the i-th frame to generate additional parity bits.

In detail, some L DPC parity bits among L DPC parity bits generated by performing L DPC encoding on L-detail signaling are punctured and then are not transmitted to the receiver 200 in which case the additional parity generator 319 may select at least some L DPC parity bits among L DPC parity bits generated by performing L DPC encoding on L-detail signaling transmitted in the i-th frame, thereby generating additional parity bits.

In addition, the additional parity generator 319 may select at least some L DPC parity bits of the L DPC parity bits to be transmitted to the receiver 200 through the ith frame to generate additional parity bits.

In detail, L DPC parity bits included in the punctured and reduced L DPC codeword to be mapped to the i-th frame may be composed of only L DPC parity bits generated through L DPC encoding or L DPC parity bits generated through L DPC encoding and repeated L DPC parity bits according to the corresponding mode.

In this case, the additional parity generator 319 may select at least some L DPC parity bits of L DPC parity bits included in the punctured and reduced L DPC codeword to be mapped to the i-th frame to generate additional parity bits.

The additional parity bits may be transmitted to the receiver 200 through a frame preceding the ith frame, i.e., the (i-1) th frame.

That is, the transmitter 100 may transmit not only the punctured and reduced L DPC codeword including L1-detail signaling corresponding to the (i-1) th frame to the receiver 200 through the (i-1) th frame but also additional parity bits generated based on L1-detail signaling transmitted in the i-th frame to the receiver 200 through the (i-1) th frame.

In this case, the frame to which the additional parity bits are transmitted may be a temporally foremost frame among frames prior to the current frame.

For example, the additional parity bits have the same leading primary/secondary version as the current frame in frames preceding the current frame, and may be transmitted in the temporally foremost frame.

In some cases, the additional parity generator 319 may not generate additional parity bits.

In this case, the transmitter 100 may transmit information on whether additional parity bits for L1-detail signaling of the next frame are transmitted through the current frame to the receiver 200 using L1-basic signaling transmitted through the current frame.

For example, the use of additional parity bits for L1-Detail signaling that directs the next frame of the primary/secondary version that is the same as the current frame may be signaled by field L1B _ L1 _ Detail _ additional _ parity _ mode in the L1-base parameters of the current frame in Detail, when L1B _ L1 _ Detail _ additional _ parity _ mode in the L1-base parameters of the current frame is set to "00", additional parity bits for L1-Detail signaling of the next frame are not sent in the current frame.

As such, to additionally improve the robustness of L1-detail signaling, additional parity bits may be sent in frames preceding the current frame in which L1-detail signaling for the current frame was sent.

Fig. 17 shows an example in which L1-additional parity bits for the details signaling of the ith frame are transmitted in the preamble of the (i-1) th frame.

Fig. 17 shows that L1 detail signaling transmitted through the ith frame is divided into M blocks by division, and each of the divided blocks is FEC-encoded.

Thus, M L DPC codewords (i.e., L DPC codeword comprising L DPC information bits L1-d (i) _1 and its parity bits parity for L1-d (i) _1, …, L DPC codeword comprising L DPC information bits L1-d (i) _ M and its parity bits parity for L1-d (i) _ M) are mapped to the i-th frame to be transmitted to receiver 200.

In this case, additional parity bits generated based on L1-detail signaling transmitted in the ith frame may be transmitted to the receiver 200 through the (i-1) th frame.

In detail, additional parity bits (i.e., AP for L1-d (i) _1, …, AP for L1-d (i) _ M generated based on L1-detail signaling transmitted in the ith frame) may be mapped to a preamble of the (i-1) th frame to be transmitted to the receiver 200. as a result of using the additional parity bits, a diversity gain for L1 signaling may be obtained.

Hereinafter, a method for generating additional parity bits will be described in detail.

The additional parity bit generator 319 calculates a temporary number N of additional parity bits based on the following equation 44_{AP_temp}。

In addition, K denotes a ratio of additional parity bits to half of the total number of bits of the transmitted encoded L1-detail signaling block (i.e., bits constituting the L1-detail signaling block which are repeated, punctured, and have zero bits removed).

Here, the value of L1B _ L1 _ Detail _ additional _ parameter _ mode associated with L-Detail signaling of the i-th frame (i.e., frame (# i)) may be sent in the (i-1) -th frame (i.e., frame (# i-1)).

As described above, when the L1 detail patterns are 2, 3, 4, 5, 6, and 7, since repetition is not performed, N is N in equation 44 above_repeat Is 0.

In addition, the additional parity generator 319 calculates the number N of additional parity bits based on the following equation 45_AP. Thus, the number of additional parity bits N_APMay be an integer multiple of the modulation order.

Here, the first and second liquid crystal display panels are,

is the largest integer not greater than x here, η_MODIs a modulation order, for example, η when L1-detail signaling is modulated by QPSK, 16-QAM, 64-QAM or 256-QAM according to the corresponding mode_MODMay be 2, 4, 6 or 8.

Next, the additional parity generator 319 may select as many bits as the calculated number of bits among the L DPC parity bits to generate additional parity bits.

In detail, when the number of punctured L DPC parity bits is equal to or greater than the number of additional parity bits to be generated, the additional parity generator 319 may select as many bits as the calculated number starting from the first L DPC parity bit among the punctured L DPC parity bits to generate the additional parity bits.

When the number of punctured L DPC parity bits is less than the number of additional parity bits to be generated, the additional parity generator 319 may first select all the punctured L DPC parity bits and additionally select as many bits as a number obtained by subtracting the number of punctured L DPC parity bits from the number of additional parity bits to be generated, starting with the first L DPC parity bit among the L DPC parity bits included in the L DPC codeword, to generate the additional parity bits.

In detail, when the repetition is not performed, L DPC parity bits included in the repeated L DPC codeword are L DPC parity bits generated by L DPC encoding.

In this case, the additional parity generator 319 may first select all the punctured L DPC parity bits and additionally select as many bits as obtained by subtracting the number of punctured L DPC parity bits from the number of additional parity bits to be generated, starting with the first L DPC parity bit among the L DPC parity bits generated through L DPC encoding, to generate the additional parity bits.

Here, the L DPC parity bits generated through L DPC encoding are divided into unpunctured L DPC parity bits and punctured L DPC parity bits as a result, when bits are selected starting from the first bit among L DPC parity bits generated through L DPC encoding, the bits may be selected in the order of the unpunctured L DPC parity bits and the punctured L DPC parity bits.

When the repetition is performed, the L DPC parity bits included in the repeated L DPC codeword are the repeated L DPC parity bits and L DPC parity bits generated through L DPC encoding, here, the repeated L DPC parity bits are located between the L DPC information bits and the L DPC parity bits generated through L DPC encoding.

In this case, the additional parity generator 319 may first select all of the punctured L DPC parity bits and additionally select as many bits as obtained by subtracting the number of punctured L DPC parity bits from the number of additional parity bits, starting with the first L DPC parity bit among the repeated L DPC parity bits, to generate the additional parity bits.

Here, when bits are selected starting from the first bit among the repeated L DPC parity bits, the bits may be selected in the order of the repeated bits and the L DPC parity bits generated through L DPC encoding, and in addition, among the L DPC parity bits generated through L DPC encoding, the bits may be selected in the order of the non-punctured L DPC parity bits and the punctured L DPC parity bits.

Hereinafter, a method for generating additional parity bits according to an exemplary embodiment will be described in more detail with reference to fig. 18 to 20.

FIGS. 18 through 20 are diagrams for describing a method of generating additional parity bits when repetition is performed according to an exemplary embodiment, in this case, a repeated L DPC codeword

May be represented as shown in fig. 18.

First, when N is_AP≤N_puncIn time, as shown in fig. 19, the additional parity generator 319 may select N starting from the first L DPC parity bit among the punctured L DPC parity bits_APBits to generate additional parity bits.

Thus, for the additional parity bits, the punctured L DPC parity bits

That is, the additional parity generator 319 may select N starting from the first bit among the punctured L DPC parity bits_APBits to generate additional parity bits.

When N is present_AP＞N_puncThen, as shown in FIG. 20, an additional oddThe even parity generator 319 selects all of the punctured L DPC parity bits.

Thus, for the additional parity bits, all the punctured L DPC parity bits

May be selected.

In addition, the additional parity generator 319 may additionally select the top-N DPC parity bits from L DPC parity bits including the repeated L DPC parity bits and L DPC parity bits generated through L DPC encoding_AP-N_puncAnd (4) a bit.

That is, since the repeated L DPC parity bits and the L DPC parity bits generated through L DPC encoding are sequentially arranged, the additional parity generator 319 may additionally select N starting from the first L DPC parity bit among the repeated L DPC parity bits_AP-N_puncA parity bit.

Thus, for the additional parity bits, L DPC parity bits

May be additionally selected.

In this case, the additional parity generator 319 may add the additionally selected bits to the previously selected bits to generate additional parity bits, that is, as shown in fig. 20, the additional parity generator 319 may add the additionally selected L DPC parity bits to the punctured L DPC parity bits to generate additional parity bits.

As a result, for the additional parity bits,

may be selected.

As such, when the number of punctured bits is equal to or greater than the number of additional parity bits, the additional parity bits may be generated by selecting bits among the punctured bits based on the puncturing order. However, in other cases, all of the punctured bits and N may be selected_AP-N_puncAdditional parity bits are generated from the parity bits.

Since N is not performed when the repetition is not performed_repeat0, and thus a method for generating additional parity bits when repetition is not performed and N in fig. 18 to 20_repeatThe same applies to the case of 0.

In this case, the constellation for the additional parity bits may be generated by the same method as the constellation for the L1-detail signaling bits transmitted in the current frame, where the L1-detail signaling bits are repeated, punctured, and zero bits have been removed, in which case, as shown in FIG. 18, the additional parity bits may be added after the L1-detail signaling block in the L1-detail signaling frame prior to the current frame, after being mapped to the constellation.

The additional parity generator 319 may output additional parity bits to the bit demultiplexer 323.

As described above with reference to tables 9 and 10, the group-wise interleaving pattern defining the permutation order may have two patterns: a first mode and a second mode.

In detail, since the B value in the above equation 40 represents the minimum length of L DPC parity bits to be punctured, a predetermined number of bits may always be punctured according to the B value regardless of the length of input signaling, for example, in L1-detail mode 2, since B6036 and a bit group is formed of 360 bits, there is at least when the reduced length is 0

The groups of bits are always punctured.

In this case, since puncturing is performed starting from the last L DPC parity bit, a predetermined number of bit groups starting from the last bit group among a plurality of bit groups constituting L DPC parity bits interleaved in groups may always be punctured regardless of the reduced length.

For example, in L1-detail mode 2, the last 16 bit groups among 36 bit groups constituting L DPC parity bits interleaved by groups may always be punctured.

As a result, some of the group-wise interleaving patterns defining the permutation order represent bit groups that are always punctured, and thus, the group-wise interleaving patterns may be divided into two patterns. In detail, a pattern defining a remaining bit group except for a bit group to be always punctured among the group-wise interleaving patterns is referred to as a first pattern, and a pattern defining a bit group to be always punctured is referred to as a second pattern.

For example, in L1-detail mode 2, since the group-wise interleaving mode is defined as in table 9 above, an index (i.e., Y) indicating that the bit groups located in the 9 th bit group to the 28 th bit group after the group-wise interleaving are not subjected to the group-wise interleaving is indicated (i.e., Y)₉＝X_πp(9)＝X₉,Y₁₀＝X_πp(10)＝X₃₁,Y₁₁＝X_πp(11)＝X₂₃,..., Y₂₆＝X_πp(26)＝X₁₇,Y₂₇＝X_πp(27)＝X₃₅,Y₂₈＝X_πp(28)＝X₂₁) May be the first pattern and represents an index (i.e., Y) that a bit group located in a 29 th bit group to a 44 th bit group after the group interleaving is not subjected to the group interleaving₂₉＝X_πp(29)＝X₂₀,Y₃₀＝X_πp(30)＝X₂₄,Y₃₁＝X_πp(31)＝X₄₄,...,Y₄₂＝X_πp(42)＝X₂₈,Y₄₃＝X_πp(43)＝X₃₉,Y₄₄＝X_πp(44)＝X₄₂) Is referred to as a second mode.

As described above, the second mode defines a bit group that will always be punctured in the current frame regardless of the reduced length, and the first mode defines a bit group that will be additionally punctured when the reduced length is long, so that the first mode can be used to determine L DPC parity bits to be transmitted in the current frame after puncturing.

In detail, according to the number of L DPC parity bits to be punctured, more L DPC parity bits may be additionally punctured in addition to L DPC parity bits that are always punctured.

For example, in L1-detail mode 2, when the number of L DPC parity bits to be punctured is 7200, 20 bit groups need to be punctured and thus four (4) bit groups need to be additionally punctured in addition to 16 bit groups that will always be punctured.

In this case, the additionally punctured four (4) bit groups correspond to bit groups located at the 25 th to 28 th positions after the group-wise interleaving, and since the bit groups are determined according to (i.e., belong to) the first pattern, the first pattern may be used to determine the punctured bit groups.

That is, when L DPC parity bits are punctured more than the minimum value of L DPC parity bits to be punctured, it is determined which bit groups are to be additionally punctured according to which bit groups are located after a bit group to be always punctured.

That is, as in the foregoing example, when the number of L DPC parity bits to be punctured is 7200, four (4) bit groups (i.e., bit groups located at the 28 th, 27 th, 26 th, and 25 th positions after the group-by-group interleaving is performed) are additionally punctured in addition to the 16 bit groups to be always punctured, here, bit groups located at the 25 th to 28 th positions after the group-by-group interleaving are determined according to the first pattern.

In addition, the remaining L DPC parity bits other than the punctured L DPC parity bits are transmitted through the current frame, and thus, the first mode may be considered for determining the bit group transmitted in the current frame.

The second mode may be used to determine additional parity bits to be sent in a previous frame.

In detail, since bit groups determined to be always punctured are always punctured and then are not transmitted in the current frame, the bit groups only need to be located at positions where bits are always punctured after group-wise interleaving. It is therefore immaterial where these groups of bits are located after interleaving in groups.

For example, in L1-detail mode 2, bit groups located at positions 20, 24, 44, …, 28, 39, and 42 before the group-wise interleaving need only be located at bit groups 29 to 44 after the group-wise interleaving.

As such, the second pattern defining the group of bits to be always punctured is used to identify the group of bits to be punctured. Therefore, defining the order between bit groups in the second pattern is meaningless in the puncturing operation, and thus, the second pattern defining a bit group to be always punctured may be considered not for puncturing.

However, in order to determine the additional parity bits, the position of the bit groups within the bit groups that will always be punctured needs to be considered.

In detail, since additional parity bits are generated by selecting as many bits as a predetermined number from the first bit among the punctured L DPC parity bits, bits included in at least some of bit groups to be always punctured may be selected as at least some of the additional parity bits according to the number of punctured L DPC parity bits and the number of additional parity bits to be generated.

That is, when the additional parity bits are selected more than the number of bit groups defined according to the first pattern, since the additional parity bits are sequentially selected from the beginning of the second pattern, the order of the bit groups belonging to the second pattern is meaningful in terms of the selection of the additional parity bits. As a result, a second pattern defining groups of bits that will always be punctured may be considered for determining additional parity bits.

For example, in L1-detail mode 2, the total number of L DPC parity bits is 12960, and the number of bit groups that will always be punctured is 16.

In this case, the second mode may be used to generate additional parity bits according to whether a value obtained by subtracting the number of L DPC parity bits to be punctured from the number of all L DPC parity bits and adding the subtraction result to the number of additional parity bits to be generated exceeds 7200 here, 7200 is the number of L DPC parity bits except for a bit group to be always punctured among bit groups constituting L DPC parity bits 7200 ═ × 360.

In detail, when a value obtained by subtracting and adding the above is equal to or less than 7200 (i.e., 12960-N)_punc+N_AP7200), additional parity bits may be generated according to the first mode.

However, when the value obtained by the above subtraction and addition exceeds 7200 (i.e., 12960-N)_punc+N_AP> 7200), additional parity bits may be generated according to the first and second patterns.

In detail, when 12960-N_punc+N_AP(> 7200), for the additional parity bits, a bit included in a bit group located at a 28 th position from a first L DPC parity bit among the punctured L DPC parity bits may be selected, and a bit included in a bit group located at a predetermined position from a 29 th position may be selected.

Here, a bit group to which the first L DPC parity bit among the punctured L DPC parity bits belongs and a bit group at the predetermined position (i.e., a bit group to which the finally selected L DPC parity bit belongs when sequentially selected from the first L DPC parity bit among the punctured L DPC parity bits) may be determined according to the number of punctured L DPC parity bits and the number of additional parity bits to be generated.

In this case, a bit group located at the 28 th position from the first L DPC parity bit among the punctured L DPC parity bits is determined according to the first pattern, and a bit group located at a predetermined position from the 29 th position is determined according to the second pattern.

As a result, additional parity bits are determined according to the first pattern and the second pattern.

As such, the first mode may be used to determine additional parity bits to be generated and L DPC parity bits to be punctured, and the second mode may be used to determine additional parity bits to be generated and L DPC parity bits to be always punctured regardless of the number of parity bits to be punctured by the puncturers 217 and 318.

The foregoing examples describe the inclusion of the first pattern and the second pattern in the group interleaving pattern, which is merely for convenience of explanation in terms of puncturing and additional parity. That is, the group-wise interleaving mode may be regarded as one mode without being divided into the first mode and the second mode. In this case, the group-wise interleaving may be regarded as being performed with one pattern for both puncturing and additional parity.

The values used in the foregoing examples (such as the number of punctured L DPC parity bits) are merely example values.

The zero removers 218 and 321 may remove zero bits padded by the zero padders 213 and 314 from the L DPC codeword output from the puncturers 217 and 318 and output the remaining bits to the bit demultiplexers 219 and 322.

Here, the removal operation not only removes the padded zero bits, but also may include outputting L remaining bits of the DPC codeword except for the padded zero bits.

In detail, the zero removers 218 and 321 may remove the K padded by the zero padders 213 and 314_ldpc-N_outerAnd zero bits. Thus, K_ldpc-N_outerThe padded zero bits are removed and thus may not be transmitted to the receiver 200.

For example, as shown in fig. 21, it is assumed that all bits in a first bit group, a fourth bit group, a fifth bit group, a seventh bit group, and an eighth bit group among a plurality of bit groups constituting the L DPC codeword are padded with zero bits, and some bits in the second bit group are padded with zero bits.

In this case, the zero removers 218 and 321 may remove zero bits padded to the first bit group, the second bit group, the fourth bit group, the fifth bit group, the seventh bit group, and the eighth bit group.

Thus, when the zero bits are removed, as shown in FIG. 21, the zero bits can be retained by K_sigAn information bit (i.e., K)_sigL1-basic signaling bit sum K_sigL1-detail signaling bits), 168 BCH parity bits (i.e., BCH FEC), and N_inner-K_ldpc-N_puncOr N_inner-K_ldpc-N_punc+N_repeatL DPC codewords formed of parity bits.

That is, when repetition is performed, the length of all L DPC code words becomes N_FEC+N_repeat. Here, N_FEC＝N_outer+N_{ldpc_parity}-N_puncHowever, in the mode in which repetition is not performed, the length of all L DPC codewords becomes N_FEC。

The bit demultiplexers 219 and 322 may interleave the bits output from the zero removers 218 and 321, demultiplex the interleaved bits, and then output them to the constellation mappers 221 and 324.

For this purpose, the bit demultiplexer 219 and the bit demultiplexer 322 may include a block interleaver (not shown) and a demultiplexer (not shown).

First, a block interleaving scheme performed in the block interleaver is shown in fig. 22.

In detail, N after zero bits are removed_FECOr N_FEC+N_repeatBits of length may be written into the block interleaver consecutively in columns. Here, the number of columns of the block interleaver is equal to the modulation order, and the number of rows is N_FEC/η_MODOr (N)_FEC+N_repeat)/η_MOD。

In addition, in the read operation, bits of one constellation symbol may be sequentially read in a row direction to be input to the demultiplexer. The operation may continue to the last row of columns.

That is, N_FECOr (N)_FEC+N_repeat) The bits may be written in a plurality of columns in a column direction from a first row of the first column, and the bits written in the plurality of columns are sequentially read in a row direction from the first row to a last row of the plurality of columns. In this case, the bits read in the same row may constitute one modulation symbol.

The demultiplexer may demultiplex bits output from the block interleaver.

In detail, the demultiplexer may demultiplex each of the block-interleaved bit groups (i.e., bits output when reading bit by bit in the same row of the block interleaver within the bit group) before the bits are mapped to the constellation.

In this case, there may be two mapping rules according to the modulation order.

In detail, when QPSK is used for modulation, since the reliability of bits within a constellation symbol is the same, the demultiplexer does not perform a demultiplexing operation on a bit group. Accordingly, the bit groups read and output from the block interleaver can be mapped to QPSK symbols without a demultiplexing operation.

However, when high-order modulation is used, the demultiplexer may perform demultiplexing on the bit group read and output from the block interleaver based on the following equation 46. That is, the bit groups may be mapped to QAM symbols according to equation 46 below.

S_{demux_in(i)}＝{b_i(0)_，b_i(1)，b_i(2)，...，b_i(η_MOD-1)}，

S_{demux_out(i)}＝{c_i(0)，c_i(1)，c_i(2)，...，c_i(η_MOD-1)}，

c_i(0)＝b_i(i％η_MOD)，c_i(1)＝b_i((i+1)％η_MOD)，...，c_i(η_MOD-1)＝b_i((i+η_MOD-1)％η_MOD)...(46)

In equation 46 above,% represents modulo operation, η_MODIs the modulation order.

In addition, i is a bit group index corresponding to a row index of the block interleaver. That is, the bit group S mapped to the output of each of the QAM symbols_{demux_out(i)}Can be indexed by bit group i at S_{demux_in(i)}Is cyclically shifted.

Fig. 23 shows an example of performing bit demultiplexing for a 16-non-uniform constellation (16-NUC) (i.e., NUC 16-QAM). The operation may be continued until all bit groups are read in the block interleaver.

The bit demultiplexer 323 may perform the same operation as that performed by the bit demultiplexer 219 and the bit demultiplexer 322 on the additional parity bits output from the additional parity generator 319, and output the block-interleaved and demultiplexed bits to the constellation mapper 325.

The constellation mappers 211, 324, and 325 may map bits output from the bit demultiplexers 219, 322, and 323 to constellation symbols, respectively.

That is, each of the constellation mapper 211, the constellation mapper 324, and the constellation mapper 325 may use the constellation to map S according to the corresponding pattern_{demux_out(i)}Mapping to a cell word. Here, S_{demux_out(i)}Can be of the same number as the modulation orderBits.

In detail, the constellation mappers 211, 324, and 325 may map bits output from the bit demultiplexers 219, 322, and 323 to constellation symbols using QPSK, 16-QAM, 64-QAM, 256-QAM, etc., according to the corresponding modes.

In this case, the constellation mappers 211, 324, and 325 may use NUC, that is, the constellation mappers 211, 324, and 325 may use NUC 16-QAM, NUC 64-QAM, or NUC 256-QAM, modulation schemes applied to L1-basic signaling and L1-detail signaling according to corresponding modes are shown in table 4 above.

Meanwhile, the transmitter 100 may map the constellation symbols to a frame and transmit the mapped symbols to the receiver 200.

In detail, the transmitter 100 may map constellation symbols corresponding to each of L1-basic signaling and L1-detail signaling output from the constellation mapper 221 and the constellation mapper 324, and map constellation symbols corresponding to additional parity bits output from the constellation mapper 325 to preamble symbols of a frame.

In this case, the transmitter 100 may map additional parity bits generated based on L1-detail signaling transmitted in the current frame to a frame preceding the current frame.

That is, the transmitter 100 may map L DPC codeword bits including L1-basic signaling corresponding to the i-1 th frame, map L DPC codeword bits including L1-detail signaling corresponding to the i-1 th frame, and additionally map additional parity bits generated by selecting from L DPC parity bits generated based on L1-detail signaling corresponding to the i-1 th frame and may transmit the mapped bits to the receiver 200.

Further, in addition to the L1 signaling, the transmitter 100 may map data to data symbols of a frame and transmit a frame including L1 signaling and data to the receiver 200.

In this case, since L1 signaling includes signaling information related to data, the signaling related to data mapped to each data may be mapped to a preamble of a corresponding frame, for example, the transmitter 100 may map L1 signaling including signaling information related to data mapped to an ith frame to the ith frame.

As a result, the receiver 200 may acquire data from a corresponding frame and process the data using signaling acquired from the frame.

Fig. 24 and 25 are block diagrams for describing a configuration of a receiver according to an exemplary embodiment.

In detail, as shown in fig. 24, the receiver 200 may include a constellation demapper 2410, a multiplexer 2420, a log likelihood ratio (LL R) inserter 2430, a LL R combiner 2440, a parity de-permutator 2450, a L DPC decoder 2460, a zero remover 2470, a BCH decoder 2480, and a descrambler 2490 for processing L1-basic signaling.

In addition, as shown in fig. 25, the receiver 200 may include constellation demappers 2511 and 2512 for processing L1 detail signaling, multiplexers 2521 and 2522, a LL R inserter 2530, a LL R combiner 2540, a parity de-permutator 2550, a L DPC decoder 2560, a zero remover 2570, a BCH decoder 2580, a descrambler 2590, and a de-partitioner 2595.

Here, the components shown in fig. 24 and 25 are components that perform functions corresponding to those of the components shown in fig. 8 and 9, respectively, which is merely an example, and in some cases, some of the components may be omitted and changed and other components may be added.

The receiver 200 may acquire frame synchronization using the preamble of the frame and receive L1-basic signaling from the preamble of the frame using information included in the preamble for processing L1-basic signaling.

In addition, the receiver 200 may receive L-1 detail signaling from the preamble using information included in L1-basic signaling for processing L1-detail signaling, and receive broadcast data required by a user from data symbols of a frame using L1-detail signaling.

Accordingly, the receiver 200 may determine the modes used at the transmitter 100 for processing L1-basic signaling and L1-detail signaling, and process the signal received from the transmitter 100 according to the determined modes to receive L1-basic signaling and L1-detail signaling, for this purpose, the receiver 200 may previously store information on parameters used at the transmitter 100 to process signaling according to the corresponding modes.

Thus, L1-basic signaling and L1-detail signaling can be sequentially acquired from the preamble in the description of fig. 24 and 25, components performing the same function will be described together for convenience of explanation.

The constellation demapper 2510, the constellation demapper 2611, and the constellation demapper 2612 demodulate a signal received from the transmitter 100.

In detail, the constellation demapper 2510, the constellation demapper 2611, and the constellation demapper 2612 are components corresponding to the constellation mapper 211, the constellation mapper 324, and the constellation mapper 325 of the transmitter 100, respectively, and may demodulate a signal received from the transmitter 100 and generate a value corresponding to a bit transmitted from the receiver 100.

That is, as described above, the transmitter 100 maps the L DPC codeword including L1-basic signaling and the L DPC codeword including L1-detail signaling to the preamble of the frame and transmits the mapped L DPC codeword to the receiver 200, and in addition, the transmitter 100 may map additional parity bits to the preamble of the frame and transmit the mapped bits to the receiver 200.

As a result, the constellation demapper 2510 and the constellation demapper 2611 may produce values corresponding to L DPC codeword bits including L1-basic signaling and L DPC codeword bits including L1-detail signaling.

For this purpose, the receiver 200 may previously store information on a modulation scheme used by the transmitter 100 to modulate L1-basic signaling, L1-detail signaling, and additional parity bits according to corresponding modes, and thus, the constellation demapper 2510, constellation demapper 2611, and constellation demapper 2612 may demodulate a signal received from the transmitter 100 according to corresponding modes to generate values corresponding to L DPC codeword bits and additional parity bits.

The value corresponding to the bit transmitted from the transmitter 100 is a value calculated based on the probability that the received bit is 0 and 1, and instead, the probability itself may be used as the value corresponding to each bit.

In detail, the L R value may represent a ratio of a probability that a bit transmitted from the transmitter 100 is 0 to a probability that the bit is 1, and the LL R value may represent a value obtained by taking a logarithm of the probability that the bit transmitted from the transmitter 100 is 0 to the probability that the bit is 1.

The foregoing example uses either the L R value or the LL R value, which is merely one example, according to another exemplary embodiment, the received signal itself may be used in addition to the L R or LL R value.

The multiplexers 2520, 2621, and 2622 perform multiplexing on the LL R values output from the constellation demapper 2510, the constellation demapper 2611, and the constellation demapper 2612.

In detail, the multiplexers 2520, 2621, and 2622 are components corresponding to the bit demultiplexer 219, the bit demultiplexer 322, and the bit demultiplexer 323 of the transmitter 100, and may perform operations corresponding to the operations of the bit demultiplexer 219, the bit demultiplexer 322, and the bit demultiplexer 323, respectively.

For this purpose, the receiver 200 may previously store information on parameters used by the transmitter 100 to perform demultiplexing and block interleaving, and thus, the multiplexers 2520, 2621, and 262 may inversely perform demultiplexing and block interleaving operations of the bit demultiplexers 219, 322, and 323 on the LL R values corresponding to the cell words in order to multiplex the LL R values corresponding to the cell words in units of bits.

LL R inserters 2530 and LL R inserter 2630 may insert LL R values for punctured and reduced bits into LL R values output from multiplexer 2520 and multiplexer 2621, respectively in this case, LL R inserter 2530 and LL R inserter 2630 may insert a predetermined LL R value between LL R values output from multiplexer 2520 and multiplexer 2621, or into a head or tail of LL R values output from multiplexer 2520 and multiplexer 2621.

In detail, LL R inserters 2530 and LL R inserters 2630 are components corresponding to zero removers 218 and 321 and puncturers 217 and 318 of transmitter 100, respectively, and may perform operations corresponding to the operations of zero removers 218 and 321 and puncturers 217 and 318, respectively.

First, the LL R inserters 2530 and LL R inserter 2630 may insert LL R values corresponding to zero bits into the L DPC codeword at positions where the zero bits are filled in.

Accordingly, the LL R inserters 2530 and LL R inserter 2630 may determine positions of zero bits filled in L DPC codewords according to the corresponding modes and insert LL R values corresponding to the reduced zero bits into the corresponding positions.

In addition, the LL R inserters 2530 and LL R inserter 2630 may insert LL R values corresponding to the punctured bits at positions of the punctured bits in the L DPC codeword, in this case, LL R values corresponding to the punctured bits may be 0.

Accordingly, the LL R inserters 2530 and LL R inserters 2630 may determine the length of the punctured L DPC parity bits according to the corresponding mode and insert corresponding LL R values into positions where the L DPC parity bits are punctured.

When additional parity bits among the additional parity bits are selected from the punctured bits, the LL R inserter 2630 may insert LL R values corresponding to the received additional parity bits (instead of the LL R value '0' for the punctured bits) into the positions of the punctured bits.

LL R combiners 2540 and LL R combiner 2640 may combine (i.e., add) the LL 2R value output from LL 0R inserter 2530 and LL 1R inserter 2630 with the LL 3R value output from multiplexer 2622 however, LL 4R combiners 2540 and LL R combiner 2640 are used to update the LL R value for a particular bit to a more correct value however, the LL R value for a particular bit may also be decoded from the received LL R value without LL R combiners 2540 and LL R combiner 2640 and therefore, in some cases, LL R combiners 2540 and LL R combiner 2640 may be omitted.

In detail, the LL R combiner 2540 is a component corresponding to the repeater 216 of the transmitter 100 and may perform an operation corresponding to the operation of the repeater 216 alternatively, the LL R combiner 2640 is a component corresponding to the repeater 317 and the additional parity generator 319 of the transmitter 100 and may perform an operation corresponding to the operation of the repeater 317 and the additional parity generator 319.

First, the LL R combiners 2540 and LL R combiners 2640 may combine the LL R value corresponding to the repetition bits with other LL R values here, the other LL R values may be the bits that are the basis for the generation of the repetition bits by the transmitter 100, i.e., the LL R value of the L DPC parity bits selected as the repetition object.

That is, as described above, the transmitter 100 selects bits from the L DPC parity bits and repeats the selected bits between the L DPC information bits and the L DPC parity bits generated through L DPC encoding, and transmits the repeated bits to the receiver 200.

As a result, the LL R value for the L DPC parity bits may be formed from the LL 1R value for the repeated LL 0DPC parity bits and the LL R value for the non-repeated L DPC parity bits (i.e., the L DPC parity bits generated by L DPC encoding.) accordingly, the L LR combiners 2540 and LL R combiner 2640 may combine the LL R values for the same LDPC parity bits.

To this end, the receiver 200 may previously store information on parameters used by the transmitter 100 to perform repetition according to a corresponding pattern, as a result, the LL R combiners 2540 and LL R combiner 2640 may determine the length of the repeated L DPC parity bits, determine the positions of the bits on which the repetition is based, and combine LL R values for the repeated L DPC parity bits with LL R values for the L DPC parity bits on which the repetition is based and generated through L DPC encoding.

For example, as shown in fig. 26 and 27, the LL R combiners 2540 and LL R combiner 2640 may combine the LL R value for the repeated L DPC parity bits with the LL R value for the L DPC parity bits that are the basis of the repetition and that are generated by L DPC encoding.

When L DPC parity bits are repeated n times, the LL R combiners 2540 and LL R combiners 2640 may combine the LL R values for the bits at the same position n times or less.

For example, FIG. 26 illustrates a case where some L DPC parity bits among L DPC parity bits other than punctured bits are repeated once, in this case, L0L 2R combiners 2540 and L1R combiner 2640 may combine L4R values for repeated L3 DPC parity bits with LL R values for L DPC parity bits generated through L DPC encoding and then output the combined LL R values, or output LL R values for received repeated L DPC parity bits or LL R values for received LDPC parity bits generated through LDPC encoding without combining them.

As another example, fig. 27 shows a case where some L DPC parity bits of the transmitted unpunctured L DPC parity bits are repeated twice, the remaining portion is repeated once, and the punctured L DPC parity bits are repeated once.

In this case, the LL R combiners 2540 and LL R combiner 2640 may process the remaining part repeated once and the punctured L DPC parity bits through the same scheme as the above-described scheme, however, the LL R combiners 2540 and LL R combiner 2640 may process the part repeated twice as follows.

In detail, the LL R combiners 2540 and LL R combiners 2640 may combine the LL 0R value for each of the first and second parts with the LL 2R value for the LL 1DPC parity bits, alternatively, the LL 3R combiners 2540 and LL 4R combiners 2640 may combine the LL 5R value for the first part with the LL 6R value for the L DPC parity bits, the LL 7R value for the second part with the LL 8R value for the L DPC parity bits, or the LL 9R value for the first part with the LL R value for the second part alternatively, the LL R combiners 2540 and LL R combiners 2640 may output LL R values for the first part, LL R values for the second part, the LL R values for the remaining part and the punctured bits, without separate combinations.

Additionally, the LL R combiner 2640 may combine the LL R value corresponding to the additional parity bits with other LL R values where the other LL R values may be L DPC parity bits that are the basis for generating the additional parity bits by the transmitter 100, i.e., LL R values for L DPC parity bits selected for generating the additional parity bits.

That is, as described above, the transmitter 100 may map additional parity bits for L1-detail signaling transmitted in the current frame to a previous frame and transmit the mapped bits to the receiver 200.

In this case, the additional parity bits may include L DPC parity bits that are punctured and not transmitted in the current frame, and in some cases, may also include L DPC parity bits transmitted in the current frame.

As a result, the LL R combiner 2640 may combine the LL R value for the additional parity bits received over the current frame with the LL R value inserted into the position of the punctured L DPC parity bits in the L DPC codeword received over the next frame and the LL R value for the L DPC parity bits received over the next frame.

To this end, the receiver 200 may previously store information on a parameter and/or a mode used by the transmitter 100 to generate the additional parity bits according to the corresponding mode, as a result, the LL R combiner 2640 may determine the length of the additional parity bits, determine the positions of the L DPC parity bits on which the additional parity bits are generated, and combine the LL R value for the additional parity bits with the LL R value for the L DPC parity bits on which the additional parity bits are generated.

The parity de-permutator 2550 and the parity de-permutator 2650 may de-permutate the LL R values output from the LL R combiner 2540 and the LL R combiner 2640, respectively.

In detail, the parity de-permutator 2550 and the parity de-permutator 2650 are components corresponding to the parity permutator 215 and the parity permutator 316 of the transmitter 100, and may perform operations corresponding to the operations of the parity permutator 215 and the parity permutator 316, respectively.

For this purpose, the receiver 200 may previously store information on parameters and/or modes used by the transmitter 100 to perform the group-wise interleaving and parity interleaving according to the corresponding modes, and thus, the parity de-permutator 2550 and the parity de-permutator 2650 may inversely perform the group-wise interleaving and parity interleaving operations of the parity permutator 215 and the parity permutator 316 on the LL R values corresponding to the L DPC codeword bits (i.e., perform the group-wise de-interleaving and parity de-interleaving operations) to perform parity de-permutation on the LL R values corresponding to the L DPC codeword bits, respectively.

The L DPC decoders 2560 and L DPC decoders 2660 may perform L DPC decoding based on LL R values output from the parity de-permutator 2550 and 2650, respectively.

In detail, the L DPC decoders 2560 and L DPC decoder 2660 are components corresponding to the L DPC encoders 214 and L DPC encoders 315 of the transmitter 100, and may perform operations corresponding to the operations of the L DPC encoders 214 and L DPC encoders 315, respectively.

For this purpose, the receiver 200 may previously store information on parameters used by the transmitter 100 to perform L DPC encoding according to the corresponding mode, and thus, the L DPC decoder 2560 may perform L DPC decoding according to the corresponding mode based on LL R values output from the parity de-permutator 2550 and the parity de-permutator 2650.

For example, the L DPC decoders 2560 and L DPC decoder 2660 may perform L DPC decoding based on LL R values output from the parity de-permuter 2550 and the parity de-permuter 2650 through iterative decoding based on a sum-product algorithm, and output error-corrected bits according to L DPC decoding.

The zero removers 2570 and 2670 may remove zero bits from the bits output from the L DPC decoders 2560 and L DPC decoders 2660, respectively.

In detail, the zero removers 2570 and 2670 are components corresponding to the zero padders 213 and 314 of the transmitter 100, and may perform operations corresponding to the operations of the zero padders 213 and 314, respectively.

To this end, the receiver 200 may previously store information on parameters and/or modes used by the transmitter 100 to pad the zero bits according to the corresponding modes as a result, the zero removers 2570 and 2670 may remove the zero bits padded by the zero padders 213 and 314 from the bits output from the L DPC decoders 2560 and L DPC decoder 2660, respectively.

The BCH decoders 2580 and 2680 may perform BCH decoding on the bits output from the zero removers 2570 and 2670, respectively.

In detail, the BCH decoders 2580 and 2680 are components corresponding to the BCH encoders 212 and 313 of the transmitter 100, and may perform operations corresponding to the operations of the BCH encoders 212 and 313, respectively.

For this purpose, the receiver 200 may previously store information on parameters used by the transmitter 100 to perform BCH encoding. As a result, the BCH decoders 2580 and 2680 may correct errors by performing BCH decoding on the bits output from the zero removers 2570 and 2670, and output the error-corrected bits.

The descramblers 2590 and 2690 may descramble bits output from the BCH decoders 2580 and 2680, respectively.

In detail, the descramblers 2590 and 2690 are components corresponding to the scramblers 211 and 312 of the transmitter 100, and may perform operations corresponding to the operations of the scramblers 211 and 312.

For such a purpose, the receiver 200 may previously store information on parameters used by the transmitter 100 to perform scrambling. As a result, the descramblers 2590 and 2690 may descramble and output bits output from the BCH decoders 2580 and 2680, respectively.

In addition, when the transmitter 100 does not perform the segmentation on the L1-detail signaling, the L1-detail signaling transmitted from the transmitter 100 may also be recovered.

However, when the transmitter 100 performs segmentation on the L1-detail signaling, the de-segmenter 2695 may perform de-segmentation on the bits output from the descrambler 2690.

In detail, the de-slicer 2695 is a component corresponding to the slicer 311 of the transmitter 100, and may perform an operation corresponding to the operation of the slicer 311.

To this end, the receiver 200 may previously store information on parameters used by the transmitter 100 to perform the segmentation, as a result, the de-segmenter 2695 may combine bits (i.e., L1-segments of the detail signaling) output from the descrambler 2690 to restore the L1-detail signaling before the segmentation.

Information on the length of the L1 signaling is provided as shown in fig. 28, and thus, the receiver 200 may calculate L1-the length of the detail signaling and the length of the additional parity bits.

Referring to fig. 28, since L1-basic signaling provides information about L1-detail total cells, the receiver 200 needs to calculate the length of L1-detail signaling and the length of additional parity bits.

In Detail, when L1-L1B _ L1 _ Detail _ additional _ parameter _ mode of basic signaling is not 0, since information related to a given L1B _ L1 _ Detail _ total _ cells indicates a total cell length (═ N _ cell)_{L1_detail_total_cells}) Accordingly, the receiver 200 may calculate based on equations 47 to 50 belowL1-Length of detail Signaling N_{L1_detail_cells}And length N of additional parity bits_{AP_total_cells}。

N_{L1_FEC_cells}＝(N_outer+N_repeat+N_{ldpc_parity}-N_punc)/η_MOD＝N_FEC/η_MOD…(47)

N_{L1_detail_cells}＝N_{L1D_FECFRAME}×N_{L1_FEC_cells}…(4₈)

N_{AP_total_cells}＝N_{L1_detail_total_cells}-N_{L1_detail_cells}…(49)

In this case, N is based on equations 47 through 49 above_{AP_total_cells}The value may be based on N, which may be obtained from information related to L1B _ L1 _ Detail _ total _ cells of L1-basic signaling_{L1_detail_total_cells}、N_FEC、N_{L1D_FECFRAME}And modulation order η_MODTo obtain the final product. By way of example, N_{AP_total_cells}May be calculated based on equation 50 below.

N_{AP_total_cells}＝N_{L1_detail_total_cells}-N_{L1D_EECFRAME}×N_FEC/η_MOD…(50)

Meanwhile, L1-syntax and field semantics of the basic signaling field are as in table 13 below.

[ Table 13]

As a result, the receiver 200 may be based on N sent into the received L1 detail cell_{AP_total_cells}The additional parity bits of one cell perform the receiver's operations on the additional parity bits in the next frame.

Fig. 29 is a flowchart for describing a segmentation method of a transmitter according to an exemplary embodiment.

First, information bits are divided into a plurality of blocks based on one of a plurality of preset reference values (S2710).

Next, first parity bits are generated by encoding the plurality of blocks (S2720), and a codeword including second parity bits is generated by encoding the plurality of blocks and the first parity bits (S2730).

In operation S2710, one of a plurality of preset reference values may be determined based on at least one of a code rate and whether repetition of at least a portion of codewords of the codewords is performed.

For example, the preset reference values may include 2352, 3072 and 6312.

In operation S2710, when the code rate is 3/15 and the second parity bit is repeated, the information bit may be divided based on 2352.

When the code rate is 3/15 and the second parity bit is not repeated, the information bit may be divided based on 3072 in operation S2710.

When the code rate is 6/15 and the second parity bit is not repeated, the information bit may be divided based on 6312 in operation S2710.

The detailed method for generating the additional parity bits is described above, and thus, a repetitive description is omitted.

According to an exemplary embodiment, a non-transitory computer-readable medium may be provided, in which a program that executes various methods described above is stored. The non-transitory computer-readable medium is not a medium (such as a register, a cache, a memory, etc.) in which data is temporarily stored, but means a medium in which data is at least semi-permanently stored and which can be read by a device (such as a microprocessor). In detail, various applications or programs described above may be stored and provided in a non-transitory computer readable medium, such as a Compact Disc (CD), a Digital Versatile Disc (DVD), a hard disk, a blu-ray disc, a Universal Serial Bus (USB), a memory card, a Read Only Memory (ROM), and the like.

According to an exemplary embodiment, at least one of the components, elements, modules or units represented by blocks as shown in fig. 1, 8, 9, 24 and 25 may be implemented as various numbers of hardware, software and/or firmware structures performing the respective functions described above. For example, at least some of these components, elements, modules or units may use direct circuit structures (such as memories, processors, logic circuits, look-up tables, etc.) that may perform various functions under the control of one or more microprocessors or other control devices. In addition, at least one of these components, elements, modules or units may be specially implemented by a module, program or portion of code containing one or more executable instructions for performing specific logical functions, and may be executed by one or more microprocessors or other control devices. In addition, at least one of these components, elements, modules or units may further include or be implemented by a processor, such as a Central Processing Unit (CPU), a microprocessor, or the like, which performs various functions. Two or more of these components, elements, modules or units may be combined into a single component, element, module or unit that performs all of the operations or functions of the combined two or more components, elements, modules or units. In addition, at least a part of the functions of at least one of these components, elements, modules or units may be performed by another one of these components, elements, modules or units. In addition, although a bus is not shown in the above block diagrams, communication between components, elements, modules, or units may be performed through the bus. The functional aspects of the above exemplary embodiments may be implemented in terms of algorithms executed on one or more processors. Further, the components, elements, modules or units represented by the blocks or process steps may employ any number of conventional techniques for electronic configuration, signal processing and/or control, data processing, and the like.

Although exemplary embodiments of the inventive concept have been illustrated and described above, the inventive concept is not limited to the above-described exemplary embodiments, but may be modified in various ways by those skilled in the art to which the inventive concept pertains without departing from the scope and spirit of the inventive concept disclosed in the claims.

Claims (4)

1. A transmitting apparatus that processes input bits in one of a plurality of modes, the transmitting apparatus comprising:

a division unit configured to divide an input bit into a plurality of blocks based on a division reference value of the pattern;

an encoding unit configured to encode the divided blocks based on a low density parity check L DPC code to generate a parity bit corresponding to each block, and

a repetition unit configured to perform repetition on parity bits corresponding to the plurality of blocks in a first pattern of the plurality of patterns,

wherein the plurality of patterns includes a second pattern that is repeatedly not executed,

wherein the division reference value of the second pattern, for which repetition is not performed, is different from the division reference value of the first pattern.

2. The transmission apparatus of claim 1, wherein the repetition unit performs the repetition in the first pattern by adding one or more bits of the parity bits corresponding to each block to the corresponding each block.

3. The transmission apparatus of claim 1, wherein in the first mode, the division reference value is 2352 and the code rate of the L DPC code is 3/15.

4. The transmission apparatus of claim 1, wherein in a second mode in which repetition is not performed, the division reference value is one of 3072 or 6312 and the code rate of the L DPC code is one of 3/15 or 6/15.

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