CN107564973B

CN107564973B - Cell, cell matrix, solar cell and preparation method of cell

Info

Publication number: CN107564973B
Application number: CN201610512518.2A
Authority: CN
Inventors: 孙翔; 姚云江; 姜占锋
Original assignee: BYD Co Ltd
Current assignee: BYD Co Ltd
Priority date: 2016-06-30
Filing date: 2016-06-30
Publication date: 2020-07-10
Anticipated expiration: 2036-06-30
Also published as: CN107564973A

Abstract

The invention discloses a cell, a cell matrix, a solar cell and a preparation method of the cell, wherein the cell comprises the following components: the silicon chip, the positive grid line layer, the side electrode, first electrode, back grid line layer and second electrode, the silicon chip includes the silicon chip, the first type diffusion layer in front, the first type diffusion layer in back and the second type diffusion layer in back, the surface of a back of silicon chip includes first region and the second region that does not contact each other, the first type diffusion layer in back only establishes and is covered with on first region, the second type diffusion layer in back only establishes and is covered with on the second region, the positive grid line layer is established on the first type diffusion layer in front, the side electrode is established on the side surface of silicon chip and is connected with the positive grid line layer electricity, first electrode is established on the first type diffusion layer in back and is connected with the side electrode electricity, back grid line layer and second electrode electricity are connected and all establish on the second type diffusion layer in back. The battery piece has good leakage resistance and high power.

Description

Cell, cell matrix, solar cell and preparation method of cell

Technical Field

The invention relates to the technical field of solar cells, in particular to a cell, a cell matrix, a solar cell and a preparation method of the cell.

Background

In the crystalline silicon solar cell in the related art, the light receiving surface and the backlight surface are respectively provided with 2-3 silver main grid lines as the anode and the cathode of the cell, and the silver main grid lines not only consume a large amount of silver paste, but also shield incident light to cause the efficiency reduction of the cell. In addition, because the positive electrode and the negative electrode are respectively distributed on the light receiving surface and the backlight surface of the battery piece, when the battery pieces are connected in series, the negative electrode of the light receiving surface of the battery piece needs to be welded on the positive electrode of the backlight surface of the adjacent battery piece by adopting a welding strip, so that the problems of complicated welding process and more welding materials are caused, and the battery piece and the welding strip are easily damaged during welding and in a subsequent laminating process.

In addition, the cell matrix in the related art is usually formed by sequentially connecting 72 or 60 cells in series to form three loops formed by six strings of cells, at this time, at least three diodes are generally needed, so that a diode is additionally arranged on each loop for bypass protection, the diodes are usually arranged in a junction box of the cells, so that the cost of an integrated junction box is increased, the structural complexity of the cells is increased, and when a series assembly formed by connecting a plurality of cells in series is connected again in series, the use amount of connecting cables is large, the material waste is large, and the cost of a power station is increased.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a battery piece which is good in leakage resistance and high in power.

The invention also provides a preparation method of the battery piece.

The invention also provides a battery piece matrix with the battery piece.

The invention also provides a solar cell with the cell sheet matrix.

A battery sheet according to a first aspect of the invention includes: the silicon chip comprises a silicon substrate, a front first-class diffusion layer, a back first-class diffusion layer and a back second-class diffusion layer, wherein the back surface of the silicon substrate comprises a first region and a second region which are not in contact with each other, the front first-class diffusion layer is arranged on the light receiving surface of the silicon substrate, the back first-class diffusion layer is only arranged on and distributed on the first region, and the back second-class diffusion layer is only arranged on and distributed on the second region, wherein the back first-class diffusion layer and the front first-class diffusion layer are the same in type, and the back second-class diffusion layer and the front first-class diffusion layer are different in type; the front grid line layer is arranged on the front first-type diffusion layer; the side electrode is arranged on the side surface of the silicon wafer and is electrically connected with the front grid line layer; the first electrode is arranged on the first diffusion layer on the back surface and is electrically connected with the side electrode; the back grid line layer and the second electrode are electrically connected and are arranged on the back second-type diffusion layer.

The battery piece has good leakage resistance and high power.

In some embodiments, the outer edge of the first electrode, projected in the thickness direction of the silicon wafer, falls on the contour line of the first region.

In some embodiments, the back gate line layer and the second electrode are not stacked on each other and are in contact connection.

In some embodiments, the projection along the thickness direction of the silicon wafer, the outer edge of the back grid line layer and the second electrode are all located on the contour line of the second area.

In some embodiments, the back gate line layer includes a plurality of back sub-gate lines extending in a direction perpendicular to the length direction of the second electrode.

In some embodiments, the front side gate line layer includes a plurality of front side sub-gate lines extending in a direction perpendicular to the length direction of the side electrodes.

In some embodiments, the silicon wafer further comprises a side first type diffusion layer disposed on a side surface of the silicon substrate, and the side electrode is disposed on the side first type diffusion layer, wherein the side first type diffusion layer is of the same type as the front first type diffusion layer.

In some embodiments, at least one of the first region and the second region is a non-discrete region.

In some embodiments, the silicon wafer spans 20mm to 60mm in a direction perpendicular to the side electrodes.

In some embodiments, the silicon wafer is a rectangular sheet, the first electrode and the second electrode are respectively disposed adjacent to two long sides of the silicon wafer and extend along a length direction of the silicon wafer, and the side electrode is disposed on a side surface of one long side of the silicon wafer adjacent to the first electrode in a width direction of the silicon wafer.

In some embodiments, the silicon substrate is P-type, the front-side first-type diffusion layer is a phosphorus diffusion layer, and the back-side second-type diffusion layer is a boron diffusion layer.

In some embodiments, the silicon substrate is N-type, the front-side first-type diffusion layer is a boron diffusion layer, and the back-side second-type diffusion layer is a phosphorus diffusion layer.

In some embodiments, the battery cell comprises: and the anti-reflection layer is arranged between the front first-type diffusion layer and the front grid line layer.

In some embodiments, the antireflective layer is also disposed between the side electrode and the silicon substrate.

In some embodiments, the battery piece includes: and the passivation layer is arranged between the second-type diffusion layer on the back surface and the grid line layer on the back surface.

In some embodiments, the passivation layer is respectively disposed on and filled between the back surface first type diffusion layer and the back surface second type diffusion layer.

According to a second aspect of the invention, the method for manufacturing a battery piece is used for manufacturing the battery piece according to the first aspect of the invention, the silicon substrate comprises a side surface interlayer, the side surface interlayer is arranged on the side surface of the silicon substrate, and the side electrode is arranged on the side surface interlayer, and the method for manufacturing the battery piece comprises the following steps: a: obtaining the silicon substrate; b: preparing the front first-type diffusion layer, the side surface interlayer, the back first-type diffusion layer and the back second-type diffusion layer on the silicon substrate to obtain the silicon wafer; c: and preparing the first electrode, the back grid line layer, the second electrode, the front grid line layer and the side electrode on the silicon chip.

In some embodiments, the step a specifically includes: and dividing the square conventional silicon substrate body at least once according to the length-invariant rule to obtain a plurality of silicon substrates.

In some embodiments, the side spacers are side first-type diffusion layers distributed over the side surfaces, and step B specifically includes: preparing a first diffusion layer on the light receiving surface, the side surface and the first region of the silicon substrate to obtain the front first diffusion layer, the side first diffusion layer and the back first diffusion layer, and preparing a back second diffusion layer on the second region to obtain the back second diffusion layer.

The battery piece matrix according to the third aspect of the invention is formed by connecting the battery pieces according to the first aspect of the invention in series and/or in parallel.

The solar cell according to the fourth aspect of the present invention comprises a matrix of cells according to the third aspect of the present invention.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a schematic diagram of a light receiving side of a cell according to an embodiment of the invention;

FIG. 2 is a schematic view of the backlight side of the cell shown in FIG. 1;

FIG. 3 is a schematic side view of the cell shown in FIG. 2;

FIG. 4 is a schematic view of two of the battery plates shown in FIG. 1 connected in series using conductive tape;

FIG. 5 is a schematic view of FIG. 4 with the conductive strip removed;

FIG. 6 is a schematic diagram of a matrix of battery cells according to an embodiment of the invention;

fig. 7 is a circuit schematic of the cell matrix shown in fig. 6.

Reference numerals:

a cell matrix 1000; a solder strip 1001; a bus bar 1002;

a first cell array 100A; a second cell array 100B; a third cell array 100C;

a battery piece 100;

a silicon wafer 1; a silicon substrate 11; a front-side first-type diffusion layer 12; a lateral first-type diffusion layer 13; a back first-type diffusion layer 14; a back second-type diffusion layer 15;

an antireflection layer 101; a passivation layer 102;

a front gate line layer 2; a front sub-grid line 21; a side electrode 3; a first electrode 4; a second electrode 5;

a back gate line layer 6; the back side sub-grid lines 61.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the applicability of other processes and/or the use of other materials.

Next, a battery sheet 100 according to an embodiment of the first aspect of the invention is described with reference to the drawings. Wherein the battery piece 100 is The back contact type solar cell converts solar energy into electric energy.

The battery sheet 100 according to the embodiment of the present invention includes: silicon chip 1, front grid line layer 2, side electrode 3, first electrode 4, back grid line layer 6 and second electrode 5. The silicon wafer 1 comprises a silicon substrate 11, a front first-type diffusion layer 12, a back first-type diffusion layer 14 and a back second-type diffusion layer 15.

The silicon substrate 11 is in a shape of a plate, and two surfaces of the silicon substrate 11 in the thickness direction are a light receiving surface and a backlight surface respectively, and the light receiving surface and the backlight surface are connected through a side surface. For example, in a preferred embodiment of the present invention, the front first-type diffusion layer 12 is fully distributed on the light receiving surface of the silicon substrate 11, so as to reduce the processing difficulty of the front first-type diffusion layer 12, improve the processing efficiency, reduce the processing cost, and effectively improve the power of the battery piece 100.

The backlight surface of the silicon substrate 11 includes a first region and a second region, which do not intersect and do not contact each other, that is, the contour line of the first region does not contact the contour line of the second region.

The first region may be a non-discrete region, that is, when the first region is arbitrarily divided into a plurality of sub-regions, the plurality of sub-regions may be connected to form a continuous first region. The back surface first type diffusion layer 14 is only provided on the first region, that is, the back surface of the silicon substrate 11 except the first region is not provided with the back surface first type diffusion layer 14, and further, the back surface first type diffusion layer 14 is fully distributed on the first region, so that when the first region is a non-discrete continuous region, the back surface first type diffusion layer 14 can be non-discretely, that is, continuously arranged on the silicon substrate 11.

Therefore, the back-side first-type diffusion layer 14 is continuously, i.e., non-discretely, arranged on the silicon substrate 11, rather than discretely, i.e., discontinuously, and is scattered on the silicon substrate 11 in a discrete form, such as a scattered point, a zebra stripe, etc., so that the processing difficulty of the back-side first-type diffusion layer 14 is greatly reduced, the processing efficiency is improved, the processing cost is reduced, and the power of the battery piece 100 can be effectively improved.

The second region may be a non-discrete region, that is, when the second region is arbitrarily divided into a plurality of sub-regions, the plurality of sub-regions may be connected to form a continuous second region. The back surface second type diffusion layer 15 is provided only on the second region, i.e., the back surface of the silicon substrate 11 except the second region is not provided with the back surface second type diffusion layer 15. Further, the back surface second type diffusion layer 15 is spread over the second region, so that when the second region is a non-discrete continuous region, the back surface second type diffusion layer 15 may be non-discretely, i.e., continuously, arranged on the silicon substrate 11.

Therefore, the back surface second-type diffusion layer 15 is continuously, i.e., non-discretely, arranged on the silicon substrate 11, rather than discretely, i.e., discontinuously, and is scattered on the silicon substrate 11 in a discrete form, such as a scattered point, a zebra stripe, etc., so that the processing difficulty of the back surface second-type diffusion layer 15 is greatly reduced, the processing efficiency is improved, the processing cost is reduced, and the power of the battery piece 100 can be effectively improved.

The front grid line layer 2 is disposed on the front first-type diffusion layer 12, that is, the front grid line layer 2 may be directly or indirectly disposed on the front first-type diffusion layer 12, at this time, the front grid line layer 2 is disposed on the light receiving surface of the silicon wafer 1 and is opposite to the front first-type diffusion layer 12, that is, the front grid line layer 2 does not exceed the contour line of the front first-type diffusion layer 12 in projection along the thickness direction of the silicon wafer 1.

For example, in some embodiments of the present invention, the silicon wafer 1 may further include an anti-reflection layer 101, and the anti-reflection layer 101 may be disposed on the front-side first-type diffusion layer 12. Thus, when the silicon wafer 1 includes the anti-reflection layer 101, the front-side gate line layer 2 may be directly provided on the anti-reflection layer 101. And when the silicon wafer 1 does not include the anti-reflection layer 101, the front-side gate line layer 2 may be directly disposed on the front-side first-type diffusion layer 12. In addition, the anti-reflection layer 101 may be provided between the side electrode 3 and the side first type diffusion layer 13 as described herein, and in this case, the silicon wafer 1 may have the anti-reflection layer 101 on the entire light receiving surface and the outer surface of one side surface, thereby facilitating processing and manufacturing. Furthermore, it should be noted that the concept of the antireflection layer 101 described herein should be well known to those skilled in the art, and mainly functions to reduce reflection and enhance charge collection. For example, the material of the antireflective layer 101 may include, but is not limited to, TiO₂、Al₂O₃、SiNxOy、SiNxCy。

The first electrode 4 is disposed on the back first-type diffusion layer 14, that is, the first electrode 4 may be disposed directly or indirectly on the back first-type diffusion layer 14, and in this case, the first electrode 4 is disposed on the back surface of the silicon wafer 1 and is opposite to the first region, that is, the first electrode 4 does not exceed the first region when projected along the thickness direction of the silicon wafer 1.

For example, in some embodiments of the present invention, the silicon wafer 1 may further include a passivation layer 102, and the passivation layer 102 may be disposed on the back side first type diffusion layer 14. Thus, when the silicon wafer 1 comprises the passivation layer 102, the first electrode 4 may be provided directly on the passivation layer 102. Whereas when the silicon wafer 1 does not comprise the passivation layer 102, the first electrode 4 may be provided directly on the back side first type diffusion layer 14. In addition, the passivation layer 102 may also be disposed on the back second-type diffusion layer 15 and between the back first-type diffusion layer 14 and the back second-type diffusion layer 15, and in this case, the passivation layer 102 may be disposed on the outer surface of the whole back surface of the silicon wafer 1, so as to facilitate processing and manufacturing. Furthermore, it should be noted that the concept of the passivation layer 102 described herein should be well known to those skilled in the art, and it mainly serves to reduce reflection and enhance charge collection. For example, the material of the passivation layer 102 may include, but is not limited to, TiO₂、Al₂O₃、SiNxOy、SiNxCy。

The first region and the second region do not intersect and are not in contact with each other, so that the first electrode 4 with a large area can be processed, and preferably, the outer edge of the first electrode 4 falls on the contour line of the first region when projected along the thickness direction of the silicon wafer 1. Thus, the first region can be maximally utilized, and the power of the battery cell 100 can be increased. Here, it should be noted that the "outer edge" refers to the outline of a surface-shaped component (for example, the rectangular plate-shaped first electrode 4 and the rectangular plate-shaped second electrode 5 described herein), and the "outer edge" refers to the end points of both ends of a linear component (for example, the thin grid line described herein).

The back grid line layer 6 and the second electrode 5 are both arranged on the back second-type diffusion layer 15, that is, the back grid line layer 6 and the second electrode 5 can be directly or indirectly arranged on the back second-type diffusion layer 15, at this time, the back grid line layer 6 and the second electrode 5 are arranged on the backlight surface of the silicon wafer 1 and are opposite to the second region, that is, the back grid line layer 6 and the second electrode 5 do not exceed the second region along the projection of the thickness direction of the silicon wafer 1. Wherein the first electrode 4 is in contact with neither the back-side gate line layer 6 nor the second electrode 5.

For example, in some embodiments of the present invention, the silicon wafer 1 may further include a passivation layer 102, and the passivation layer 102 may be disposed on the backside second type diffusion layer 15. Thus, when the silicon wafer 1 includes the passivation layer 102, the back gate line layer 6 and the second electrode 5 may be directly provided on the passivation layer 102. And when the silicon wafer 1 does not include the passivation layer 102, the back gate line layer 6 and the second electrode 5 may be directly disposed on the back second-type diffusion layer 15.

In addition, it should be noted that, in some embodiments of the present invention, the back gate line layer 6 and the second electrode 5 may not be overlapped and connected in a contact manner, at this time, the back gate line layer 6 and the second electrode 5 are respectively and completely disposed on the back surface of the silicon wafer 1, and the edges of the back gate line layer and the second electrode are in direct contact electrical connection, so that the space can be fully utilized, and the power of the battery cell 100 is improved; in other embodiments of the present invention, the back gate line layer 6 and the second electrode 5 may be stacked on each other, and in this case, the stacked surface of the back gate line layer 6 and the second electrode 5 is disposed on the back surface of the silicon wafer 1.

The first region and the second region are not intersected and are not contacted with each other, so that the back grid line layer 6 and the second electrode 5 with large areas can be processed. Preferably, the outer edges of the back gate line layer 6 and the second electrode 5 as a whole projected in the thickness direction of the silicon wafer 1 all fall on the contour line of the second region. Thereby, the second region can be maximally utilized, and the power of the battery cell 100 can be increased. Here, it should be noted that "the outer edge of the entirety of the two members" means: all the outer edges of the two members except for the edge for contact connection are referred to, and in addition, for a surface-shaped member (for example, the rectangular plate-shaped first electrode 4 and the rectangular plate-shaped second electrode 5 described herein), "outer edges" refer to the outline thereof, and for a linear member (for example, the fine grid line described herein), "outer edges" refer to the end points at both ends thereof.

Here, it should be noted that the "first type diffusion layer" and the "second type diffusion layer" described herein are two different types of diffusion layers, and different types of charges can be collected when the conductive medium is disposed on (e.g., directly disposed on or indirectly disposed through the antireflective layer 101 or the passivation layer 102 described herein) the first type diffusion layer and the second type diffusion layer. In addition, it is noted that the concepts of antireflective and passivation layers described herein are well known to those skilled in the art, and both of them primarily function to reduce reflection and enhance charge collection.

Thus, the front first-type diffusion layer 12, the back first-type diffusion layer 14, and the side first-type diffusion layer 13 described herein in the "first-type diffusion layer" are the same kind of diffusion layer, and when a conductive medium is provided on the first-type diffusion layer, charges of the first kind can be collected; and the back second-type diffusion layer 15 in the "second-type diffusion layer" is another-type diffusion layer that can collect the second-type charges when the conductive medium is provided on the second-type diffusion layer. Here, it should be noted that the principle of the conductive medium collecting charges on the silicon chip should be well known to those skilled in the art, and will not be described in detail here.

For example, when the silicon substrate 11 is P-type silicon, the first type diffusion layer may be a phosphorus diffusion layer, in which case the conductive medium disposed on the phosphorus diffusion layer may collect negative charges, and the second type diffusion layer may be a boron diffusion layer, in which case the conductive medium disposed on the boron diffusion layer may collect positive charges. For another example, when the silicon substrate 11 is N-type silicon, the "first type diffusion layer" may be a boron diffusion layer, and the "second type diffusion layer" may be a phosphorus diffusion layer, which is not described herein again.

In this way, since the front-side gate line layer 2 is provided on (e.g., directly on or indirectly through the antireflective layer 101) the first-type diffusion layer, the front-side gate line layer 2 can collect the first-type charges (e.g., negative charges). And the back side gate line layer 6 is disposed (e.g., directly or indirectly through the passivation layer 102) on the second type diffusion layer so that the front and back side gate line layer 6 can collect the second type of charge (e.g., positive charge).

Specifically, the first electrode 4 is electrically connected to the front-side gate line layer 2 through the side electrode 3, so that the first kind of charges (e.g., negative charges) collected by the front-side gate line layer 2 can be transferred to the first electrode 4 (e.g., negative electrode); the second electrode 5 is electrically connected to the back gate line layer 6 so that the second kind of charges (e.g., positive charges) collected by the back gate line layer 6 can be transferred to the second electrode 5 (e.g., positive electrode). Thus, the first electrode 4 and the second electrode 5 can output electric energy as both positive and negative poles of the battery sheet 100.

In this way, the first electrode 4 can collect the first kind of charges through the front grid line layer 2 positioned on the light receiving side of the silicon wafer 1, and the second electrode 5 can collect the second kind of charges through the back grid line layer 6 positioned on the backlight side of the silicon wafer 1, so that the space utilization rate is effectively improved, the power of the battery piece 100 is further improved, and the battery piece 100 can become a beautiful and efficient double-sided battery.

It can be understood by those skilled in the art that the first electrode 4 and the second electrode 5 are electrodes with opposite polarities, and need to be insulated, i.e. not conducted, and not electrically connected to each other, at this time, the first electrode 4, and all components electrically connected to the first electrode 4, and the second electrode 5, and all components electrically connected to the second electrode 5, cannot be directly conducted, nor indirectly conducted through any external conductive medium, for example, may not be in contact with or isolated by an insulating material, so as to avoid short circuit connection between the first electrode 4 and the second electrode 5.

Specifically, the side electrode 3 is disposed on the side surface of the silicon wafer 1, that is, the side electrode 3 is not embedded inside the silicon wafer 1, so that the processing difficulty of the whole cell 100 can be reduced, the processing process can be simplified, the processing efficiency can be improved, and the processing cost can be reduced, and the front grid line layer 2 and the first electrode 4 can be electrically connected together simply and conveniently through the side electrode 3, thereby ensuring the reliability of the operation of the cell 100.

Further, the side electrodes 3 are provided on the side surfaces of the silicon wafer 1 means that the side electrodes 3 may be provided directly or indirectly on the side surfaces of the silicon substrate 11. For example, in some embodiments of the present invention, the side electrode 3 may be directly disposed on the side spacer, and in this case, in order to avoid short circuit between the first electrode 4 and the second electrode 5, an electrode having an insulating coating layer itself may be selected as the side electrode 3, so that the problem that the conductive medium in the side electrode 3 directly contacts the surface of the silicon substrate 11 without the first type diffusion layer or the second type diffusion layer to collect the second type of charge and transfer the second type of charge to the first electrode 4 can be avoided, thereby ensuring insulation between the first electrode 4 and the second electrode 5.

For example, in some other embodiments of the present invention, the silicon chip 1 may further include a side spacer, and the side spacer may be disposed on the side surface of the silicon substrate 11, and in this case, the side electrode 3 may be directly disposed on the side spacer to be indirectly disposed on the side surface of the silicon substrate 11. The side spacers are designed to insulate the first electrode 4 from the second electrode 5, i.e. when the side electrode 3 is arranged directly on the side spacers, no short-circuit connection of the first electrode 4 to the second electrode 5 occurs.

For example, the side spacers may be all insulating layers (i.e., side insulating layers), or all diffusion layers of the first type (i.e., side first diffusion layers 13), or a portion thereof may be insulating layers, and another portion thereof may be diffusion layers of the first type. When the side electrode 3 is directly provided on the insulating layer, the side electrode 3 is insulated from the silicon wafer 1 and can transfer only the electric charges collected in the front surface gate line layer 2 to the first electrode 4, so that the insulation of the first electrode 4 and the second electrode 5 can be ensured. When the side electrode 3 is directly disposed on the first type diffusion layer, the side electrode 3 can collect charges (charges of the first type) from the first type diffusion layer and transfer the charges (charges of the first type) to the first electrode 4 together with the charges collected by the front surface gate line layer 2, so that the insulation between the first electrode 4 and the second electrode 5 can be ensured, and the power of the battery cell 100 can be improved.

Here, it should be noted that the concepts of silicon substrate, diffusion layer, passivation layer, anti-reflection layer, etc. and the principle of collecting charges from the silicon substrate by the conductive medium are well known to those skilled in the art and will not be described in detail herein. In addition, in a preferred embodiment of the present invention, the front gate line layer 2 and the back gate line layer 6 may be conductive dielectric layers formed by a plurality of conductive thin gate lines arranged at intervals, wherein the thin gate lines may be formed by silver, so that on one hand, the conductive rate may be improved, and on the other hand, the light shielding area may be reduced, so as to increase the power of the battery piece 100.

In summary, according to the battery piece 100 of the embodiment of the invention, the front-side grid line layer 2 connected to the first electrode 4 is processed on the light receiving surface of the silicon wafer 1, and the back-side grid line layer 6 connected to the second electrode 5 is processed on the back surface of the silicon wafer 1, so that the battery piece 100 can be a double-sided battery, and the power is higher.

Moreover, by arranging the side electrode 3 on the side surface of the silicon substrate 11, the first electrode on the light receiving surface of the existing battery piece 100 can be moved from the light receiving side of the silicon chip 1 to the backlight side, so as to prevent the light receiving side of the silicon chip 1 from being shielded by the first electrode 4, improve the power of the battery piece 100, and ensure that the first electrode 4 and the second electrode 5 are both positioned on the same side of the silicon chip 1, thereby facilitating the electrical connection among a plurality of battery pieces 100, reducing the welding difficulty, reducing the usage amount of solder, and simultaneously reducing the damage probability of the battery pieces 100 during welding and in the subsequent lamination process.

In addition, the side electrodes 3 are arranged on the side surfaces of the silicon wafer 1, so that the processing difficulty of the battery piece 100 is greatly reduced (for example, processing procedures such as processing holes on the silicon wafer 1 and injecting conductive media into the holes are not needed), the processing speed is further improved, and the processing failure rate and the processing cost are reduced. In addition, when the side electrode 3 is provided on one side surface in the width direction of the silicon substrate 11, it is possible to effectively shorten the path of transferring charges from the light receiving side to the backlight side of the silicon wafer 1, increase the charge transfer rate, and thus improve the power of the battery cell 100 phase-changeably.

In one embodiment of the invention, the silicon wafer 1 has a span in the direction perpendicular to the side electrodes 3 of 20mm to 60 mm. That is, the silicon wafer 1 includes a set (two) of oppositely disposed side surfaces, one of which is provided with the side electrode 3, and the distance between the set of side surfaces is 20mm to 60 mm. For example, in the example shown in FIGS. 2 and 3, when the silicon wafer 1 is a rectangular plate and the side electrode 3 is provided on one of the long-side surfaces of the silicon wafer 1, the width of the silicon wafer 1 is 20mm to 60 mm. For example, in another example of the present invention (this example is not shown in the figure), when the silicon wafer 1 is a rectangular plate body and the side electrode 3 is provided on one broad side surface of the silicon wafer 1, the length of the silicon wafer 1 is 20mm to 60 mm. Therefore, the path for transferring charges from the light receiving surface to the backlight surface of the silicon wafer 1 can be shortened, so that the transfer rate of charges is improved, and the power of the battery piece 100 is improved.

For example, in a preferred example of the present invention, the silicon substrate 11 is a rectangular body, i.e., a rectangular body or a rectangular body. Here, it should be noted that "rectangular sheet" is to be understood in a broad sense, i.e. not limited to a strictly rectangular sheet, for example, a generally rectangular sheet, a rectangular sheet with rounded or chamfered corners at four corners, etc. also fall within the scope of the present invention. Thus, the processing of the battery sheet 100 is facilitated, and the connection between the

battery sheets

100 and 100 is facilitated.

Preferably, the silicon substrate 11 is a rectangular plate. For example, the silicon substrate 11 may be formed by dividing a square-sized silicon wafer body into a plurality of rectangular silicon substrates 11 in a manner such that the length of the silicon substrate is not changed (which means "dividing" rather than "performing a cutting process"), that is, the length of each silicon substrate 11 is equal to the length of the square-sized silicon wafer body, and the sum of the widths of the silicon substrates 11 is equal to the width of the square-sized silicon wafer body.

In a preferred embodiment of the present invention, the back gate line layer 6 includes a plurality of back sub-gate lines 61 extending in a direction perpendicular to the length direction of the second electrodes 5, that is, each of the back sub-gate lines 61 is perpendicular to the length direction of the second electrodes 5. Therefore, the charge transmission path of the back sub-grid line 61 can be shortened, the charge transmission efficiency can be improved, and the power of the battery piece 100 can be improved.

In a preferred embodiment of the present invention, the front surface gate line layer 2 includes a plurality of front surface sub-gate lines 21 extending in a direction perpendicular to the length direction of the side electrodes 3, that is, each front surface sub-gate line 21 is perpendicular to the length direction of the side electrodes 3. Therefore, the charge transmission path of the front sub-grid line 21 can be shortened, the charge transmission efficiency can be improved, and the power of the battery piece 100 can be improved.

The following description will explain a battery cell 100 according to an embodiment of the present invention, taking only the silicon wafer 1 as a rectangular sheet.

Preferably, the first region and the second region may be both rectangular, and the length of the first region and the length of the second region are both equal to the length of the silicon substrate 11, the sum of the widths of the first region and the second region is smaller than the width of the silicon substrate 11, the first region and the second region are spaced apart in the width direction of the silicon substrate 11, and preferably, the first region and the second region are respectively disposed adjacent to two long sides of the silicon substrate 11. That is, the silicon substrate 11 may be divided into a first region and a second region on both sides of two lines parallel to the long sides of the silicon substrate 11, and the region between the two lines is a gap region between the first region and the second region. Therefore, subsequent processing is facilitated. Of course, the present invention is not limited thereto, and the shapes of the first and second regions are not limited, and for example, the first and second regions may also be formed in a triangular shape, a semicircular shape, or the like.

Preferably, the first electrode 4 and the second electrode 5 are respectively disposed adjacent to two long sides of the silicon wafer 1 and extend along the length direction of the silicon wafer 1, and the side electrode 3 is disposed on the side surface of one long side of the silicon wafer 1 adjacent to the first electrode 4 (as shown in fig. 2 and 3), that is, the side electrode 3 is disposed on the side surface of one side of the silicon wafer 1 in the width direction adjacent to the first electrode 4. That is, the first electrode 4 and the second electrode 5 are spaced apart in the width direction of the silicon wafer 1 and are disposed respectively against the two long sides of the silicon wafer 1, and the side electrode 3 is disposed on one long-side surface of the silicon wafer 1, that is, on one side surface in the width direction of the silicon wafer 1, and on the side close to the first electrode 4. Therefore, the transmission path of the electric charge is shorter, the power of the battery piece 100 is higher, the processing of the battery piece 100 is simpler, and the connection between the battery piece 100 and the battery piece 100 is more convenient.

Preferably, the first electrode 4 and the second electrode 5 may be both rectangular sheet bodies and have the same length as that of the silicon substrate 11, so that two wide sides and one long side of the first electrode 4 and the second electrode 5 may be aligned with two wide sides and one long side of the silicon substrate 11, respectively, and thus the space may be fully utilized, the power of the battery piece 100 may be improved, and the subsequent connection of the battery piece 100 and the battery piece 100 may be facilitated.

In addition, the side electrode 3 may be formed in a sheet shape to fill up one side surface of the silicon wafer 1 in the width direction, so that the power of the battery cell 100 can be increased. Of course, the specific structure of the side electrode 3, the first electrode 4 and the second electrode 5 is not limited to this, for example, the side electrode 3, the first electrode 4 and the second electrode 5 may also be formed of a plurality of sub-electrodes distributed at intervals to form a discrete electrode.

Further, each back sub-gate line 61 extends along the width direction of the silicon chip 1. This reduces the charge transfer path and increases the power of the battery cell 100. Preferably, one end of each back sub-grid line 61 is aligned with one side edge of the second electrode 5 adjacent to the first electrode 4, and the other end is aligned with one side edge of the second region adjacent to the first region, projected along the thickness direction of the silicon wafer 1. Therefore, the distribution area of the back sub-grid lines 61 can be increased, so that the charge collection amount is increased, the power of the battery piece 100 is further increased, and the short circuit between the first electrode 4 and the second electrode 5 can be effectively avoided.

A method for manufacturing a battery cell 100 according to an embodiment of the second aspect of the present invention will be described below with reference to the accompanying drawings, in which, the silicon substrate comprises a side surface interlayer arranged on the side surface of the silicon substrate 11, and the side electrodes 3 are arranged on the side surface interlayer The preparation method is used for preparing the battery sheet 100 of the first aspect embodiment.

Specifically, the preparation method comprises the following steps A, B and C.

Step A: a silicon substrate 11 is obtained. For example, a plurality of silicon substrates 11 may be obtained by dividing a square conventional silicon substrate body at least once according to a rule of not changing the length.

And B: and preparing a front first-type diffusion layer 12, a side surface interlayer, a back first-type diffusion layer 14 and a back second-type diffusion layer 15 on a silicon substrate 11 to obtain the silicon wafer 1.

For example, in one specific example of the invention, the side spacers are side first-type diffusion layers 13. The step B specifically comprises the following steps: a first type diffusion layer is prepared on the light receiving surface, the side surface and the first region of the silicon substrate 11 to obtain a front first type diffusion layer 12 on the light receiving surface, a side first type diffusion layer 13 on the side surface and a back first type diffusion layer 14 on the backlight surface, and a second type diffusion layer is prepared on the second region to obtain a back second type diffusion layer 15 on the backlight surface.

Optionally, the silicon substrate 11 may be P-type (i.e., P-type silicon), in which case, the first type diffusion layer may be a phosphorus diffusion layer, and the second type diffusion layer may be a boron diffusion layer. Or alternatively, the silicon substrate 11 may be N-type (i.e., N-type silicon), in which case the first type diffusion layer may be a boron diffusion layer and the second type diffusion layer may be a phosphorus diffusion layer.

And C: a first electrode 4, a back grid line layer 6, a second electrode 5, a front grid line layer 2 and a side electrode 3 are prepared on a silicon chip 1. Specifically, the first electrode 4 is processed on the back-side first-type diffusion layer 14; processing a back grid line layer 6 and a second electrode 5 on the back second-type diffusion layer 15; processing a front grid line layer 2 on the front first-type diffusion layer 12; the side electrodes 3 are machined on the side spacers.

Here, it should be noted that, in order to further increase the power of the battery cell 100, the antireflection layer 101 may be prepared on the front-side first-type diffusion layer 12, so that the antireflection layer 101 is fully distributed on the front-side first-type diffusion layer 12, and then the front-side grid line layer 2 is processed on the antireflection layer 101 to be indirectly processed on the front-side first-type diffusion layer 12; meanwhile, the passivation layer 102 may be prepared on the back second-type diffusion layer 15, so that the passivation layer 102 is fully distributed on the back second-type diffusion layer 15 and the back first-type diffusion layer 14, of course, the passivation layer 102 may also extend to be spread on the back surface and the back first-type diffusion layer 14, and then the back grid line layer 6 is processed on the passivation layer 102 to be indirectly processed on the back second-type diffusion layer 15. Thus, the antireflection layer 101 and the passivation layer 102 are provided to reduce the reflection of sunlight from the front and back surfaces of the cell sheet 100, thereby effectively increasing the power of the cell sheet 100.

Therefore, the preparation method of the battery piece 100 according to the embodiment of the invention has the advantages of simple process, easy realization, low difficulty and low cost.

Hereinafter, a battery cell 100 and a method for manufacturing the same according to an embodiment of the present invention will be briefly described with reference to the accompanying drawings.

As shown in fig. 1, the battery cell 100 includes a silicon substrate 11 in a rectangular plate shape, a light receiving surface of the silicon substrate 11 has a front first-type diffusion layer 12, the front first-type diffusion layer 12 has an antireflection layer 101, the antireflection layer 101 has a front gate line layer 2, a side surface of the silicon substrate 11 in a width direction has a side first-type diffusion layer 13, the side first-type diffusion layer 13 has a side electrode 3, and a backlight surface of the silicon substrate 11 includes a first region and a second region which are spaced apart from each other, wherein the first region has a back first-type diffusion layer 14 thereon, the back first-type diffusion layer 14 has a first electrode 4 thereon, the second region has a back second-type diffusion layer 15 thereon, and the back second-type diffusion layer 15 has a back gate line layer 6 and a second electrode 5 thereon. Wherein the shapes and the arrangement positions of the components are shown in figures 1-3. Specifically, a passivation layer 102 may be disposed on the back first-type diffusion layer 14 and the back second-type diffusion layer 15, and between the back first-type diffusion layer 14 and the back second-type diffusion layer 15, and the first electrode 4, the back gate line layer 6, and the second electrode 5 are disposed on the passivation layer 102.

Specifically, when the battery piece 100 is prepared, a square conventional silicon substrate body (for example, a conventional silicon substrate with a specification of 156mm x 156mm) may be equally divided by a laser and cut into 2 to 8 parts of rectangular sheet-shaped silicon substrates 11 (for example, each having a length of 156mm) with constant length, and then the subsequent battery piece 100 manufacturing process is performed. Of course, the present invention is not limited thereto, and a silicon substrate 11 having a rectangular plate shape may be obtained by other means or processes. Here, it should be noted that, when the square conventional silicon substrate body is divided into 2 to 8 parts, on one hand, the distance of charge migration from the light receiving surface to the backlight surface can be shortened, so that the charge collection is efficient and easy, and the power of the battery piece 100 is improved, on the other hand, the silicon substrate 11 is easy to cut and process, and the solder consumed by the subsequent series-parallel battery pieces 100 is less, so that the overall power of the battery pieces 100 after series-parallel connection is improved, and the cost is reduced.

The method for manufacturing the cell 100 is described below by taking the silicon substrate 11 as P-type silicon as an example, and it is obvious to those skilled in the art that the method for manufacturing the cell 100 with the silicon substrate 11 as N-type silicon can be understood after reading the following technical solutions.

a1, cleaning and texturing: cleaning and removing dirt on each surface of the silicon substrate 11, and texturing to reduce the reflectivity of each surface of the silicon substrate 11;

a2, diffusion and junction preparation: respectively diffusing phosphorus and boron on the front and back surfaces of the silicon substrate 11 to prepare a first diffusion layer and a second diffusion layer, wherein the first diffusion layer extends from the light receiving surface of the silicon substrate 11 to the backlight surface from the side surface and comprises: the light source comprises a front first-type diffusion layer 12 positioned on a light receiving surface of a silicon substrate 11, a side first-type diffusion layer 13 positioned on a side surface of the silicon substrate 11, and a back first-type diffusion layer 14 positioned on a backlight surface of the silicon substrate 11, wherein the second-type diffusion layer is a back second-type diffusion layer 15 positioned on the backlight surface of the silicon substrate 11, and the back first-type diffusion layer 14 is not in contact with the edge of the back second-type diffusion layer 15 and has a certain safety distance. Edge etching: removing the P-N junctions on the side surface of the silicon substrate 11 except the first diffusion layer on the side surface, and removing the phosphorosilicate glass;

specifically, the above steps a2 and a3 can also be extended to: simultaneously diffusing a first diffusion layer on the two sides of the silicon wafer 1, then manufacturing a protective layer on the first area and the long side surface of one side adjacent to the first area, etching the diffusion layers on the backlight surface and the area of the side surface which is not protected by the protective layer, then manufacturing a second diffusion layer on the second area, and then removing the protective layer and the phosphorosilicate glass;

a3, PECVD coating: respectively evaporating an antireflection layer 101 and a passivation layer 102 on the light receiving surface and the backlight surface of the silicon wafer 1, wherein the materials include but are not limited to TiO₂、Al₂O₃、SiN_xO_y、SiN_xC_y；

a4, screen printing the first electrode 4 and the second electrode 5: the back gate line layer 6 and the second electrode 5 are screen-printed on the passivation layer 102 attached to the back second type diffusion layer 15, the first electrode 4 is screen-printed on the passivation layer 102 attached to the back first type diffusion layer 14, and dried. The first electrode 4 is located in the area where the first-type diffusion layer 14 on the back is located, the back grid line layer 6 and the second electrode 5 are located in the area where the second-type diffusion layer 15 on the back is located, one end of the back grid line layer 6 is connected with the second electrode 5, the other end of the back grid line layer is not connected with the first electrode 4, and a certain safety distance exists;

a5, screen printed front side grid layer 2: screen printing a front grid line layer 2 on the antireflection layer 101 along the width direction, enabling a front sub-grid line 21 to be perpendicular to the first electrode 4 and the second electrode 5, and drying;

a6, forming a side electrode 3 on the side first diffusion layer 13, and drying. Here, it should be noted that the execution order of the steps a4, a5, a6 can be flexibly changed according to actual needs. In addition, the "back surface" and the "back surface" referred to herein are both the back surface side and the "front surface" is the light receiving surface.

Next, a cell sheet matrix 1000 according to an embodiment of the third aspect of the invention is described.

The cell matrix 1000 is formed by connecting a plurality of, i.e. at least two, cells 100 according to the above-described first aspect embodiment in series and/or in parallel. For example, the cell array 1000 may be a first cell array 100A, a second cell array 100B, or a third cell array 100C, where the first cell array 100A is formed by serially connecting a plurality of cells 100 arranged in a single-row multi-row array, the second cell array 100B is formed by parallelly connecting a plurality of first cell arrays 100A, and the third cell array 100C is formed by serially connecting a plurality of second cell arrays 100B.

Therefore, the cell array 1000 according to the embodiment of the invention has the advantages of good power, high energy efficiency, simple structure, simple and convenient processing and low cost. Specifically, the battery piece matrix 1000 of the embodiment of the invention has high power, does not need to add a diode for bypass protection, and has low cost, and in addition, the positive and negative junction boxes can be distributed on two sides of the battery piece matrix 1000, so that the use amount of connecting cables between adjacent components is reduced, and the cost of a power station is reduced.

Next, a solar cell according to an embodiment of the fourth aspect of the invention is described.

The solar cell comprises the cell matrix 1000 of the embodiment of the third aspect described above. For example, the solar cell may include, in order from the light receiving side to the backlight side: a first panel, a first adhesive layer, a cell matrix 1000, a second adhesive layer, and a second panel. The first panel is located on the light receiving side of the cell 100 and may be a glass panel made of a glass material to avoid light blocking, the second panel is located on the backlight side of the cell 100 and may be a conventional back plate, or the second panel may also be a glass panel made of a glass material, and at this time, the solar cell may be a dual-glass assembly. The first adhesive layer is disposed between the first panel and the battery sheet 100 and is used for adhering the first panel to the battery sheet 100, and at this time, the first adhesive layer may be made of an EVA (Ethylene Vinyl Acetate, which is an abbreviation for EVA) material or a transparent silicone rubber or the like material to ensure a good light transmission effect. The second adhesive layer is disposed between the second panel and the battery sheet 100 and is used for adhering the second panel to the battery sheet 100, and in this case, the second adhesive layer may be made of an EVA (Ethylene Vinyl Acetate, abbreviated as EVA) material or a transparent silicone rubber or the like to ensure a good light transmission effect. Therefore, the solar cell has better power, better energy efficiency, simpler and more convenient processing and lower cost.

In the following, solar cells according to two specific embodiments of the present invention are briefly described.

The first embodiment,

The solar cell includes: the battery cell array comprises a first panel, a first insulating layer, a battery cell matrix 1000, a second insulating layer and a second panel which are arranged in sequence from a light receiving side to a backlight side, wherein the battery cell matrix 1000 is the first battery cell array 100A, that is, a plurality of battery cells 100 are sequentially arranged and connected in series according to the same arrangement mode (for example, the arrangement mode that the light receiving surfaces face backwards and the side electrodes 3 face downwards).

At this time, since the plurality of battery pieces 100 in a single row are arranged in the same manner, the second electrode 5 of each battery piece 100 is adjacent to the first electrode 4 of the previous battery piece 100, in other words, the first electrode 4 of each battery piece 100 is adjacent to the second electrode 5 of the next battery piece 100, and therefore, the second electrodes 5 and the first electrodes 4 of the two adjacent battery pieces 100 can be electrically connected together along the length direction of the silicon wafer 1 by using a conductive tape 1001 (e.g., a solder tape) for the purpose of series connection.

Of course, the present invention is not limited thereto, and a conductive tape 1001 (e.g., a solder tape) may be further used to electrically connect the second electrodes 5 and the first electrodes 4 of two adjacent battery pieces 100 together in the width direction of the silicon wafer 1. Of course, without being limited thereto, for example, the second panel may be used to connect the second electrodes 5 and the first electrodes 4 of two adjacent battery pieces 100 in series, and in this embodiment, the second insulating layer may have a through hole, and the second panel may include an electrical conductor penetrating through the through hole to conduct the second electrodes 5 and the first electrodes 4 in series, so that the electrical conductor on the second panel may connect the two adjacent battery pieces 100 in series. The variants are not described in detail here.

Thus, when packaging the battery, the following steps can be adopted: first, a plurality of battery pieces 100 are arranged in a single-row and multi-row array, and then two adjacent battery pieces 100 are connected in series by using a conductive tape 1001 (e.g., a solder tape) to obtain a battery piece matrix 1000, and a bus bar 1002 is led out. Next, in order from bottom to top, a first panel (e.g., glass), a first insulating layer (e.g., EVA), a cell sheet matrix 1000, a second insulating layer (e.g., EVA), and a second panel (e.g., a cell back sheet) are sequentially laid, and are put into a laminator for lamination, thereby realizing encapsulation of the solar cell, and obtaining the solar cell.

Example II,

The second embodiment is substantially the same as the first embodiment except that: the cell array 1000 is a third cell array 100C. For example, the first cell array 100A may be combined into the third cell array 100C by "first three and then two strings". Thus, in packaging the back contact cell, the following steps may be employed: firstly, a plurality of battery pieces 100 are arranged in a single-row multi-row array, then two adjacent battery pieces 100 are connected in series by using a conductive belt 1001 (for example, a solder strip) to obtain a first battery piece array 100A, then six first battery piece arrays 100A are connected in parallel in a tri-parallel mode by using a bus bar 1002 to form two second battery piece arrays 100B, then two second battery piece arrays 100B are connected in series to form a third battery piece array 100C, so that a battery piece matrix 1000 is obtained, and the positive and negative electrodes are respectively led out from the two ends of the battery piece matrix 1000.

Then, according to the sequence from bottom to top, a first panel (for example, glass), a first insulating layer (for example, EVA), the cell sheet matrix 1000, a second insulating layer (for example, EVA), and a second panel (for example, a cell back sheet or glass) are sequentially laid, and a laminating machine is put into the layers for lamination, and a junction box and a frame are installed, so that the packaging and manufacturing of the solar cell are realized, and the solar cell is obtained. Here, it should be noted that the position where the junction box is disposed may be set according to actual requirements to better meet the actual requirements, for example, the junction box may be designed on two edges of the cell matrix 1000, and may also be disposed on the back of two adjacent edges of the cell matrix 1000, and the like.

In summary, the battery cell 100 and the battery cell matrix 1000 according to the embodiment of the invention have the following advantages And (4) potential.

First, because the first electrode 4 and the second electrode 5 are both located at the backlight side of the silicon substrate 11, the problem of shading of the first electrode 4 to the light receiving surface of the silicon substrate 11 can be effectively solved, so as to improve the power of the battery piece 100, reduce the amount of silver paste and reduce the production cost, and meanwhile, because the charge collected by the front grid line layer 2 is transferred to the first electrode 4 at the backlight side by adopting the mode of arranging the side electrode 3 on the side surface of the silicon substrate 11, the production process of the battery piece 100 is greatly simplified, the manufacturing difficulty and the production cost of the battery piece 100 are reduced, so that the battery piece 100 can be produced in large scale.

However, in the prior art, back contact cells such as EWT (emitter wrap around back contact cell), MWT (metal wrap around back contact cell), IBC (all back contact cell) and the like, although the light receiving surface may have no grid lines at all or no main grid lines to reduce front shading, the manufacturing process of the back contact cells such as EWT, MWT, IBC and the like is quite complicated, for example, the MWT cell and the EWT cell need to be laser-drilled on a silicon wafer, and an electrode or an emitter region is manufactured on the back of the cell through a hole, which is difficult and costly, a large amount of solder is consumed to manufacture a module, and the IBC cell has extremely high requirements on the manufacturing process and can be produced only in a small scale.

Second, since the second electrode 5 and the first electrode 4 are both located on the backlight side of the cell 100 and on both sides of the silicon substrate 11 in the width direction, therefore, two adjacent battery plates 100 can be directly connected in series without being overlapped, sequentially arranged and arranged, so that the welding damage rate is reduced, even the usage amount of the solder is reduced by about 2/3 compared with the prior art, the heat loss of the conductive belt 1001 (such as a welding belt) is greatly reduced, the power of the battery plate matrix 1000 is effectively improved, and, since the second electrode 5 and the first electrode 4 of two adjacent battery sheets 100 may be connected at the backlight side of the battery sheet 100, thereby reducing the gap between two adjacent battery pieces 100, and the bus bar 1002 can be directly led out from the battery pieces 100, thereby reducing the overall area of the cell matrix 1000, increasing the effective area of the cell matrix 1000, and further increasing the power of the cell matrix 1000.

However, in the prior art, there is a connection process of overlapping and connecting the back electrodes of the battery pieces and the front electrodes of the adjacent battery pieces in series by using solder paste in a tile-type arrangement manner, however, although this manner can save a large amount of welding materials and reduce heat loss, the method of manufacturing the module in the tile-type arrangement manner is easy to cause the breaking damage of the battery pieces in the welding process and the subsequent lamination process, and the battery pieces at the lamination position cannot participate in power generation, which causes waste and affects the module power.

Thirdly, because the cell matrix 1000 can adopt a structure combining series connection and parallel connection, the production cost can be effectively reduced, so that the positive and negative junction boxes can be distributed on two sides of the cell matrix 1000, the cable consumption is reduced, and the power station cost is reduced.

However, in the prior art, all the cells in the cell matrix need to be connected in series in sequence, so that a diode needs to be additionally added for bypass protection, and the prior art is not high in reliability, complex in structure, high in production cost, and not beneficial to mass production.

Fourth, since the back surface of the cell sheet 100 can receive light and generate electricity, the power of the cell sheet 100 is increased, and the manufactured solar cell, for example, a dual glass module, has excellent aesthetic properties.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", and the like indicate orientations or positional relationships based on those shown in the drawings, and are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be directly connected or indirectly connected through intervening media, and can be internal to or interactive with respect to two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A battery cell (100), comprising:

the silicon chip (1) comprises a silicon substrate (11), a front first-type diffusion layer (12), a back first-type diffusion layer (14) and a back second-type diffusion layer (15), wherein the back surface of the silicon substrate (11) comprises a first region and a second region which are not in contact with each other, the front first-type diffusion layer (12) is arranged on the light receiving surface of the silicon substrate (11), the back first-type diffusion layer (14) is only arranged on and distributed in the first region, the back second-type diffusion layer (15) is only arranged on and distributed in the second region, the back first-type diffusion layer (14) and the front first-type diffusion layer (12) are of the same type, and the back second-type diffusion layer (15) and the front first-type diffusion layer (12) are of different types;

the front grid line layer (2), the front grid line layer (2) is arranged on the front first-type diffusion layer (12);

the side electrode (3) is arranged on the side surface of the silicon wafer (1) and is electrically connected with the front grid line layer (2);

a first electrode (4), wherein the first electrode (4) is arranged on the back first diffusion layer (14) and is electrically connected with the side electrode (3);

a back grid line layer (6) and a second electrode (5), wherein the back grid line layer (6) and the second electrode (5) are electrically connected and are arranged on the back second-type diffusion layer (15), the silicon chip (1) is a rectangular sheet body, the first electrode (4) and the second electrode (5) are respectively attached to two long edges of the silicon chip (1) and extend along the length direction of the silicon chip (1), the back grid line layer (6) comprises a plurality of back sub-grid lines (61) extending along the direction vertical to the length direction of the second electrode (5), the side electrode (3) is arranged on the side surface of the long side of the silicon chip (1) adjacent to the first electrode (4), the front side grid line layer (2) comprises a plurality of front side sub-grid lines (21) extending along the direction vertical to the length direction of the side electrodes (3), the span of the silicon chip (1) in the direction vertical to the side electrode (3) is 20-60 mm.

2. The battery piece (100) according to claim 1, wherein the outer edge of the first electrode (4) falls on the contour line of the first region as projected in the thickness direction of the silicon piece (1).

3. The battery cell (100) of claim 1, wherein the back grid layer (6) and the second electrode (5) are not stacked and are in contact connection with each other.

4. The battery cell (100) according to claim 3, wherein the outer edges of the back grid line layer (6) and the second electrode (5) as a whole, projected in the thickness direction of the silicon wafer (1), all fall on the contour line of the second region.

5. The cell wafer (100) according to claim 1, wherein the silicon wafer (1) further comprises a lateral first type diffusion layer (13) provided on a lateral surface of the silicon substrate (11), the lateral electrode (3) being provided on the lateral first type diffusion layer (13), wherein the lateral first type diffusion layer (13) is of the same type as the front first type diffusion layer (12).

6. The battery cell (100) of claim 1, wherein at least one of the first region and the second region is a non-discrete region.

7. The cell (100) according to claim 1, wherein the silicon substrate (11) is P-type, the front first type diffusion layer (12) is a phosphorus diffusion layer, and the back second type diffusion layer (15) is a boron diffusion layer.

8. The cell wafer (100) according to claim 1, wherein the silicon substrate (11) is N-type, the front side first type diffusion layer (12) is a boron diffusion layer, and the back side second type diffusion layer (15) is a phosphorus diffusion layer.

9. The battery piece (100) of claim 1, comprising:

and the antireflection layer (101) is arranged between the front-surface first-type diffusion layer (12) and the front-surface grid line layer (2).

10. The battery cell (100) of claim 9, wherein the antireflective layer (101) is further provided between the side electrode (3) and the silicon substrate (11).

11. The battery piece (100) of claim 1, comprising:

a passivation layer (102), the passivation layer (102) being arranged between the back second type diffusion layer (15) and the back gate line layer (6).

12. The battery piece (100) according to claim 11, wherein the passivation layer (102) is respectively provided on the back surface first type diffusion layer (14) and the back surface second type diffusion layer (15) and filled between the back surface first type diffusion layer (14) and the back surface second type diffusion layer (15).

13. A method for preparing a battery plate (100) according to any one of claims 1 to 12, the silicon substrate comprising a side spacer layer provided on a side surface of the silicon substrate (11), the side electrode being provided on the side spacer layer, the method comprising the steps of:

a: -obtaining said silicon substrate (11);

b: preparing the front first-type diffusion layer (12), the side surface interlayer, the back first-type diffusion layer and the back second-type diffusion layer (15) on the silicon substrate (11) to obtain the silicon wafer (1);

c: preparing the first electrode (4), the back grid line layer (6), the second electrode (5), the front grid line layer (2) and the side electrode (3) on the silicon chip (1).

14. The method for preparing a battery piece (100) according to claim 13, wherein the step a is specifically:

and dividing the square conventional silicon substrate body at least once according to the length-invariant rule to obtain a plurality of silicon substrates (11).

15. The method for preparing a battery piece (100) according to claim 13, wherein the side surface spacers are side first type diffusion layers (13) distributed on the side surfaces, and the step B specifically comprises:

preparing a first type diffusion layer on the light receiving surface, the side surface and the first region of the silicon substrate (11) to obtain the front first type diffusion layer (12), the side first type diffusion layer (13) and the back first type diffusion layer (14), and preparing a back second type diffusion layer on the second region to obtain the back second type diffusion layer (15).

16. A cell matrix (1000) characterized by a plurality of cells (100) according to any of claims 1-12 connected in series and/or in parallel.

17. A solar cell, characterized in that it comprises a matrix of cells (1000) according to claim 16.