WO2018001186A1

WO2018001186A1 - Battery cell, battery cell matrix, and solar cell

Info

Publication number: WO2018001186A1
Application number: PCT/CN2017/089818
Authority: WO
Inventors: 孙翔; 姚云江; 姜占锋
Original assignee: 比亚迪股份有限公司
Priority date: 2016-06-30
Filing date: 2017-06-23
Publication date: 2018-01-04
Also published as: CN205863176U

Abstract

A battery cell (100), a battery cell matrix, and a solar cell, the battery cell (100) comprising: a silicon wafer (1), a front gate line layer (2), a side electrode (3), a rear first gate line layer (7), and a first electrode (4) and a second electrode (5), the silicone wafer (1) comprising a silicon substrate (11), a front first type diffusion layer (12), and a rear first type diffusion layer (14), a backlight surface of the silicon substrate (11) comprising a non-discrete first and second region, the area of the first region being 30% to 70% of the area of the backlight surface of the silicon substrate (11), the front gate line layer (2) being arranged on the front first type diffusion layer (12), the side electrode (3) being arranged on the side surface of the silicon wafer (1) and being electrically connected to the front gate line layer (2), the rear first gate line layer (7) and the first electrode (4) being electrically connected and both being arranged on the rear first type diffusion layer (14), the first electrode (4) being electrically connected to the side electrode (3), and the second electrode (5) being arranged on the second region and not being in contact with the rear first gate line layer (7).

Description

Cell, cell matrix and solar cell

Technical field

The present disclosure relates to the field of solar cell technologies, and in particular, to a battery chip, a battery chip matrix, and a solar cell.

Background technique

In the crystalline silicon solar cell sheet of the related art, the backlight surface and the light receiving surface respectively have 2-3 silver main gate lines as the positive and negative electrodes of the battery sheet, and these silver main gate lines not only consume a large amount of silver paste, but also block incident light. This results in a decrease in the efficiency of the battery. In addition, since the positive and negative electrodes are respectively distributed on the backlight surface and the light receiving surface of the battery sheet, when the battery sheets are connected in series, it is necessary to solder the negative electrode of the light receiving surface of the battery sheet to the positive electrode of the backlight surface of the adjacent battery sheet when the battery sheets are connected in series. As a result, the welding process is cumbersome and the welding material is used more. Moreover, the battery sheets and the solder ribbon are easily broken during soldering and subsequent lamination processes.

In addition, the matrix of the battery in the related art is usually composed of 72 pieces or 60 pieces of cells in series, which constitutes three circuits composed of six strings of battery strings. At this time, at least three diodes are generally required to make each circuit. By providing a diode for bypass protection, since the diode is usually disposed in the junction box of the battery, the cost of the integrated junction box is increased, resulting in an increase in the structural complexity of the battery. Moreover, when the series components in which a plurality of battery cells are connected in series are connected in series again, the amount of the connecting cable is large, and the material is wasted a lot, resulting in an increase in the cost of the power station.

Summary of the invention

The present disclosure is intended to address at least one of the technical problems existing in the prior art. To this end, the present disclosure is directed to a battery sheet that is excellent in leakage resistance and high in power.

The present disclosure also proposes a battery chip matrix having the above battery sheets.

The present disclosure also proposes a solar cell having the above-described battery chip matrix.

A battery sheet according to a first aspect of the present disclosure, comprising: a silicon wafer including a silicon substrate, a front first diffusion layer, and a back first diffusion layer, wherein the backlight surface of the silicon substrate includes a discrete first region and a non-discrete second region, wherein the first region has an area of 30% to 70% of an area of the backlight surface of the silicon substrate, and the back first diffusion layer Provided only on and over the first region, wherein the front first diffusion layer and the back first diffusion layer are of the same type; the front gate layer, the front gate layer is The front surface of the first type of diffusion layer; the side electrode, the side electrode is disposed on a side surface of the silicon wafer and electrically connected to the front gate line layer; the first gate line layer and the first electrode on the back surface The first gate line layer and the first electrode are electrically connected and are disposed on the back side of the first type On the diffusion layer, the first motor is electrically connected to the side electrode; and the second electrode is disposed on the second region and is not in contact with the back first gate line layer.

The battery sheet according to the present disclosure has good leakage resistance and high power.

In some embodiments, the battery chip further includes: a back second gate line layer, the back second gate line layer is disposed on the second region, wherein the back second gate line layer and the The second electrode is electrically connected and not in contact with the first electrode.

In some embodiments, the silicon wafer comprises a backside second type of diffusion layer, the backside second type of diffusion layer being of a different type than the backside first type of diffusion layer and disposed only and overlying the second In the region, the second electrode is disposed on the back diffusion layer of the second type.

In some embodiments, the silicon substrate is P-type, the front first diffusion layer is a phosphorus diffusion layer, and the back second diffusion layer is a boron diffusion layer.

In some embodiments, the silicon substrate is N-type, the front first diffusion layer is a boron diffusion layer, and the back second diffusion layer is a phosphorus diffusion layer.

In some embodiments, the back first gate line layer and the first electrode are non-overlapping and in contact with each other.

In some embodiments, the back second gate line layer and the second electrode are non-overlapping and in contact with each other.

In some embodiments, the first region and the second region are not in contact with each other.

In some embodiments, the first region and the second region are in a non-contact finger cross-shaped distribution, wherein the first region includes a first communication region and a plurality of first dispersion regions, and the plurality of The first dispersion regions are spaced apart in the longitudinal direction of the first communication region and are both in communication with the first communication region, the second region includes a second communication region and a plurality of second dispersion regions, and the plurality of The second dispersion regions are spaced apart in the longitudinal direction of the second communication region and are both in communication with the second communication region, wherein the first communication region is disposed opposite to the second communication region, and the plurality of a first dispersion region and a plurality of the second dispersion regions alternate between the first communication region and the second communication region, and the first dispersion region and the second dispersion region and the The second communication regions are not in contact, and the second dispersion region is not in contact with the first dispersion region and the first communication region.

In some embodiments, the back first gate line layer includes a plurality of back first sub-gate lines extending perpendicular to a length of the first electrode, the back second gate line layer including being perpendicular to the a plurality of back second sub-gate lines extending in the longitudinal direction of the second electrode.

In some embodiments, the silicon wafer further includes a side first diffusion layer, the side first diffusion layer is disposed on a side surface of the silicon substrate, and the side electrode is disposed on the side first On the diffusion layer.

In some embodiments, the silicon wafer has a span of 20 mm to 60 mm in a direction perpendicular to the side electrode.

In some embodiments, the silicon wafer is a rectangular sheet, and the first electrode and the second electrode are respectively disposed adjacent to two long sides of the silicon wafer and extend along a length of the silicon wafer. The side electrode is disposed adjacent to the silicon wafer One side of the first electrode is on the long side surface.

In some embodiments, the battery sheet further includes: an anti-reflection layer disposed between the front first diffusion layer and the front gate layer.

In some embodiments, the anti-reflective layer is further disposed between the side electrode and the silicon substrate.

In some embodiments, the battery sheet further includes a passivation layer disposed between the back first diffusion layer and the back first gate line.

In some embodiments, the passivation layers are respectively disposed on the back first diffusion layer and the back second diffusion layer, and are filled on the back first diffusion layer and the back second Between class diffusion layers.

The battery chip matrix according to the second aspect of the present disclosure is formed by series and/or parallel connection of the battery sheets according to the first aspect of the present disclosure.

A solar cell according to a third aspect of the present disclosure includes a cell sheet matrix according to the second aspect of the present disclosure.

The additional aspects and advantages of the present disclosure will be set forth in part in the description which follows.

DRAWINGS

1 is a schematic view of a light receiving side of a battery sheet according to an embodiment of the present disclosure;

Figure 2 is a schematic view of the backlight side of the battery chip shown in Figure 1;

Figure 3 is a schematic illustration of one side of the battery sheet shown in Figure 2;

Figure 4 is a schematic view of the other side of the battery sheet shown in Figure 2;

Figure 5 is a process diagram of the preparation of the backlight side of the battery chip shown in Figure 4;

Figure 6 is a schematic view showing the two battery sheets shown in Figure 1 in series with a conductive strip;

Figure 7 is a schematic view of the two battery sheets shown in Figure 6 with the conductive strip removed;

8 is a schematic diagram of a battery chip matrix in accordance with an embodiment of the present disclosure;

Figure 9 is a circuit diagram of the battery chip matrix shown in Figure 8.

Reference mark:

Cell matrix 1000; solder ribbon 1001; bus bar 1002;

First cell array 100A; second cell array 100B; third cell array 100C;

Battery chip 100;

Silicon wafer 1; silicon substrate 11; front side first type diffusion layer 12; side first type diffusion layer 13; back side first type diffusion layer 14; back side second type diffusion layer 15;

Anti-reflection layer 101; passivation layer 102;

Front gate line layer 2; front side gate line 21; side electrode 3; first electrode 4; second electrode 5;

a second gate line layer 6 on the back surface; a second sub-gate line 61 on the back surface;

The first gate line layer 7 on the back side and the first sub-gate line 71 on the back side.

detailed description

The embodiments of the present disclosure are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are illustrative, and are not intended to be construed as limiting.

Many different embodiments or examples are provided below to implement the different structures of the present disclosure. In order to simplify the disclosure, the components and settings of the specific examples are described below. Of course, they are merely examples and are not intended to limit the disclosure. Furthermore, the present disclosure may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of simplicity and clarity, and is not in the nature of the description of the various embodiments and/or arrangements discussed. Moreover, the present disclosure provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.

Hereinafter, a battery sheet 100 according to an embodiment of the first aspect of the present disclosure will be described with reference to the accompanying drawings. The battery chip 100 is a back contact solar cell that converts solar energy into electrical energy.

The battery sheet 100 according to an embodiment of the present disclosure includes: a silicon wafer 1, a front gate line layer 2, a side electrode 3, a back surface first gate line layer 7, a first electrode 4, a back surface second gate line layer 6, and a second electrode 5. The silicon wafer 1 includes a silicon substrate 11, a front first diffusion layer 12, and a back first diffusion layer 14.

The silicon substrate 11 has a sheet shape, and the two surfaces in the thickness direction of the silicon substrate 11 are respectively a light receiving surface and a backlight surface, and the light receiving surface is connected to the backlight surface through the side surface. The front first diffusion layer 12 is disposed on the light receiving surface of the silicon substrate 11. For example, in an alternative embodiment of the present disclosure, the front first diffusion layer 12 is covered on the light receiving surface of the silicon substrate 11. Therefore, the processing difficulty of the front type first diffusion layer 12 is reduced, the processing efficiency is improved, the processing cost is reduced, and the power of the battery sheet 100 can be effectively improved.

The backlight surface of the silicon substrate 11 includes a first region and a second region, and the first region and the second region have no intersection, and the first region and the second region may contact each other or not contact each other, that is, the first region The contour line may or may not be in contact with the contour of the second area.

The first area is a non-discrete type area, that is, when the first area is arbitrarily divided into a plurality of sub-areas, the plurality of sub-areas may be connected into one continuous first area. The first type of diffusion layer 14 on the back surface is disposed only on the first region, that is, the other surface than the first region on the backlight surface of the silicon substrate 11 does not have the back diffusion layer 14 on the back surface, and further, the back surface A type of diffusion layer 14 is overlaid on the first region such that, since the first region is a non-discrete continuous region, the back first diffusion layer 14 can be disposed non-discretely, i.e., continuously, on the silicon substrate 11.

Thereby, since the back type first diffusion layer 14 is continuously, that is, non-discretely disposed on the silicon substrate 11, it is not separated Dispersions, that is, discontinuously, for example, discrete forms such as scatters and zebra strips are scattered on the silicon substrate 11, thereby greatly reducing the processing difficulty of the first type of diffusion layer 14 on the back surface, improving processing efficiency, and reducing The processing cost and the power of the battery sheet 100 can be effectively improved.

The second area is a non-discrete type, that is, when the second area is arbitrarily divided into a plurality of sub-areas, the plurality of sub-areas may be connected into one continuous second area. The silicon wafer 1 may further include a back surface second type diffusion layer 15 which may be disposed only on the second region, that is, on the remaining surface of the backlight surface of the silicon substrate 11 except for the second region There is no back diffusion layer 15 of the second type. Further, the back type second diffusion layer 15 may be covered on the second region, such that since the second region is a non-discrete continuous region, the back second diffusion layer 15 may be non-discrete, ie, continuously disposed in the silicon. On the substrate 11.

Thereby, since the back surface type second diffusion layer 15 is continuously, that is, non-discretely disposed on the silicon substrate 11, it is not discretely, that is, discontinuously, for example, scattered in the form of scatter, zebra strips, etc. On the silicon substrate 11, the processing difficulty of the second type diffusion layer 15 on the back surface is greatly reduced, the processing efficiency is improved, the processing cost is reduced, and the power of the battery sheet 100 can be effectively improved.

The front gate line layer 2 is disposed on the front first diffusion layer 12, that is, the front gate line layer 2 may be directly or indirectly disposed on the front first diffusion layer 12, and the front gate line layer 2 is disposed at The light-receiving surface of the silicon wafer 1 corresponds to the front-surface first-type diffusion layer 12, that is, in the thickness direction of the silicon wafer 1, and the front gate line layer 2 does not exceed the outline of the front-surface first-type diffusion layer 12.

For example, in some embodiments of the present disclosure, the silicon wafer 1 may further include an anti-reflection layer 101, and the anti-reflection layer 101 may be disposed on the front first diffusion layer 12. Thus, when the silicon wafer 1 includes the anti-reflection layer 101, the front gate line layer 2 can be directly provided on the anti-reflection layer 101. When the silicon wafer 1 does not include the anti-reflection layer 101, the front gate line layer 2 may be directly disposed on the front first diffusion layer 12.

In addition, the anti-reflection layer 101 may also be disposed between the side electrode 3 and the side first diffusion layer 13 described herein. At this time, the entire light-receiving surface of the silicon wafer 1 and the outer surface of one side surface may have a subtraction. The layer 101 is reversed to facilitate processing and manufacturing. Furthermore, it should be noted that the concept of the anti-reflection layer described herein should be well known to those skilled in the art, which primarily serves to reduce reflection and enhance charge collection. For example, the material of the anti-reflection layer 101 may include, but is not limited to, TiO2, Al2O3, SiNxOy, SiNxCy.

The back first gate line layer 7 and the first electrode 4 are disposed on the back first type diffusion layer 14, that is, the back first gate line layer 7 and the first electrode 4 may be directly or indirectly disposed on the back side of the first type of diffusion. On the layer 14, at this time, the back first gate line layer 7 and the first electrode 4 are disposed on the backlight surface of the silicon wafer 1 and correspond to the first region, that is, projected in the thickness direction of the silicon wafer 1, and the back surface The first gate line layer 7 and the first electrode 4 do not extend beyond the first region.

For example, in some embodiments of the present disclosure, the silicon wafer 1 may further include a passivation layer 102, and the passivation layer 102 may be disposed on the back first diffusion layer 14. Thus, when the silicon wafer 1 includes the passivation layer 102, the back first gate line layer 7 and the first electricity The pole 4 can be directly disposed on the passivation layer 102. When the silicon wafer 1 does not include the passivation layer 102, the back first gate line layer 7 and the first electrode 4 may be directly disposed on the back first diffusion layer 14.

In addition, the passivation layer 102 may be disposed on the back surface type second diffusion layer 15 and between the back surface first type diffusion layer 14 and the back surface second type diffusion layer 15. At this time, the entire backlight surface of the silicon wafer 1 A passivation layer 102 can be provided on the outer surface to facilitate processing and fabrication. Furthermore, it should be noted that the concept of the passivation layer described herein should be well known to those skilled in the art and is primarily intended to reduce reflection and enhance charge collection. For example, the material of the passivation layer 102 may include, but is not limited to, TiO2, Al2O3, SiNxOy, SiNxCy.

In addition, it should be noted that, in some embodiments of the present disclosure, the back first gate line layer 7 and the first electrode 4 may be non-overlapping and in contact with each other. In this case, the back first gate line layer 7 and the first The electrodes 4 are completely disposed on the backlight surface of the silicon wafer 1 and the edges are directly in contact with the electrical connection, so that the space can be fully utilized to increase the power of the battery chip 100. In still other embodiments of the present disclosure, the back first gate line layer 7 and the first electrode 4 may also overlap each other. At this time, the back first gate line layer 7 and the first electrode 4 are stacked on both sides. The junction surface is provided on the backlight surface of the silicon wafer 1.

The second gate line layer 6 and the second electrode 5 on the back surface may be disposed on the back diffusion layer 15 of the second type, that is, the second gate line layer 6 and the second electrode 5 on the back surface may be directly or indirectly disposed on the back side of the second type. On the diffusion layer 15, at this time, the back second gate line layer 6 and the second electrode 5 are disposed on the backlight surface of the silicon wafer 1 and correspond to the second region, that is, projected in the thickness direction of the silicon wafer 1, The second gate line layer 6 and the second electrode 5 on the back side do not extend beyond the second region. Wherein, the second gate line layer 6 on the back surface is neither in contact with the back first gate line layer 7 nor in contact with the first electrode 4, and the second electrode 5 is neither in contact with the back first gate line layer 7 nor The first electrode 4 is in contact.

Of course, the disclosure is not limited thereto. In other embodiments of the present disclosure, the battery sheet 100 may not include the second gate line layer 6 on the back surface, and may further include an electrical back layer disposed on the back diffusion layer 15 of the second type. The backing layer can be used to collect charge and be electrically connected to the second electrode 5.

For example, in some embodiments of the present disclosure, the silicon wafer 1 may further include a passivation layer 102, and the passivation layer 102 may be disposed on the back second diffusion layer 15. Thus, when the silicon wafer 1 includes the passivation layer 102, the back second gate line layer 6 and the second electrode 5 may be directly disposed on the passivation layer 102. When the silicon wafer 1 does not include the passivation layer 102, the back second gate line layer 6 and the second electrode 5 may be directly disposed on the back surface second type diffusion layer 15.

In addition, it should be noted that when the silicon wafer 1 does not include the back type second diffusion layer 15, the back second gate line layer 6 and the second electrode 5 may be directly or indirectly disposed on the backlight surface of the silicon substrate 11, for example The passivation layer is indirectly provided on the backlight surface of the silicon substrate 11. Hereinafter, only the silicon wafer 1 including the back surface second diffusion layer 15 will be described as an example.

In some embodiments of the present disclosure, the back second gate line layer 6 and the second electrode 5 may be non-overlapping and in contact with each other. At this time, the back second gate line layer 6 and the second electrode 5 are completely disposed on the silicon, respectively. The backlight surface of the sheet 1 and the edge are in direct contact with the electrical connection, so that the space can be fully utilized to increase the power of the battery sheet 100. In still other embodiments of the present disclosure, the back second gate line layer 6 and the second electrode 5 may also overlap each other, in this case, the back second gate line layer 6 and the second electrode 5 The surface of the junction after being superposed on both sides is provided on the backlight surface of the silicon wafer 1.

Here, it should be noted that the "first type of diffusion layer" described herein is a diffusion layer of the same kind, when the conductive medium is provided (for example, directly on or through the anti-reflection layer 101 or passivation described herein). The layer 102 can be indirectly disposed on the first type of diffusion layer to collect the same type of charge. Moreover, the "first type of diffusion layer" and the "second type of diffusion layer" described herein are two different types of diffusion layers, when the conductive medium is provided (eg, directly or through the anti-reflection layer described herein). Different types of charges can also be collected when the 101 or passivation layer 102 is indirectly disposed on the first type of diffusion layer and the second type of diffusion layer. In addition, it should be noted that the concepts of the anti-reflection layer and the passivation layer described herein are well known to those skilled in the art, and both of them mainly serve to reduce reflection and enhance charge collection.

Thus, the front first diffusion layer 12, the back first diffusion layer 14, and the side first diffusion layer 13 described herein in the "first diffusion layer" are the same type of diffusion layer, when conductive When the medium is disposed on the first type of diffusion layer, the first type of charge can be collected. When a conductive medium is provided on a surface of the silicon substrate 11 which does not have the first type of diffusion layer (for example, the second type of diffusion layer and the remaining surface of the silicon substrate 11), a second kind of charge can be collected. Here, it should be noted that the principle that the conductive medium collects charges on the silicon wafer should be well known to those skilled in the art and will not be described in detail herein.

For example, when the silicon substrate 11 is P-type silicon, the first type of diffusion layer may be a phosphorus diffusion layer, and the conductive medium disposed on the phosphorus diffusion layer may collect negative charges, and the second type of diffusion layer may be boron diffusion. The conductive medium disposed on the boron diffusion layer may collect a positive charge, and the conductive medium disposed on the remaining surface of the silicon substrate 11 (ie, the non-phosphorus diffusion layer, the non-boron diffusion layer) may also collect a positive charge. For another example, when the silicon substrate 11 is N-type silicon, the “first diffusion layer” may be a boron diffusion layer, and the “second diffusion layer” may be a phosphorus diffusion layer, which will not be described herein.

Thus, since the front gate line layer 2 and the back first gate line layer 7 are both disposed (eg, directly on or through the anti-reflection layer 101 and the passivation layer 102) on the first type of diffusion layer, the front gate line The layer 2 and the back first gate line layer 7 may collect a first type of charge (eg, a negative charge). The second gate line layer 6 on the back surface is disposed on (for example, directly on or through the passivation layer 102) the second type of diffusion layer or the remaining surface (ie, the non-first diffusion layer, the non-second diffusion layer) Thus, the second gate line layer 6 on the back side can collect a second type of charge (eg, a positive charge).

In one embodiment, the first electrode 4 is electrically connected on the one hand to the front gate line layer 2 via the side electrodes 3, the first electrode 4 on the other hand, and the back first gate line layer 7 on the other hand, so that the front gate line layer 2 and the back side The first type of charge (eg, negative charge) collected by the first gate line layer 7 may be transferred to the first electrode 4 (eg, the negative electrode). The second electrode 5 is electrically connected to the back second gate line layer 6, so that a second kind of charge (for example, a positive charge) collected by the back second gate line layer 6 can be transferred to the second electrode 5 (for example, a positive electrode). Thereby, the first electrode 4 and the second electrode 5 can output electric energy as positive and negative poles of the battery sheet 100.

In this way, since the first electrode 4 can collect the first type of charges through the front gate line layer 2 and the back first gate line layer 7 on the front and back sides of the silicon wafer 1, respectively, the power of the battery sheet 100 can be effectively improved, and Since the back side of the silicon wafer 1 is provided with a back second gate line layer 6 and a back first gate line layer 7 for collecting different kinds of charges, thereby The space utilization rate is effectively improved, and the power of the battery sheet 100 is further improved, so that the battery sheet 100 can be a beautiful and efficient double-sided battery.

It can be understood by those skilled in the art that the first electrode 4 and the second electrode 5 are electrodes of opposite polarities, and need to be insulated, that is, not electrically connected to each other, and do not form an electrical connection with each other. In this case, the first electrode 4, And all components electrically connected to the first electrode 4 and the second electrode 5, and all components electrically connected to the second electrode 5 are not directly conductive, and cannot be indirectly conducted through any external conductive medium, for example, may not contact or The first electrode 4 and the second electrode 5 are prevented from being short-circuited by being separated by an insulating material or the like.

In one embodiment, the side electrodes 3 are provided on the side surface of the silicon wafer 1, that is, the side electrodes 3 are not embedded in the interior of the silicon wafer 1, thereby not only reducing the overall processing of the battery sheet 100. The difficulty, the processing process are simplified, the processing efficiency is improved, the processing cost is reduced, and the front gate line layer 2 and the first electrode 4 can be effectively electrically connected together through the side electrodes 3 to ensure the reliability of the operation of the battery sheet 100.

Further, the side electrode 3 is provided on the side surface of the silicon wafer 1 to mean that the side electrode 3 can be directly or indirectly provided on the side surface of the silicon substrate 11. For example, in some embodiments of the present disclosure, the side electrode 3 may be directly disposed on the side spacer. In this case, in order to avoid short circuit between the first electrode 4 and the second electrode 5, an electrode having an insulating wrap layer may be selected as the side. The electrode 3 can prevent the conductive medium in the side electrode 3 from directly contacting the surface of the silicon substrate 11 which does not have the first type of diffusion layer, and collect the second type of charge and transfer it to the first electrode 4, thereby ensuring the first The insulation of one electrode 4 and the second electrode 5.

For example, in other embodiments of the present disclosure, the silicon wafer 1 may further include a side spacer which may be provided on a side surface of the silicon substrate 11. At this time, the side electrode 3 may be directly provided on the side spacer to be indirectly provided on the side surface of the silicon substrate 11. At this time, the side spacer is configured to insulate the first electrode 4 and the second electrode 5, that is, when the side electrode 3 is directly disposed on the side spacer, the first electrode 4 and the second electrode 5 are not short-circuited. .

For example, the side spacers may be all insulating layers, or all of the first type of diffusion layers (ie, the side first diffusion layer 13), or a portion of the insulating layer, and the other portion of the first type of diffusion layer. When the side electrode 3 is directly disposed on the insulating layer, the side electrode 3 is insulated from the silicon wafer 1, and only the charge collected by the front gate line layer 2 can be transferred to the first electrode 4, so that the first electrode 4 and the second electrode can be ensured. 5 insulation. When the side electrode 3 is directly disposed on the first type of diffusion layer, the side electrode 3 can collect charges (first type of charge) from the first type of diffusion layer and charge with the front gate line layer 2 (first The charge of the kind is transmitted to the first electrode 4 at the same time, so that not only the insulation of the first electrode 4 and the second electrode 5 but also the power of the battery sheet 100 can be improved.

Here, it should be noted that the concepts of the silicon substrate, the diffusion layer, the passivation layer, the anti-reflection layer, and the like, and the principle that the conductive medium collects charges from the silicon wafer are well known to those skilled in the art and will not be described in detail herein. In addition, in an optional embodiment of the present disclosure, the front gate line layer 2, the back first gate line layer 7, and the back second gate line layer 6 may each be composed of a plurality of spaced apart conductive thin gate lines. a conductive dielectric layer, wherein the fine grid lines may be composed of silver material, thereby In order to increase the conduction rate, on the other hand, the shading area can be reduced, thereby increasing the power of the cell 100 in a disguised manner.

In summary, according to the battery sheet 100 of the embodiment of the present disclosure, the front gate line layer 2 and the back surface first gate line layer 7 connected to the first electrode 4 are respectively processed on the light receiving surface and the backlight surface of the silicon wafer 1, and The backlight surface of the silicon wafer 1 processes the back second gate line layer 6 connected to the second electrode 5, so that the battery sheet 100 can be a double-sided battery with higher power.

Further, by providing the side electrode 3 on the side surface of the silicon substrate 11, the first electrode on the light receiving surface of the conventional battery sheet 100 can be transferred from the light receiving side of the silicon wafer 1 to the backlight side to prevent the first electrode 4 from facing the silicon wafer. The light-receiving side of 1 is light-shielded to increase the power of the battery sheet 100, and it can be ensured that the first electrode 4 and the second electrode 5 are both located on the same side of the silicon wafer 1, thereby facilitating electrical connection between the plurality of battery sheets 100, and reducing welding difficulty. The amount of solder used is reduced, and the probability of breakage of the cell 100 during soldering and subsequent lamination processes is reduced.

In addition, by providing the side electrodes 3 on the side surface of the silicon wafer 1, the processing difficulty of the battery sheet 100 is greatly reduced (for example, it is not necessary to process the openings in the silicon wafer 1 and inject a conductive medium into the openings). ), which in turn increases the processing rate and reduces the processing failure rate and processing cost. In addition, when the side electrode 3 is provided on one side surface in the width direction of the silicon substrate 11, the path of transferring charges from the light receiving side to the backlight side of the silicon wafer 1 can be effectively shortened, and the charge transfer rate can be improved, thereby The power of the battery sheet 100 is increased in a disguised manner.

In one embodiment of the present disclosure, the silicon wafer 1 has a span of 20 mm to 60 mm in a direction perpendicular to the side electrode 3. That is, the silicon wafer 1 includes a pair (two) of oppositely disposed side surfaces, one of which is provided with side electrodes 3 having a distance of 20 mm to 60 mm. For example, in the examples shown in FIGS. 2 and 3, when the silicon wafer 1 is a rectangular sheet and the side electrodes 3 are provided on one long side surface of the silicon wafer 1, the width of the silicon wafer 1 is 20 mm to 60 mm. For example, in another example of the present invention (this example is not shown), when the silicon wafer 1 is a rectangular sheet and the side electrodes 3 are provided on one wide side surface of the silicon wafer 1, the length of the silicon wafer 1 It is 20mm to 60mm. Thereby, the path of charge transfer from the light receiving surface of the silicon wafer 1 to the backlight surface can be shortened, thereby increasing the charge transfer rate, thereby increasing the power of the battery chip 100.

For example, in an alternative example of the present disclosure, the silicon substrate 11 is a rectangular sheet. Here, it should be noted that the "rectangular sheet" is understood as a broad sense, that is, not limited to a rectangular sheet in a strict sense, such as a generally rectangular sheet, such as a rectangular sheet having rounded or chamfered corners at four corners. Etc. also falls within the scope of protection of the present disclosure. Thereby, the processing of the battery sheet 100 is facilitated, and the connection between the battery sheet 100 and the battery sheet 100 is facilitated.

Alternatively, the silicon substrate 11 is a rectangular sheet. For example, the silicon substrate 11 may be divided by a square-sized silicon wafer body in a length-invariant manner (only "separating" rather than "taking a cutting process"), that is, by a square-sized silicon wafer body according to the length. The invariable manner can be divided into a plurality of rectangular wafer-like silicon substrates 11, in which case each of the silicon substrates 11 has a length equal to the length of the square-sized silicon wafer body, and the width of the plurality of silicon substrates 11 The sum is equal to the width of the square-sized silicon wafer body.

In an embodiment of the present disclosure, the first area and the second area do not contact each other, that is, the first area The outline is not in contact with the outline of the second area. Thereby, the insulating effect of the first electrode 4 and the second electrode 5 can be improved.

Thereby, when the first region and the second region are not in contact with each other, there is a gap between the first region and the second region, projected along the thickness direction of the silicon wafer 1, and the entire back gate line layer 7 and the first electrode 4 are integrally formed. The outer edges may all fall on the outline of the first region, that is, the back first gate line layer 7 and the first electrode 4 may occupy the first region maximally, so that the power of the battery sheet 100 can be improved. Here, it should be noted that "the outer edge of the two members as a whole" means that the two members except for the outer edges for contacting the connected edges. Additionally, for a planar member, such as the rectangular sheet-like first electrode 4 and second electrode 5 described herein, the "outer edge" refers to its contour, for a linear member (such as described herein) For the fine grid line), the "outer edge" refers to the end points of both ends.

Thereby, when the first region and the second region are not in contact with each other, the outer edge of the entire second back gate line layer 6 and the second electrode 5 are projected in the thickness direction of the silicon wafer 1 and fall on the outline of the second region. on. That is, the back second gate line layer 6 and the second electrode 5 can maximize the occupation of the second region, so that the power of the battery sheet 100 can be improved. Here, it should be noted that "the outer edge of the two members as a whole" means that the two members except for the outer edges for contacting the connected edges. Additionally, for a planar member, such as the rectangular sheet-like first electrode 4 and second electrode 5 described herein, the "outer edge" refers to its contour, for a linear member (such as described herein) For the fine grid line), the "outer edge" refers to the end points of both ends.

For example, in an alternative embodiment of the present disclosure, the first region and the second region are arranged in a cross-shaped spaced apart relationship. Thereby, the insulation effect of the first electrode 4 and the second electrode 5 can be ensured, and the space can be sufficiently utilized to increase the power of the battery sheet 100. Here, it should be noted that the "finger cross shape" refers to a shape in which the fingers of the left and right hands cross each other without overlapping.

Specifically, the first region includes a first communication region and a plurality of first dispersion regions, and the plurality of first dispersion regions are spaced apart in the longitudinal direction of the first communication region and both communicate with the first communication region. The second region includes a second communication region and a plurality of second dispersion regions, and the plurality of second dispersion regions are spaced apart in the longitudinal direction of the second communication region and both communicate with the second communication region.

The number of the plurality of first dispersion regions and the plurality of second dispersion regions is not limited, and the shapes of the first communication regions, the plurality of first dispersion regions, the second communication regions, and the plurality of second dispersion regions are not limited. For example, the plurality of first dispersion regions and the plurality of second dispersion regions may each be formed into a triangle, a semicircle, a rectangle, or the like, and the plurality of first dispersion regions and the plurality of second dispersion regions may be formed into a rectangular shape, a wavy band shape, or the like. Wait.

The first communication region is disposed opposite to the second communication region. For example, the first communication region is parallel or substantially parallel (having a small angle) with the second communication region, and the plurality of first dispersion regions and the plurality of second dispersion regions are disposed at The first connected area and the second connected area alternate one by one. That is, along the first communication region, that is, along the length direction of the second communication region, a first dispersion region, a second dispersion region, a further first dispersion region, and a second dispersion region are sequentially arranged. And so on, the plurality of first dispersed regions and the plurality of second dispersed regions are alternately alternately alternately distributed. The plurality of first dispersion regions are not in contact with the plurality of second dispersion regions and the second communication regions, and the plurality of second dispersion regions are not in contact with the plurality of first dispersion regions and the first communication regions. Thereby, it can be ensured that the first area and the second area are in a non-contact finger cross arrangement.

Further, the first electrode 4 is disposed on the first communication region, and the back first gate line layer 7 is disposed on the plurality of first dispersion regions. In other words, the first electrode 4 is disposed corresponding to the first communication region, and the back first gate line layer 7 is disposed corresponding to the plurality of first dispersion regions. That is, projected in the thickness direction of the silicon wafer 1, the first electrode 4 does not exceed the outline of the first communication region, and the back first gate line layer 7 does not exceed the outline of the plurality of first dispersion regions. Thereby, the layout of the first electrode 4 and the back first gate line layer 7 is reasonable and simple, and it is easy to process on the back type first diffusion layer 14.

Optionally, the back first gate line layer 7 includes a plurality of back first sub-gate lines 71 extending perpendicular to the length direction of the first electrode 4, that is, each of the back first sub-gate lines 71 is first and first The electrode 4 is perpendicular to the longitudinal direction. For example, the back first gate line layer 7 includes a plurality of back surface first sub-gate lines 71 extending in a length direction perpendicular to the first communication region and spaced apart in the longitudinal direction of the first communication region. Thereby, the back first gate line layer 7 can transfer the collected charges to the first electrode 4 in a shorter path, thereby improving the charge transfer efficiency and increasing the power of the cell sheet 100.

Further, the second electrode 5 is disposed on the second communication region, and the second gate line layer 6 on the back surface is disposed on the plurality of second dispersion regions. The second electrode 5 is disposed corresponding to the second communication region, and the second gate line layer 6 on the back surface is disposed corresponding to the plurality of second dispersion regions. That is, projected in the thickness direction of the silicon wafer 1, the second electrode 5 does not extend beyond the outline of the second communication region, and the second gate line layer 6 on the back side does not exceed the outline of the plurality of second dispersion regions. Thereby, the layout of the second electrode 5 and the second gate line layer 6 on the back surface is rational and simple, and it is easy to process on the back diffusion layer 15 of the second type.

Optionally, the back second gate line layer 6 includes a plurality of back second sub-gate lines 61 extending perpendicular to the length direction of the second electrode 5, that is, each of the back second sub-gate lines 61 and the second The longitudinal direction of the electrode 5 is perpendicular. For example, the back second gate line layer 6 includes a plurality of back surface second sub-gate lines 61 extending in a length direction perpendicular to the second communication region and spaced apart in the length direction of the second communication region. Thereby, the back second gate line layer 6 can transfer the collected charges to the second electrode 5 in a shorter path, thereby improving the charge transfer efficiency and increasing the power of the cell sheet 100.

Hereinafter, the battery sheet 100 of one embodiment of the present disclosure will be described by taking the silicon wafer 1 as a rectangular sheet as an example.

Specifically, the first electrode 4 and the second electrode 5 are respectively disposed adjacent to the two long sides of the silicon wafer 1 and extend along the length direction of the silicon wafer 1, and the side electrodes 3 are disposed adjacent to the first electrode 4 of the silicon wafer 1. On one side long side surface (as shown in FIGS. 2 and 3), that is, the side electrode 3 is provided on one side side surface adjacent to the first electrode 4 in the width direction of the silicon wafer 1. That is, the first electrode 4 and the second electrode 5 are spaced apart in the width direction of the silicon wafer 1, and are respectively disposed adjacent to the two long sides of the silicon wafer 1, and the side electrodes 3 are disposed on one long side of the silicon wafer 1. The side surface is provided on one side side surface in the width direction of the silicon wafer 1, and is located on the side close to the first electrode 4. Thereby, the charge transmission path is shorter, the power of the battery sheet 100 is higher, and the processing of the battery sheet 100 is more convenient, and the connection between the battery sheet 100 and the battery sheet 100 is further facilitated.

Thereby, the first region and the second region may be spaced apart in the width direction of the silicon substrate 11, and the first connected region and The second communication regions may be parallel to each other and spaced apart in the width direction of the silicon substrate 11, and the plurality of first dispersion regions and the plurality of second dispersion regions may be spaced apart in the length direction of the silicon substrate 1.

The first communication region and the second communication region may both be rectangular and have a length equal to the length of the silicon substrate 11, so that the two wide sides and one long side of the first communication region and the second communication region may be combined with the silicon substrate 11. The two wide sides and one long side are respectively aligned, so that the space can be fully utilized to increase the power of the battery sheet 100.

Optionally, projecting along the thickness direction of the silicon wafer 1 , the outer edges of the first electrode 4 and the second electrode 5 both fall on the contour lines of the first communication region and the second communication region, so that the battery sheet 100 can be further improved. power. Here, it should be noted that for a face member such as the rectangular sheet-shaped first electrode 4 and the second electrode 5 described herein, the "outer edge" refers to its outline, and for the linear member ( For example, in the case of a fine grid line as described herein, the "outer edge" refers to the ends of its ends.

Optionally, the first electrode 4 and the second electrode 5 are both a sheet body and respectively occupy the first communication region and the second communication region, so that the power of the battery sheet 100 can be maximized. Further, the side electrode 3 may be configured in a sheet shape and occupy one side side surface in the width direction of the silicon wafer 1, so that the power of the battery sheet 100 can be improved. Certainly, the specific structure of the side electrode 3, the first electrode 4, and the second electrode 5 is not limited thereto. For example, the side electrode 3, the first electrode 4, and the second electrode 5 may also be discretely formed by a plurality of sub-electrodes that are spaced apart from each other. Type of electrode.

Each of the back first sub-gate lines 71 extends in the width direction of the silicon wafer 1, and each of the back second sub-gate lines 61 also extends in the width direction of the silicon wafer 1. Thereby, the charge transfer path can be reduced, and the power of the battery chip 100 can be improved.

When the first region and the second region are not in contact with each other, and each of the first dispersion regions and each of the second dispersion regions has a rectangular shape in which both the longitudinal direction and the width direction correspond to the longitudinal direction and the width direction of the silicon wafer 1, In the thickness direction of the silicon wafer 1, both ends of each of the back first sub-gate lines 71 are aligned with the two edges of the corresponding first dispersion region in the width direction of the silicon wafer 1, and each of the back second sub-gate lines 61 Both ends are aligned with the two edges of the corresponding second dispersion region in the width direction of the silicon wafer 1. Thereby, the distribution area of the first sub-gate line 71 on the back surface can be increased, thereby increasing the amount of charge collection and further increasing the power of the cell sheet 100.

In addition, the front gate line layer 2 may include a plurality of front sub-gate lines 21 extending in the width direction of the silicon wafer 1 and spaced apart in the longitudinal direction of the silicon wafer 1, whereby the charge transfer path of the front sub-gate lines 21 can be shortened. The charge transfer efficiency is improved and the power of the battery chip 100 is increased. Alternatively, projected in the thickness direction of the silicon wafer 1, both ends of each of the front sub-gate lines 21 may be aligned with the two long sides of the silicon wafer 1. Thereby, the distribution area of the front sub-gate lines 21 can be increased, thereby increasing the amount of charge collection and further increasing the power of the cell sheet 100.

Hereinafter, a battery sheet 100 and a method of manufacturing the same according to an embodiment of the present disclosure will be briefly described with reference to the accompanying drawings.

As shown in FIG. 1, the battery sheet 100 includes a rectangular wafer-shaped silicon substrate 11, the light-receiving surface of the silicon substrate 11 has a front-side diffusion layer 12, and the front-side diffusion layer 12 has an anti-reflection layer 101. The anti-reflection layer 101 has a front gate line layer 2 on the side surface of the silicon substrate 11 having a side diffusion layer 13 on the side, and a side electrode 3 on the side diffusion layer 13 on the side. The backlight side of the silicon substrate 11 includes spaced apart non-discrete first regions and non-discrete second regions.

The first region has a back diffusion layer 14 on the back, the second diffusion layer 15 on the second region, and the passivation layer 102 on the back diffusion layer 14 and the back diffusion layer 15 on the back surface. The passivation layer 102 corresponding to the first type of diffusion layer 14 has a back first gate line layer 7 and a first electrode 4 thereon, and the passivation layer 102 corresponding to the back surface second type diffusion layer 15 has a back second gate line thereon. Layer 6 and second electrode 5. The shape and arrangement position of the above components are as shown in FIGS.

Specifically, in preparing the battery sheet 100, a square conventional silicon substrate body (for example, a conventional silicon substrate having a size of 156 mm*156 mm) can be equally divided and cut into 3-15 pieces of rectangular pieces of constant length by laser. The bulk silicon substrate 11 (for example, having a length of 156 mm) is then subjected to the subsequent process of fabricating the cell sheet 100. Of course, the present disclosure is not limited thereto, and a rectangular sheet-like silicon substrate 11 may be obtained by other means or processes.

Here, it should be noted that the square conventional silicon substrate body can be equally divided into 3 parts and more than 3 parts, thereby shortening the distance that the electric charge migrates from the light receiving surface to the backlight surface, so that the charge collection is efficient and easy, thereby improving the battery sheet 100. Power, and when the square conventional silicon substrate body is divided into 15 parts and 15 parts or less, the cutting process is easy, and the subsequent series-parallel cell sheet 100 consumes less solder, thereby improving the overall power of the cell sheet 100 after serial-parallel connection. cut costs.

Hereinafter, the preparation method of the battery sheet 100 will be described by taking the silicon substrate 11 as a P-type silicon as an example. When the following technical solutions are read by those skilled in the art, it is apparent that the silicon substrate 11 is an N-type silicon battery sheet 100. Preparation method.

A1. Cleaning and texturing: cleaning removes dirt on each surface of the silicon substrate 11, and the texturing reduces the reflectance of each surface of the silicon substrate 11.

A2, diffusion-knotting: preparing a P-N junction by performing double-sided phosphorus diffusion on the silicon substrate 11 through a diffusion furnace;

A3. Mask protection: one side of the length direction of the silicon wafer 1 is protected by paraffin (ie, the area used as the side first diffusion layer 13), and an edge of the back side of the silicon wafer 1 on the same side as the side a partial region other than the edge (ie, a region serving as the back diffusion layer 14 of the first type, that is, the first region);

A4, etching: removing the diffusion layer not protected by paraffin (or water film) on the side surface of the silicon substrate 11 and the backlight surface;

A5, removing paraffin (or water film) protection, to obtain a side first diffusion layer 13 on the side surface of the silicon substrate 11 and a back surface first diffusion layer 14 on the backlight surface of the silicon substrate 11;

A6. Boron diffusion is performed on the paraffin-protected region on the back surface of the silicon substrate 11 to obtain a back diffusion layer 15, a boron diffusion region and a phosphorus diffusion region (ie, the first diffusion layer 14 on the back side and the second diffusion layer on the back surface) 15) not contacting, maintaining a certain safe distance, and presenting a cross-shaped distribution; optionally, the back type first diffusion layer 14 accounts for 30% to 70% of the total area of the backlight surface, optionally, the first type of diffusion layer on the back side The area ratio of the second type diffusion layer 15 to the back surface is 30:70 to 70:30, and 50:50 is optional.

A7, removing the phosphosilicate glass;

A8, PECVD coating: the anti-reflection layer 101 and the passivation layer 102 are respectively evaporated on the light-receiving surface and the backlight surface of the silicon wafer 1, the material Including but not limited to TiO2, Al2O3, SiNxOy, SiNxCy;

A9, processing the back first gate line layer 7 and the first electrode 4 on the passivation layer 102 opposite to the back type first diffusion layer 14, the first back sub-gate line 71 being perpendicular and in contact with the first electrode 4, the back side An outer edge of a gate line layer 7 and the first electrode 4 as a whole falls on the outline of the back diffusion layer 14 of the first type;

A10. processing the back second gate line layer 6 and the second electrode 5 on the passivation layer 102 corresponding to the back surface type second diffusion layer 15, the back second sub-gate line 61 being perpendicular and in contact with the second electrode 5, the back side The outer edges of the second gate line layer 6 and the second electrode 5 as a whole fall on the contour line of the back type second diffusion layer 15 and are sintered;

A11, screen printing front gate line layer 2: screen printing the front gate line layer 2 in the width direction on the anti-reflection layer 101, and making the front sub-gate line 21 perpendicular to the first electrode 4 and the second electrode 5;

A12. The side electrode 3 is formed on the side first diffusion layer 13, and sintered.

Here, it should be noted that the order of execution of steps a9, a10, a11, and a12 can be flexibly changed according to actual needs. In addition, "negative" and "back" as referred to herein mean the backlight surface, and "front" refers to the light receiving surface.

Next, a battery chip matrix 1000 according to an embodiment of the third aspect of the present disclosure will be described.

The cell matrix 1000 is formed by a plurality of, that is, at least two, cell sheets 100 according to the first aspect embodiment described above being connected in series and/or in parallel. For example, the cell array 1000 can be the first cell array 100A, the second cell array 100B, or the third cell array 100C. The first battery array 100A is formed by connecting a plurality of battery cells 100 arranged in a single row and multiple rows of arrays. The second battery array 100B is formed by a plurality of first battery arrays 100A connected in parallel, and the third battery array 100C. The plurality of second cell arrays 100B are connected in series.

Thus, the battery chip matrix 1000 according to the embodiment of the present disclosure has high power, high energy efficiency, simple structure, simple processing, and low cost. In particular, the battery chip matrix 1000 of the embodiment of the present disclosure has high power and does not need to be added with a diode for bypass protection, and the cost is low. In addition, the positive and negative junction boxes can be distributed on both sides of the cell matrix 1000, thereby reducing The amount of connecting cables between adjacent components reduces the cost of the plant.

Next, a solar cell according to an embodiment of the fourth aspect of the present disclosure will be described.

The solar cell includes the cell matrix 1000 of the above-described third aspect embodiment. For example, the solar cell may include, in order from the light receiving side to the backlight side, a first panel, a first bonding layer, a cell matrix 1000, a second bonding layer, and a second panel. Wherein, the first panel is located on the light receiving side of the battery sheet 100 and may be a glass panel made of a glass material to avoid shading, the second panel is located on the backlight side of the battery sheet 100 and may be a conventional back panel, or the second panel may also be For a glass panel made of a glass material, the battery assembly can be a double glass component. The first adhesive layer is disposed between the first panel and the battery sheet 100 and is used for bonding the first panel to the battery sheet 100. At this time, the first adhesive layer may adopt EVA (abbreviation of Ethylene Vinyl Acetate, ie, ethylene). - Vinyl acetate copolymer) made of materials or made of transparent silica gel to ensure good light transmission. The second adhesive layer is disposed between the second panel and the battery sheet 100 and is used for bonding the second panel to the battery sheet 100. At this time, the second adhesive layer can be EVA (Ethylene Vinyl Acetate). The abbreviation, ie ethylene-vinyl acetate copolymer, is made of materials such as transparent silica gel to ensure good light transmission. As a result, the battery assembly has better power, better energy efficiency, easier processing, and lower cost.

Hereinafter, a solar cell according to two specific embodiments of the present disclosure will be briefly described.

Embodiment 1

The solar cell includes: a first panel disposed from the light receiving side to the backlight side, a first insulating layer, a cell matrix 1000, a second insulating layer, and a second panel, wherein the cell matrix 1000 is the first cell array 100A That is to say, the plurality of battery sheets 100 are sequentially arranged and connected in series in the same arrangement form (for example, the light receiving surfaces are all facing backwards and the side electrodes 3 are all facing downwards).

At this time, since the plurality of battery sheets 100 in the single row are placed in the same form, the second electrode 5 of each of the battery sheets 100 is adjacent to the first electrode 4 of the previous one of the battery sheets 100, in other words, each The first electrodes 4 of the battery sheet 100 are each adjacent to the second electrode 5 of the next battery sheet 100, whereby the conductive strips 1001 (e.g., solder ribbons) may be used to adjoin the adjacent two along the length of the silicon wafer 1. The second electrode 5 of the cell 100 and the first electrode 4 are electrically connected together for the purpose of series connection.

Of course, the present disclosure is not limited thereto, and the conductive strip 1001 (for example, a solder ribbon) may be electrically connected to the second electrode 5 and the first electrode 4 of the adjacent two battery sheets 100 along the width direction of the silicon wafer 1. . Of course, it is not limited thereto. For example, the second electrode 5 and the first electrode 4 of the adjacent two battery cells 100 may be serially connected together by using a second panel. Specifically, in this embodiment, the second The insulating layer may have a through hole, and the second panel may include an electrical conductor that penetrates the through hole to connect the adjacent second electrode 5 and the first electrode 4 in series, whereby the electrical conductor on the second panel may be adjacent The two battery sheets 100 are connected in series. The variants are not detailed here.

Therefore, when the battery is packaged, the following steps may be taken: first, the plurality of battery sheets 100 are arranged in a single row and multiple rows, and then the adjacent two battery sheets 100 are connected in series by using the conductive tape 1001 (for example, a solder ribbon). The cell matrix 1000 is obtained together and the bus bar 1002 is taken out. Next, a first panel (eg, glass), a first insulating layer (eg, EVA), a cell matrix 1000, a second insulating layer (eg, EVA), and a second panel (eg, a battery) are sequentially laid in order from bottom to top. The back sheet) is laminated in a laminator to realize packaging of the solar cell to obtain a solar cell.

Embodiment 2

The second embodiment is substantially the same as the embodiment except that the cell matrix 1000 is the third cell array 100C. For example, the first array of cells 100A may be formed into a third array of cells 100C by "first three and then two strings". Therefore, when the back contact battery is packaged, the following steps may be taken: first, the plurality of battery sheets 100 are arranged in a single row and multiple rows, and then the adjacent two battery sheets 100 are replaced by the conductive strip 1001 (for example, a solder ribbon). The first cell array 100A is obtained in series, and then the six first cell arrays 100A are connected in parallel by the bus bar 1002 into two second cell arrays 100B, and then the two second cell arrays 100B are connected in series. The third cell array 100C is formed to obtain a cell wafer matrix 1000, and the positive and negative electrodes are respectively taken out from both ends of the cell wafer matrix 1000.

Next, a first panel (eg, glass), a first insulating layer (eg, EVA), a cell matrix 1000, a second insulating layer (eg, EVA), and a second panel (eg, a battery) are sequentially laid in order from bottom to top. Backboard or glass), laminated in a laminating machine, and equipped with a junction box and a bezel to realize solar cell packaging and fabrication, and to obtain a solar cell. Here, it should be noted that the installation position of the junction box can be set according to actual requirements to better meet the actual requirements. For example, it can be designed on both edges of the cell matrix 1000, and can also be disposed on the cell matrix 1000. The back of the edge, etc.

In summary, the battery sheet 100 and the battery chip matrix 1000 according to the embodiments of the present disclosure have the following advantages.

First, since the first electrode 4 and the second electrode 5 are both located on the backlight side of the silicon substrate 11, the problem of shading of the light receiving surface of the silicon substrate 11 by the first electrode 4 can be effectively solved to improve the solar cell 100. The power, the amount of the silver paste is lowered, and the production cost is lowered. At the same time, the charge collected by the front gate line layer 2 is transferred to the first electrode 4 on the backlight side by the side electrode 3 disposed on the side surface of the silicon substrate 11. The earth simplifies the production process of the battery sheet 100, reduces the manufacturing difficulty and production cost of the battery sheet 100, and enables the battery sheet 100 to be mass-produced on a large scale.

However, in the prior art, EWT (emitter surround back contact battery), MWT (metal surround back contact battery), IBC (full back contact battery) and other back contact batteries, although the light receiving surface can be completely free of gate lines or no main Grid lines to reduce frontal shading, but the manufacturing process of back contact batteries such as EWT, MWT, IBC, etc. is quite complicated. For example, MWT batteries and EWT batteries need to be laser-punched on the silicon wafer, and the electrodes or emitters are made through the holes. It is difficult to make the back of the battery, and the cost is high. It takes a lot of solder to make the components. The IBC battery is extremely demanding in the production process and can only be produced on a small scale.

Secondly, since the second electrode 5 and the first electrode 4 are both located on the backlight side of the battery sheet 100 and are respectively located on both sides in the width direction of the silicon substrate 11, the adjacent two battery sheets 100 can be stacked without being stacked. Discharged and directly connected in series, thereby reducing the welding damage rate, and even reducing the amount of solder used by about 2/3 compared with the prior art, thereby greatly reducing the heat loss of the conductive strip 1001 (such as a solder ribbon), thereby effectively improving the battery sheet. The power of the matrix 1000, and since the second electrode 5 and the first electrode 4 of the adjacent two battery sheets 100 can be connected on the backlight side of the battery sheet 100, the gap between the adjacent two battery sheets 100 is reduced. And the bus bar 1002 can be directly taken out from the battery sheet 100, thereby reducing the overall area of the cell matrix 1000, increasing the effective area of the cell matrix 1000, thereby increasing the power of the cell matrix 1000.

However, in the prior art, there is a connection process in which a back electrode of a cell sheet and a front electrode of an adjacent cell sheet are overlapped in series by solder paste in a tile-laying manner, however, this method can save a large amount of The welding material reduces the heat loss. However, the method of fabricating the components by the tile laying method is easy to cause breakage of the cell in the soldering process and the subsequent lamination process, and the cell at the lamination position cannot participate in power generation, resulting in Waste, affecting component power.

Third, since the cell matrix 1000 can adopt a combination of series and parallel, it can be effectively reduced. The production cost enables the positive and negative junction boxes to be distributed on both sides of the cell matrix 1000, reducing the amount of cable used and reducing the cost of the power station.

However, in the prior art, all the battery cells in the matrix of the battery are sequentially connected in series, so that additional diodes are needed for bypass protection, which is not only low in reliability, complicated in structure, but also high in production cost, which is disadvantageous for large-scale investment. produce.

Fourth, since the back surface of the battery sheet 100 can also be powered by light, the power of the battery sheet 100 is improved, and the fabricated solar battery, for example, a double glass unit can be both aesthetically pleasing and excellent.

In the description of the present disclosure, it is to be understood that the orientation or positional relationship of the terms "upper", "lower", "front", "rear" and the like is based on the orientation or positional relationship shown in the drawings, only for the purpose of The disclosure and the simplification of the present disclosure are not to be construed as limiting or limiting the scope of the present disclosure.

In the present disclosure, the terms "installation", "connected", "connected", "fixed" and the like should be understood broadly, and may be directly connected or indirectly through intermediaries, unless expressly stated otherwise. Connected, it can be the internal communication of two components or the interaction of two components. The specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis. In the present disclosure, the first feature "on" or "under" the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.

In the description of the present specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means a specific feature described in connection with the embodiment or example. A structure, material, or feature is included in at least one embodiment or example of the present disclosure. In the present specification, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and combined.

While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art The scope of the disclosure is defined by the claims and their equivalents.

Claims

A battery sheet (100), comprising:

a silicon wafer (1) comprising a silicon substrate (11), a front first diffusion layer (12) and a back first diffusion layer (14), wherein the silicon substrate (11) The backlight surface includes a non-discrete first region and a non-discrete second region, wherein the area of the first region is 30% to 70% of the area of the backlight surface of the silicon substrate (11) The back diffusion type (14) is disposed only on and over the first region, wherein the front first diffusion layer (12) and the back first diffusion layer (14) ) of the same type;

a front gate line layer (2), the front gate line layer (2) is disposed on the front first diffusion layer (12);

a side electrode (3), the side electrode (3) is disposed on a side surface of the silicon wafer (1) and electrically connected to the front gate line layer (2);

a first gate line layer (7) and a first electrode (4), the back first gate line layer (7) and the first electrode (4) are electrically connected and are disposed on the back side of the first type of diffusion On the layer (14), the first electrode (4) is electrically connected to the side electrode (3);

a second electrode (5) disposed on the second region and not in contact with the back first gate line layer (7).
The battery chip (100) according to claim 1, further comprising:

a second gate line layer (6) on the back surface, the second gate line layer (6) on the back surface is disposed on the second region, wherein the back second gate line layer (6) and the second electrode ( 5) electrically connected and not in contact with the first electrode (4).
The battery sheet (100) according to claim 1, wherein the silicon wafer (1) comprises a back surface second type diffusion layer (15), the back surface second type diffusion layer (15) and the back surface The first type of diffusion layer (14) is of a different type and is only disposed on and covered on the second region, wherein the second electrode (5) is disposed on the back second diffusion layer (15) .
The battery chip (100) according to claim 3, wherein the silicon substrate (11) is made of a P-type, and the front first diffusion layer (12) is a phosphorus diffusion layer, the back surface The second type of diffusion layer (15) is a boron diffusion layer.
The battery chip (100) according to claim 3, wherein the silicon substrate (11) is made of N-type silicon, and the front first diffusion layer (12) is a boron diffusion layer, The second type of diffusion layer (15) on the back side is a phosphorus diffusion layer.
The battery chip (100) according to claim 1, wherein the back first gate line layer (7) and the first electrode (4) are not overlapped with each other and are in contact with each other.
The battery chip (100) according to claim 2, wherein the back second gate line layer (6) and the second electrode (5) are non-overlapping and in contact with each other.
The battery sheet (100) according to claim 1, wherein the first area and the second area Do not touch each other.
The battery sheet (100) according to claim 8, wherein the first region and the second region are in a non-contact finger-crossing distribution, wherein

The first area includes a first communication area and a plurality of first dispersion areas, and the plurality of first dispersion areas are spaced apart in a longitudinal direction of the first communication area and are both in communication with the first communication area.

The second area includes a second communication area and a plurality of second dispersion areas, and the plurality of the second dispersion areas are spaced apart in a length direction of the second communication area and are both connected to the second communication area.

The first communication area and the second communication area are opposite to each other, and the plurality of first dispersion areas and the plurality of second dispersion areas are in the first connection area and the second connection area. Alternating one by one, and the plurality of first dispersed regions are not in contact with the plurality of second dispersed regions and the second connected regions, and the plurality of second dispersed regions and the plurality of first Both the dispersed area and the first connected area are not in contact.
The battery sheet (100) according to claim 1, wherein the back first gate line layer (7) comprises a plurality of back first sub-pieces extending in a direction perpendicular to a length of the first electrode (4) A gate line (71) including a plurality of back second sub-gate lines (61) extending in a length direction perpendicular to the second electrode (5).
The battery sheet (100) according to claim 1, wherein the silicon wafer (1) comprises a side first diffusion layer (13), and the side first diffusion layer (13) is provided On the side surface of the silicon substrate (11), the side electrode (3) is provided on the side first diffusion layer (13).
The battery sheet (100) according to any one of claims 1 to 11, characterized in that the silicon wafer (1) has a span of 20 mm to 60 mm in a direction perpendicular to the side electrode (3).
The battery sheet (100) according to claim 12, wherein the silicon wafer (1) is a rectangular sheet, and the first electrode (4) and the second electrode (5) are respectively placed against each other. The two long sides of the silicon wafer (1) are disposed and extend along the length direction of the silicon wafer (1), and the side electrodes are disposed adjacent to the first electrode (4) of the silicon wafer (1) One side of the long side of the surface.
The battery chip (100) according to claim 1, further comprising:

The anti-reflection layer (101) is disposed between the front first diffusion layer (12) and the front gate layer (2).
The battery chip (100) according to claim 14, wherein the anti-reflection layer (101) is further disposed between the side electrode (3) and the silicon substrate (11).
The battery chip (100) according to claim 3, further comprising:

A passivation layer (102) is disposed between the back first diffusion layer (14) and the back first gate line (7).
The battery chip (100) according to claim 16, wherein the passivation layers (102) are respectively provided On the back surface first type diffusion layer (14) and the back surface second type diffusion layer (15), and filling the back surface first type diffusion layer (14) and the back surface second type diffusion layer ( 15) Between.
A cell stack (100) characterized by being connected in series and/or in parallel by a plurality of cell sheets (100) according to any one of claims 1-17.
A solar cell characterized by comprising a cell matrix (1000) according to claim 18.