CN107564973A - Cell piece, cell piece matrix, the preparation method of solar cell and cell piece - Google Patents
Cell piece, cell piece matrix, the preparation method of solar cell and cell piece Download PDFInfo
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- CN107564973A CN107564973A CN201610512518.2A CN201610512518A CN107564973A CN 107564973 A CN107564973 A CN 107564973A CN 201610512518 A CN201610512518 A CN 201610512518A CN 107564973 A CN107564973 A CN 107564973A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses the preparation method of a kind of cell piece, cell piece matrix, solar cell and cell piece, cell piece includes：Silicon chip, front gate line layer, lateral electrode, first electrode, back side grid line layer and second electrode, silicon chip includes silicon chip, positive first kind diffusion layer, back side first kind diffusion layer and the back side the second class diffusion layer, the shady face of silicon chip includes non-touching first area and second area, back side first kind diffusion layer is only defined and is covered with the first region, the back side the second class diffusion layer is only defined and is covered with the second region, front gate line layer is located on positive first kind diffusion layer, lateral electrode is located on the side surface of silicon chip and electrically connected with front gate line layer, first electrode is located on the first kind diffusion layer of the back side and electrically connected with lateral electrode, back side grid line layer and second electrode are electrically connected and are all provided with overleaf on the second class diffusion layer.According to the cell piece of the present invention, leakproof is electrically good, power is high.
Description
Technical field
The present invention relates to technical field of solar batteries, more particularly, to a kind of cell piece, cell piece matrix, solar cell
And the preparation method of cell piece.
Background technology
Crystal silicon solar cell sheet in correlation technique, smooth surface and shady face have 2-3 root silver main gate lines as battery respectively
The both positive and negative polarity of piece, these silver-colored main gate lines not only consume substantial amounts of silver paste, and because block incident light so as to cause cell piece
Efficiency decline.Further, since both positive and negative polarity is respectively distributed on the smooth surface and shady face of cell piece, when cell piece is connected,
Need to be welded to the negative electrode of cell piece smooth surface on the positive electrode of adjacent cell piece shady face using welding, so as to cause to weld
It is cumbersome to connect technique, welding material uses the problem of more, moreover, easily causing cell piece during welding and in follow-up laminating technology
And the breakage of welding.
In addition, the cell piece matrix in correlation technique is typically to be sequentially connected in series by 72 or 60 cell pieces, form
Three loops of six string battery strings compositions, now, typically at least need three diodes, so as to set up one on each loop
Diode carries out bypass protection, because diode is generally disposed in the terminal box of battery, so as to add integrated junction box
Cost, the structural complexity of battery is caused to improve, moreover, when the series component being in series by multiple cell pieces is carried out again
During series connection, connecting cable dosage is very big, and waste of material is a lot, causes power station cost to increase.
The content of the invention
It is contemplated that at least solves one of technical problem present in prior art.Therefore, the invention reside in propose a kind of electricity
Pond piece, the cell piece leakproof is electrically good, and power is high.
The present invention also proposes a kind of preparation method of above-mentioned cell piece.
The present invention also proposes a kind of cell piece matrix with above-mentioned cell piece.
The present invention also proposes a kind of solar cell with above-mentioned cell piece matrix.
Cell piece according to a first aspect of the present invention, including：Silicon chip, the silicon chip includes silicon chip, the positive first kind spreads
Layer, back side first kind diffusion layer and the back side the second class diffusion layer, wherein, the shady face of the silicon chip includes not connecing mutually
Tactile first area and second area, the positive first kind diffusion layer is located on the smooth surface of the silicon chip, the back side
First kind diffusion layer is only defined and is covered with the first area, and the second class of back side diffusion layer is only defined and is covered with institute
State on second area, wherein, the back side first kind diffusion layer is identical with the type of the positive first kind diffusion layer, described
The back side the second class diffusion layer is different from the type of the positive first kind diffusion layer；Front gate line layer, the front gate line layer are set
On the positive first kind diffusion layer；Lateral electrode, the lateral electrode be located on the side surface of the silicon chip and with it is described just
Face grid line layer electrical connection；First electrode, the first electrode be located on the back side first kind diffusion layer and with the lateral electrode
Electrical connection；Back side grid line layer and second electrode, the back side grid line layer and the second electrode electrically connect and are each provided at the back of the body
On the second class diffusion layer of face.
According to the cell piece of the present invention, leakproof is electrically good, and power is high.
In certain embodiments, described the is all fallen within along the outward flange of the thickness direction projection of the silicon chip, the first electrode
On the contour line in one region.
In certain embodiments, mutually not stacked and contact is connected the back side grid line layer with the second electrode.
In certain embodiments, it is overall along the thickness direction projection of the silicon chip, the back side grid line layer and the second electrode
Outward flange all fall within the contour line of the second area.
In certain embodiments, the back side grid line layer is included along a plurality of back of the body perpendicular to second electrode length direction extension
Face grid line.
In certain embodiments, the front gate line layer is included along perpendicular to a plurality of front of lateral electrode length direction extension
Sub- grid line.
In certain embodiments, the silicon chip further comprises the side first kind diffusion layer being located on the silicon chip side surface,
The lateral electrode is located on the side first kind diffusion layer, wherein, the side first kind diffusion layer and described positive first
The type of class diffusion layer is identical.
In certain embodiments, at least one in the first area and the second area is non-discrete region.
In certain embodiments, the silicon chip is 20mm~60mm in the span on the lateral electrode direction.
In certain embodiments, the silicon chip is rectangle lamellar body, and the first electrode and the second electrode recline institute respectively
Two long sides for stating silicon chip set and extended along the length direction of the silicon chip, and the lateral electrode is located at the silicon chip width side
On the side long side side surface of the upward neighbouring first electrode.
In certain embodiments, the silicon chip is p-type, and the positive first kind diffusion layer is phosphorus-diffused layer, the back side
Second class diffusion layer is diffused layer of boron.
In certain embodiments, the silicon chip is N-type, and the positive first kind diffusion layer is diffused layer of boron, the back side
Second class diffusion layer is phosphorus-diffused layer.
In certain embodiments, the cell piece includes：Anti-reflection layer, the anti-reflection layer are located at the positive first kind diffusion layer
Between the front gate line layer.
In certain embodiments, the anti-reflection layer is also located between the lateral electrode and the silicon chip.
In certain embodiments, described cell piece includes：Passivation layer, the passivation layer are located at the class of the back side second diffusion
Between layer and the back side grid line layer.
In certain embodiments, the passivation layer is respectively provided at the back side first kind diffusion layer and the diffusion of the class of the back side second
On layer and it is filled between the back side first kind diffusion layer and the back side the second class diffusion layer.
The preparation method of cell piece according to a second aspect of the present invention, for preparing cell piece according to a first aspect of the present invention,
The silicon chip includes side interlayer, and the side interlayer is located on the side surface of the silicon chip, and the lateral electrode is located at institute
State on the interlayer of side, the preparation method comprises the following steps：A：Obtain the silicon chip；B：Made on the silicon chip
The standby positive first kind diffusion layer, the side interlayer, the back side first kind diffusion layer and the diffusion of the class of the back side second
Layer obtains the silicon chip；C：Prepared on the silicon chip first electrode, the back side grid line layer, the second electrode,
The front gate line layer and the lateral electrode.
In certain embodiments, the step A is specially：By the conventional silicon chip body of square according to the constant rule of length
Split at least once, to obtain multiple silicon chips.
In certain embodiments, the side interlayer is the side first kind diffusion layer being covered with the side surface, the step
Suddenly B is specially：First kind diffusion is prepared on the smooth surface of the silicon chip, the side surface and the first area
Layer, to obtain the positive first kind diffusion layer, the side first kind diffusion layer, the back side first kind diffusion layer,
The back side the second class diffusion layer is prepared on the second area, to obtain the second class of back side diffusion layer.
Cell piece matrix according to a third aspect of the present invention, by cell piece series connection described according to a first aspect of the present invention and/or simultaneously
Connection forms.
Solar cell according to a fourth aspect of the present invention, including cell piece matrix according to a third aspect of the present invention.
The additional aspect and advantage of the present invention will be set forth in part in the description, and partly will become bright from the following description
It is aobvious, or recognized by the practice of the present invention.
Brief description of the drawings
Fig. 1 is the schematic diagram of the sensitive side of cell piece according to embodiments of the present invention；
Fig. 2 is the schematic diagram of the backlight side of the cell piece shown in Fig. 1；
Fig. 3 is the schematic diagram of the side of the cell piece shown in Fig. 2；
Fig. 4 is that two cell pieces shown in Fig. 1 use the schematic diagram that conductive strips are connected；
Fig. 5 is the schematic diagram that conductive strips are removed in Fig. 4；
Fig. 6 is the schematic diagram of cell piece matrix according to embodiments of the present invention；
Fig. 7 is the circuit diagram of the cell piece matrix shown in Fig. 6.
Reference：
Cell piece matrix 1000；Welding 1001；Busbar 1002；
First battery chip arrays 100A；Second battery chip arrays 100B；3rd battery chip arrays 100C；
Cell piece 100；
Silicon chip 1；Silicon chip 11；Positive first kind diffusion layer 12；Side first kind diffusion layer 13；Back side first kind diffusion layer
14；The back side the second class diffusion layer 15；
Anti-reflection layer 101；Passivation layer 102；
Front gate line layer 2；Positive face grid line 21；Lateral electrode 3；First electrode 4；Second electrode 5；
Back side grid line layer 6；The sub- grid line 61 in the back side.
Embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein identical from beginning to end
Or similar label represents same or similar element or the element with same or like function.Retouched below with reference to accompanying drawing
The embodiment stated is exemplary, it is intended to for explaining the present invention, and is not considered as limiting the invention.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to simplify this
The disclosure of invention, hereinafter the part and setting of specific examples are described.Certainly, they are only example, and mesh
Do not lie in limitation the present invention.In addition, the present invention can in different examples repeat reference numerals and/or letter.This repetition
It is the relation between itself not indicating discussed various embodiments and/or setting for purposes of simplicity and clarity.In addition,
The invention provides various specific techniques and material examples, but those of ordinary skill in the art can be appreciated that other
The applicable property of technique and/or the use of other materials.
Below, the cell piece 100 of embodiment according to a first aspect of the present invention is described with reference to the drawings.Wherein, cell piece 100 is
The back contact solar battery piece converted solar energy into electrical energy.
Cell piece 100 according to embodiments of the present invention, including：Silicon chip 1, front gate line layer 2, lateral electrode 3, first electrode 4,
Back side grid line layer 6 and second electrode 5.Wherein, silicon chip 1 includes silicon chip 11, positive first kind diffusion layer 12, the back side
First kind diffusion layer 14 and the back side the second class diffusion layer 15.
Silicon chip 11 is demihull shape, and two surfaces on the thickness direction of silicon chip 11 are respectively smooth surface and shady face,
Smooth surface is connected with shady face by side surface.Wherein, positive first kind diffusion layer 12 is located on the smooth surface of silicon chip 11,
Such as in a preferred embodiment of the invention, positive first kind diffusion layer 12 is covered with the smooth surface of silicon chip 11,
So as to reduce the difficulty of processing of positive first kind diffusion layer 12, processing efficiency is improved, reduces processing cost, and can be with
Effectively improve the power of cell piece 100.
The shady face of silicon chip 11 includes first area and second area, first area and second area without occuring simultaneously and be not in contact with each other,
That is, the contour line of first area does not contact with the contour line of second area.
Wherein, first area can be non-discrete type region, i.e., more when first area arbitrarily is divided into more sub-regions
Sub-regions can connect into a continuous first area.Back side first kind diffusion layer 14 is only defined on first area, i.e.,
All do not have back side first kind diffusion layer 14 in the remaining surface in addition to first area on the shady face of silicon chip 11, enter
One step, back side first kind diffusion layer 14 is covered with the first region, so, when first area is non-discrete continuum
When, back side first kind diffusion layer 14 can with it is non-discrete, be continuously arranged on silicon chip 11.
Thus, due to back side first kind diffusion layer 14 it is continuous, i.e. non-discrete be arranged on silicon chip 11, and be not from
Ground, i.e. discontinuously is dissipated, such as the discrete forms such as scatterplot shape, zebra strip are presented and are dispersed on silicon chip 11, so as to very big
Ground reduces the difficulty of processing of back side first kind diffusion layer 14, improves processing efficiency, reduces processing cost, and can have
Improve the power of cell piece 100 in effect ground.
Wherein, second area can be non-discrete type region, i.e., more when second area arbitrarily is divided into more sub-regions
Sub-regions can connect into a continuous second area.The back side the second class diffusion layer 15 is only defined on second area, i.e.,
All do not have the back side the second class diffusion layer 15 in the remaining surface in addition to second area on the shady face of silicon chip 11.Enter
One step, the back side the second class diffusion layer 15 is covered with the second region, so, when second area is non-discrete continuum
When, the back side the second class diffusion layer 15 can with it is non-discrete, be continuously arranged on silicon chip 11.
Thus, due to the back side the second class diffusion layer 15 it is continuous, i.e. non-discrete be arranged on silicon chip 11, and be not from
Ground, i.e. discontinuously is dissipated, such as the discrete forms such as scatterplot shape, zebra strip are presented and are dispersed on silicon chip 11, so as to very big
Ground reduces the difficulty of processing of the back side the second class diffusion layer 15, improves processing efficiency, reduces processing cost, and can have
Improve the power of cell piece 100 in effect ground.
Front gate line layer 2 is located on positive first kind diffusion layer 12, that is to say, that front gate line layer 2 can directly or
Be connected on positive first kind diffusion layer 12, now, front gate line layer 2 be located on the smooth surface of silicon chip 1 and with front first
Class diffusion layer 12 is relative, that is to say, that is projected along the thickness direction of silicon chip 1, front gate line layer 2 is without departing from the positive first kind
The contour line of diffusion layer 12.
For example, in some embodiments of the invention, silicon chip 1 can also include anti-reflection layer 101, and anti-reflection layer 101 can be located at just
On face first kind diffusion layer 12.So, when silicon chip 1 includes anti-reflection layer 101, front gate line layer 2, which can be directly arranged in, to be subtracted
On anti-layer 101.And when silicon chip 1 does not include anti-reflection layer 101, front gate line layer 2 can be directly arranged in the positive first kind and expand
Dissipate on layer 12.In addition, anti-reflection layer 101 can also be located at lateral electrode 3 as described herein and side first kind diffusion layer 13 it
Between, now, can have anti-reflection layer 101 on the outer surface of the whole smooth surface of silicon chip 1 and a side surface, so as to side
Just process and manufacture.Furthermore, it is necessary to explanation, the concept of anti-reflection layer 101 as described herein should be those skilled in the art
Known, it mainly plays a part of to reduce reflection, strengthens charge-trapping.For example, the material of anti-reflection layer 101 can include but
It is not limited to TiO2、Al2O3、SiNxOy、SiNxCy。
First electrode 4 is located on back side first kind diffusion layer 14, that is to say, that first electrode 4 can directly or indirectly be set
Overleaf on first kind diffusion layer 14, now, first electrode 4 be located at it is on the shady face of silicon chip 1 and relative with first area,
That is, being projected along the thickness direction of silicon chip 1, first electrode 4 is without departing from first area.
For example, in some embodiments of the invention, silicon chip 1 can also include passivation layer 102, and passivation layer 102 can be located at the back of the body
On face first kind diffusion layer 14.So, when silicon chip 1 includes passivation layer 102, first electrode 4 can be directly arranged in passivation
On layer 102.And when silicon chip 1 does not include passivation layer 102, first electrode 4 can be directly arranged in back side first kind diffusion layer
On 14.In addition, passivation layer 102 can also be located on the back side the second class diffusion layer 15 and back side first kind diffusion layer 14
Between the back side the second class diffusion layer 15, now, can have passivation layer on the outer surface of the whole shady face of silicon chip 1
102, so as to convenient processing and manufacture.Furthermore, it is necessary to explanation, the concept of passivation layer 102 as described herein should be ability
Known to field technique personnel, it mainly plays a part of to reduce reflection, strengthens charge-trapping.For example, the material of passivation layer 102
TiO can be included but is not limited to2、Al2O3、SiNxOy、SiNxCy。
Wherein, because first area and second area are without occuring simultaneously and being not in contact with each other, so as to the first electricity that working (finishing) area is larger
Pole 4, it is preferable that the outward flange along the thickness direction projection of silicon chip 1, first electrode 4 falls on the contour line of first area.
Thus, it is possible to maximumlly utilize first area, the power of cell piece 100 is improved.Here, it is necessary to illustrate, for
For face shape part (such as first electrode 4 and second electrode 5 of rectangle demihull shape as described herein), " outward flange " refers to
It is its contour line, for linear element (such as thin grid line as described herein), " outward flange " refers to its both ends end points.
Back side grid line layer 6 and second electrode 5 are all provided with overleaf on the second class diffusion layer 15, that is to say, that back side grid line layer 6
Can directly or indirectly it be located on the back side the second class diffusion layer 15 with second electrode 5, now, back side grid line layer 6 and second
Electrode 5 is located on the shady face of silicon chip 1 and relative with second area, that is to say, that projected along the thickness direction of silicon chip 1,
Back side grid line layer 6 and second electrode 5 are without departing from second area.Wherein, first electrode 4 neither contacted with back side grid line layer 6,
Also do not contacted with second electrode 5.
For example, in some embodiments of the invention, silicon chip 1 can also include passivation layer 102, and passivation layer 102 can be located at the back of the body
On face the second class diffusion layer 15.So, when silicon chip 1 includes passivation layer 102, back side grid line layer 6 and second electrode 5 can
To be directly arranged on passivation layer 102.And when silicon chip 1 does not include passivation layer 102, back side grid line layer 6 and second electrode 5
It can be directly arranged on the back side the second class diffusion layer 15.
In addition, it is necessary to explanation, in some embodiments of the invention, back side grid line layer 6 and second electrode 5 can be mutual
It is not stacked and contact and be connected, now, back side grid line layer 6 and second electrode 5 be entirely disposed in respectively on the shady face of silicon chip 1 and
Edge directly contacts electrical connection, so as to fully utilization space, the power of raising cell piece 100；In the another of the present invention
In some outer embodiments, back side grid line layer 6 and second electrode 5 can be with superposed, now, back side grid line layer 6 and the
Two electrodes 5 are located on the shady face of silicon chip 1 with union surface of the both after stacked.
Wherein, because first area and second area are without occuring simultaneously and being not in contact with each other, so as to the back side grid that working (finishing) area is larger
Line layer 6 and second electrode 5.Preferably, it is whole along the thickness direction projection of silicon chip 1, back side grid line layer 6 and second electrode 5
The outward flange of body is all fallen within the contour line of second area.Thus, it is possible to maximumlly utilize second area, cell piece is improved
100 power.Here, it is necessary to which explanation, " the overall outward flange of two parts " refer to：Two parts except for
Remaining whole outward flange beyond the connected edge of contact, in addition, for face shape part (such as rectangle lamellar body as described herein
The first electrode 4 and second electrode 5 of shape) for, " outward flange " refers to its contour line, for linear element (such as this
Thin grid line described in text) for, " outward flange " refers to its both ends end points.
Here, it is necessary to which explanation, " first kind diffusion layer " specifically described herein and " the second class diffusion layer " is two variety classeses
Diffusion layer, (such as be directly arranged in or by anti-reflection layer 101 as described herein or passivation layer 102 when conducting medium is located at
Between be connected in) on first kind diffusion layer and the second class diffusion layer when can collect different types of electric charge.In addition, it is necessary to illustrate
, the concept of anti-reflection layer and passivation layer as described herein is well known to those skilled in the art, and it is anti-that both mainly plays reduction
Penetrate, strengthen the effect of charge-trapping.
Thus, the positive first kind diffusion layer 12 in " first kind diffusion layer ", back side first kind diffusion layer 14 and this paper institutes
The side first kind diffusion layer 13 stated is same kind of diffusion layer, can when conducting medium is located on first kind diffusion layer
To collect the electric charge of the first species；And the back side the second class diffusion layer 15 in " the second class diffusion layer " is the diffusion of another species
Layer, when being located at conducting medium on the second class diffusion layer, can collect the electric charge of second species.Here, it is necessary to explanation
It is that the principle that conducting medium collects electric charge on silicon chip should be as it is known to those skilled in the art that I will not elaborate.
For example, when silicon chip 11 is P-type silicon, first kind diffusion layer can be phosphorus-diffused layer, now be arranged on phosphorus-diffused layer
On conducting medium can collect negative electrical charge, and the second class diffusion layer can be diffused layer of boron, be arranged on leading on diffused layer of boron
Dielectric can collect positive charge.In another example when silicon chip 11 is N-type silicon, " first kind diffusion layer " can be that boron spreads
Layer, " the second class diffusion layer " can be phosphorus-diffused layer, repeat no more here.
So, because front gate line layer 2 is located at (such as be directly arranged in or by being connected between anti-reflection layer 101), the first kind expands
Dissipate on layer, so as to which front gate line layer 2 can collect the electric charge (such as negative electrical charge) of the first species.And back side grid line layer 6 is located at
On (such as be directly arranged in or by being connected between passivation layer 102) second class diffusion layer, so as to which positive back side grid line layer 6 can be with
Collect the electric charge (such as positive charge) of second species.
Specifically, first electrode 4 is electrically connected to front gate line layer 2 by lateral electrode 3, so as to front gate line layer 2 collect the
One species electric charge (such as negative electrical charge) can pass to first electrode 4 (such as negative electrode)；Second electrode 5 is electrically connected to the back of the body
Face grid line layer 6, so as to which the second species electric charge (such as positive charge) that back side grid line layer 6 is collected can pass to second electrode 5
(such as positive electrode).Thus, first electrode 4 and second electrode 5 can export electric energy as the positive and negative polarities of cell piece 100.
So, because first electrode 4 can collect the first species electric charge by the front gate line layer 2 positioned at the sensitive side of silicon chip 1,
Second electrode 5 can be by collecting second species electric charge, so as to effectively improve for the back side grid line layer 6 of the backlight side of silicon chip 1
Space availability ratio, further improve the power of cell piece 100 so that cell piece 100 can turn into attractive in appearance, efficient double
Face battery.
It will be appreciated by persons skilled in the art that first electrode 4 and second electrode 5 are opposite polarity electrode, it is necessary to absolutely
Edge, i.e., mutually it is not turned on, do not form electrical connection between each other, now, first electrode 4 and is electrically connected with first electrode 4
All parts for being electrically connected with second electrode 5 and with second electrode 5 of all parts can not directly turn on, can not
Turned on indirectly by any extraneous conducting medium, such as can not contact or be kept apart by insulating materials, so as to avoid
One electrode 4 is connected with the short circuit of second electrode 5.
Specifically, lateral electrode 3 is located on the side surface of silicon chip 1, that is to say, that lateral electrode 3 is not to be embedded in silicon chip 1
Inside, thus, can not only reduce the overall difficulty of processing of cell piece 100, simplify processing technology, improve processing effect
Rate, processing cost is reduced, and can be simply and easily effective by front gate line layer 2 and first electrode 4 by lateral electrode 3
Ground is electrically connected, it is ensured that the reliability that cell piece 100 works.
Further, lateral electrode 3, which is located on the side surface of silicon chip 1, refers to that lateral electrode 3 can be directly or indirectly located at
On the side surface of silicon chip 11.For example, in some embodiments of the invention, lateral electrode 3 can be directly arranged on the interlayer of side,
Now, in order to avoid first electrode 4 and the short circuit of second electrode 5, the electrode conduct that itself there is insulation to wrap up in attached layer can be selected
Lateral electrode 3, so as to avoid conducting medium in lateral electrode 3 with silicon chip 11 without first kind diffusion layer or the
The problem of surface of two class diffusion layers directly contacts and collects the electric charge of second species and pass to first electrode 4, and then ensure
The insulation of first electrode 4 and second electrode 5.
For example, in other embodiment of the present invention, silicon chip 1 can also include side interlayer, and side interlayer can be located at
On the side surface of silicon chip 11, now, lateral electrode 3 can be directly arranged on the interlayer of side is connected in silicon chip 11 with
On side surface.Now, side interlayer is configured to make first electrode 4 and second electrode 5 insulate, that is to say, that works as lateral electrode
3 when being directly arranged on the interlayer of side, will not cause the short circuit connection of first electrode 4 and second electrode 5.
For example, side interlayer can be whole insulating barriers (i.e. side insulation layer) or all first kind diffusion layer (i.e. sides
Face first kind diffusion layer 13) or a part be insulating barrier, another part be first kind diffusion layer.When lateral electrode 3 is directly set
When on the insulating layer, lateral electrode 3 insulate with silicon chip 1, and the charge transfer that can only collect front gate line layer 2 is to first electrode
4, so as to ensure the insulation of first electrode 4 and second electrode 5.And when lateral electrode 3 is directly arranged on first kind diffusion layer
When, lateral electrode 3 can collect electric charge (electric charge of the first species) from first kind diffusion layer, and be collected with front gate line layer 2
Electric charge (electric charge of the first species) pass to first electrode 4 in the lump, so as to not only may insure first electrode 4 and second
The insulation of electrode 5, and the power of cell piece 100 can be improved.
Here, it is necessary to which explanation, the concept such as silicon chip, diffusion layer, passivation layer, anti-reflection layer and conducting medium are from silicon
The principle that electric charge is collected on piece is well known to the skilled person, and I will not elaborate.In addition, in the preferred of the present invention
In embodiment, front gate line layer 2 and back side grid line layer 6 can be for by the electrically conductive thin grid line structures of a plurality of setting spaced apart
Into conducting medium layer, wherein, thin grid line can be made up of silver-colored material, so as on the one hand can improve conduction rate, the opposing party
Face can reduce shading-area, so as in a disguised form increase the power of cell piece 100.
To sum up, cell piece 100 according to embodiments of the present invention, it is connected by being processed in the smooth surface of silicon chip 1 with first electrode 4
Front gate line layer 2, and by the back side grid line layer 6 that is connected with second electrode 5 of shady face processing in silicon chip 1 so that
It can be double-side cell to obtain cell piece 100, and power is higher.
Moreover, by setting lateral electrode 3 in the side of silicon chip 11, can be by first on the existing smooth surface of cell piece 100
Electrode is migrated to backlight side by the sensitive side of silicon chip 1, to prevent sensitive side shading of the first electrode 4 to silicon chip 1, improves electricity
The power of pond piece 100, and may insure that first electrode 4 and second electrode 5 are respectively positioned on the same side of silicon chip 1, consequently facilitating
Electrical connection between multiple cell pieces 100, reduce welding difficulty, when reducing solder usage amount, while reducing welding and after
The damaged probability of cell piece 100 in continuous laminating technology.
In addition, by the way that lateral electrode 3 is located on the side surface of silicon chip 1, so as to significantly reduce the processing of cell piece 100
Difficulty (such as without processing perforate on silicon chip 1 and the manufacturing procedures such as conducting medium being injected into perforate), and then improve and add
Work speed, reduce processing mortality and processing cost.Lateral electrode 3 is located on the width of silicon chip 11 in addition, working as
Side side surface on when, can effectively shorten from the sensitive side of silicon chip 1 to backlight side transmit electric charge path, improve electricity
Lotus transfer rate, so as in a disguised form improve the power of cell piece 100.
In one embodiment of the invention, silicon chip 1 is 20mm~60mm in the span on the direction of lateral electrode 3.
That is, silicon chip 1 includes the side surface that one group (two) are oppositely arranged, one of side surface is provided with lateral electrode 3,
The distance between this group of side surface is 20mm~60mm.Such as in the example shown in Fig. 2 and Fig. 3, when silicon chip 1 is length
When square lamellar body and lateral electrode 3 are located on a long side side surface of silicon chip 1, the width of silicon chip 1 is 20mm~60mm.
Such as in another example of the present invention (the not shown example), when silicon chip 1 sets for rectangle lamellar body and lateral electrode 3
When on a broadside side surface of silicon chip 1, the length of silicon chip 1 is 20mm~60mm.Thus, it is possible to shorten electric charge from
The path that the smooth surface of silicon chip 1 transmits to shady face, so as to improve the transfer rate of electric charge, and then improve cell piece 100
Power.
Such as in the preferred exemplary of the present invention, silicon chip 11 is rectangle lamellar body, i.e. rectangle lamellar body or rectangle lamellar body.
Here, it is necessary to which explanation, " rectangle lamellar body " are not limited to proper rectangle lamellar body as broad understanding, such as
General rectangular lamellar body, the rectangle lamellar body that such as four vertex have fillet or chamfering are also fallen within protection scope of the present invention.
Thus, facilitate the processing of cell piece 100, and facilitate the connection between cell piece 100 and cell piece 100.
Preferably, silicon chip 11 is rectangle lamellar body.For example, silicon chip 11 can by square specification silicon chip body according to
The constant mode of length, which is split and (only refers to " separated " rather than refer in particular to " taking cutting technique "), to be formed, that is to say, that by square
Specification silicon chip body can be divided into the silicon chip 11 of multiple rectangle demihull shapes according to the constant mode of length, now, each
The length of silicon chip 11 with the equal length of square specification silicon chip body and the width sum of multiple silicon chips 11 with just
The width of square specification silicon chip body is equal.
In a preferred embodiment of the invention, back side grid line layer 6 includes extending along perpendicular to the length direction of second electrode 5
The sub- grid line 61 in a plurality of back side, that is to say, that each sub- grid line 61 in the back side is each perpendicular to the length direction of second electrode 5.
Thus, it is possible to shorten the charge transfer path of the sub- grid line 61 in the back side, charge transfer efficiency is improved, improves the work(of cell piece 100
Rate.
In a preferred embodiment of the invention, front gate line layer 2 is included along perpendicular to the extension of the length direction of lateral electrode 3
A plurality of positive face grid line 21, that is to say, that each positive face grid line 21 is each perpendicular to the length direction of lateral electrode 3.Thus,
The charge transfer path of positive face grid line 21 can be shortened, improve charge transfer efficiency, improve the power of cell piece 100.
Below, the cell piece 100 of a specific embodiment of the invention is only illustrated so that silicon chip 1 is rectangle lamellar body as an example.
Preferably, first area and second area can be rectangle, and the length of first area and second area is and silicon substrate
The width sum of the equal length of piece 11, first area and second area is less than the width of silicon chip 11, first area and the
Two regions are spaced apart on the width of silicon chip 11, it is preferable that first area and second area recline silicon chip 11 respectively
Two long sides set.That is, silicon chip 11 can be drawn by two straight lines parallel with the long side of silicon chip 11
The region being divided between the first area of two straight line both sides and second area, two straight lines is first area and second
Gap area between region.Thus, following process is facilitated.Certainly, the invention is not restricted to this, first area and the secondth area
The shape in domain is unlimited, such as first area and second area may be formed as triangle, semicircle etc..
Preferably, first electrode 4 and second electrode 5 recline respectively silicon chip 1 two long sides set and along the length of silicon chip 1
Direction extension is spent, lateral electrode 3 is located at (such as Fig. 2 and Fig. 3 on the side long side side surface of the neighbouring first electrode 4 of silicon chip 1
It is shown), that is to say, that lateral electrode 3 is located on the side side surface of the neighbouring first electrode 4 on the width of silicon chip 1.
That is first electrode 4 and second electrode 5 are spaced apart on the width of silicon chip 1, and recline the two of silicon chip 1 respectively
Bar long side set, lateral electrode 3 be located on a long side side surface of silicon chip 1, be located on the width of silicon chip 1 one
On the side surface of side, and positioned at close to the side of first electrode 4.Thus, the transmission path of electric charge is shorter, cell piece 100
Power is higher, and the processing of cell piece 100 is easier, easily facilitates the connection between cell piece 100 and cell piece 100.
Preferably, first electrode 4 and second electrode 5 can be rectangle lamellar body and length and the equal length of silicon chip 11,
So as to which first electrode 4 and two broadsides of second electrode 5 and a long side can be with two broadsides of silicon chip 11 and one
Long side is alignd respectively, and then can fully utilization space, the power of raising cell piece 100, and facilitate further battery piece 100
With the connection of cell piece 100.
In addition, lateral electrode 3 can also be configured to demihull shape and take on the side side surface on the width of silicon chip 1, so as to
The power of cell piece 100 can be improved.Certainly, the concrete structure of lateral electrode 3, first electrode 4 and second electrode 5 is unlimited
In this, for example, lateral electrode 3, first electrode 4 and second electrode 5 can also be respectively by being spaced apart the multiple sub-electrodes being distributed
Form the electrode of discrete type.
Further, the sub- grid line 61 in each back side extends along the width of silicon chip 1.Thus, it is possible to reduce the biography of electric charge
Defeated path, improve the power of cell piece 100.Preferably, projected along the thickness direction of silicon chip 1, each sub- grid line 61 in the back side
One end can be with the neighbour of the side edge-justified calibrations, the other end of the neighbouring first electrode 4 of second electrode 5 with second area
One side edge-justified calibrations of nearly first area.Thus, it is possible to increase the distribution area of the sub- grid line 61 in the back side, received so as to improve electric charge
Collection amount, further improves the power of cell piece 100, and can be effectively prevented from the short circuit of first electrode 4 and second electrode 5.
Below, the preparation method of the cell piece 100 of embodiment according to a second aspect of the present invention is described with reference to the drawings, wherein, silicon
Substrate includes side interlayer, and side interlayer is located on the side surface of silicon chip 11, and lateral electrode 3 is located on the interlayer of side, this system
Preparation Method is used for the cell piece 100 for preparing first aspect embodiment.
Specifically, preparation method comprises the following steps A, step B, step C.
Step A：Obtain silicon chip 11.It is for instance possible to use by the conventional silicon chip body of square according to the constant rule of length
Then split mode at least once, obtain multiple silicon chips 11.
Step B：Positive first kind diffusion layer 12, side interlayer, back side first kind diffusion layer 14 are prepared on silicon chip 11
With the back side the second class diffusion layer 15, the silicon chip 1 is obtained.
Such as in the specific example of the present invention, side interlayer is side first kind diffusion layer 13.Step B is specially：
First kind diffusion layer is prepared on the smooth surface of silicon chip 11, side surface and first area, to obtain on smooth surface just
Face first kind diffusion layer 12, the side first kind diffusion layer 13 on side surface and the back side first on shady face
Class diffusion layer 14, the second class diffusion layer is prepared on the second region, to obtain the back side the second class diffusion layer on the shady face
15。
Wherein, alternatively, silicon chip 11 can be p-type (i.e. P-type silicon), and now, first kind diffusion layer can be that phosphorus expands
Layer is dissipated, the second class diffusion layer can be diffused layer of boron.Or alternatively, silicon chip 11 can be N-type (i.e. N-type silicon),
Now, first kind diffusion layer can be diffused layer of boron, and the second class diffusion layer can be phosphorus-diffused layer.
Step C：First electrode 4, back side grid line layer 6, second electrode 5, front gate line layer 2 and side are prepared on silicon chip 1
Electrode 3.Specifically, first electrode 4 is overleaf processed on first kind diffusion layer 14；Overleaf add on the second class diffusion layer 15
Work back side grid line layer 6 and second electrode 5；Front gate line layer 2 is processed on positive first kind diffusion layer 12；In side interlayer
Upper processing lateral electrode 3.
Here, can be in positive first kind diffusion layer in order to further improve the power of cell piece 100, it is necessary to illustrate
Anti-reflection layer 101 is prepared on 12, anti-reflection layer 101 is covered with positive first kind diffusion layer 12, then again adds front gate line layer 2
Work is on anti-reflection layer 101 with processing indirectly on positive first kind diffusion layer 12；Meanwhile can be with overleaf the second class diffusion layer
Passivation layer 102 is prepared on 15, passivation layer 102 is covered with the back side the second class diffusion layer 15 and back side first kind diffusion layer 14,
Certainly, passivation layer 102, which can also extend to, is laid on shady face and back side first kind diffusion layer 14, then again by back side grid line
The processing of layer 6 is processed overleaf on the second class diffusion layer 15 on passivation layer 102 with indirect.Thus, by setting anti-reflection layer
101 and passivation layer 102 reduce reflection of the positive back side of cell piece 100 to sunshine, so as to effectively improve battery
The power of piece 100.
Thus, the preparation method of cell piece 100 according to embodiments of the present invention, process is simple, easily realize, difficulty is low, into
This is low.
Below, refer to the attached drawing, briefly describe according to cell piece 100 of a specific embodiment of the invention and preparation method thereof.
As shown in figure 1, cell piece 100 includes the silicon chip 11 of rectangle demihull shape, the smooth surface of silicon chip 11 has front
First kind diffusion layer 12, there is anti-reflection layer 101 on positive first kind diffusion layer 12, there is front gate line layer on anti-reflection layer 101
2, there is side first kind diffusion layer 13, side first kind diffusion layer 13 on the side side surface on the width of silicon chip 11
Upper to have lateral electrode 3, the shady face of silicon chip 11 includes first area spaced apart and second area, wherein, first area
It is upper that there is back side first kind diffusion layer 14, there is first electrode 4 on back side first kind diffusion layer 14, there is the back of the body on second area
Face the second class diffusion layer 15, there is back side grid line layer 6 and second electrode 5 on the back side the second class diffusion layer 15.Wherein, it is above-mentioned
The shape and position of part are as shown in Figure 1-Figure 3.Specifically, on back side first kind diffusion layer 14 and the class of the back side second
Passivation layer can be provided between on diffusion layer 15 and back side first kind diffusion layer 14 and the back side the second class diffusion layer 15
102, first electrode 4, back side grid line layer 6 and second electrode 5 are each provided on passivation layer 102.
Specifically, when preparing the cell piece 100, first can by laser by the conventional silicon chip body of square (such as
Specification is 156mm*156mm conventional silicon chip) decile and cut into the silicon of the constant rectangle demihull shape of 2-8 part length
Substrate 11 (such as length is 156mm), the follow-up production process of cell piece 100 is then carried out again.Certainly, it is of the invention
Not limited to this, other modes or technique can also be used to obtain the silicon chip 11 of rectangle demihull shape.Here, it is necessary to explanation
It is that, when the conventional silicon chip body of square is divided into 2-8 parts, on the one hand can shorten electric charge and be moved from smooth surface to shady face
The distance of shifting, make the collection of electric charge efficiently easy, so as to improve the power of cell piece 100, on the other hand cause silicon chip 11
Easy cutting processing, and the solder of the follow-up consumption of connection in series-parallel cell piece 100 is less, after improving the connection in series-parallel of cell piece 100
Overall power, reduce cost.
Below, the preparation method of cell piece 100 is illustrated so that silicon chip 11 is P-type silicon as an example, works as those skilled in the art
After having read following technical scheme, it is clear that it is appreciated that preparation method of the silicon chip 11 for the cell piece 100 of N-type silicon.
A1, cleaning and texturing：Cleaning removes the dirt on 11 each surface of silicon chip, and making herbs into wool reduces by 11 each surface of silicon chip
Reflectivity；
A2, diffusion：Phosphorus is spread respectively in the positive and negative of silicon chip 11 and boron prepares first kind diffusion layer and the diffusion of the second class
Layer, wherein first kind diffusion layer by silicon chip 11 smooth surface from side surface extend to shady face and including：Positioned at silicon chip 11
Smooth surface on positive first kind diffusion layer 12, the side first kind diffusion layer 13 on the side surface of silicon chip 11,
And the back side first kind diffusion layer 14 on the shady face of silicon chip 11, wherein the second class diffusion layer is positioned at silicon chip
The back side the second class diffusion layer 15 on 11 shady face, wherein, back side first kind diffusion layer 14 and the back side the second class diffusion layer
15 edge does not contact, certain safe distance be present.Edge etch：Remove and remove side first on the side surface of silicon chip 11
P-N junction beyond diffusion layer, remove phosphorosilicate glass；
Specifically, above-mentioned steps a2 and a3 can also be expanded to：In the two-sided of silicon chip 1 while first kind diffusion layer is spread,
Then protective layer is made on first area and side long side side surface adjacent with first area, then etches shady face and side table
Diffusion layer on the region of the unprotected layer protection in face, then makes the second class diffusion layer, then removes and protect on the second region
Sheath and phosphorosilicate glass；
A3, PECVD plated film：Anti-reflection layer 101 and passivation layer 102, material are deposited respectively in the smooth surface and shady face of silicon chip 1
Material includes but is not limited to TiO2、Al2O3、SiNxOy、SiNxCy；
A4, silk-screen printing first electrode 4 and second electrode 5：Adhering to the overleaf passivation layer 102 on the second class diffusion layer 15
Upper silk-screen printing back side grid line layer 6 and second electrode 5, adhering to overleaf on the passivation layer 102 on first kind diffusion layer 14
Silk-screen printing first electrode 4, and dry.Wherein, first electrode 4 is overleaf within the region of first kind diffusion layer 14,
Back side grid line layer 6 and second electrode 5 be overleaf within the region of the second class diffusion layer 15, one end of back side grid line layer 6 with
Second electrode 5 connects, the other end and first electrode 4 are not connected to, certain safe distance be present；
A5, silk-screen printing front gate line layer 2：The silk-screen printing front gate line layer 2, and making in the width direction on anti-reflection layer 101
Positive face grid line 21 is dried perpendicular to first electrode 4 and second electrode 5；
A6, make lateral electrode 3 on side first kind diffusion layer 13 and dry.Here, it is necessary to illustrate, step a4,
A5, a6 execution sequence can be according to being actually needed flexible exchange.In addition, " reverse side " mentioned in this article, " back side " are
Refer to shady face, " front " refers to smooth surface.
Below, the cell piece matrix 1000 of embodiment according to a third aspect of the present invention is described.
Cell piece matrix 1000 by it is multiple, i.e. at least two connected according to the cell piece 100 of above-mentioned first aspect embodiment and/
Or it is formed in parallel.For example, cell piece matrix 1000 can be the first battery chip arrays 100A, the second battery chip arrays 100B,
Or the 3rd battery chip arrays 100C, wherein, the first battery chip arrays 100A by single-row multirow array arrangement multiple cell pieces
100 are in series, and the second battery chip arrays 100B is formed in parallel by multiple first battery chip arrays 100A, the 3rd cell piece
Array 100C is in series by multiple second battery chip arrays 100B.
Thus, the power of cell piece matrix 1000 according to embodiments of the present invention is good, efficiency is high, simple in construction, simple processing,
Cost is low.Specifically, the power of the cell piece matrix 1000 of the embodiment of the present invention is high, and need not add diode progress
Bypass protection, cost is low, in addition, positive and negative terminal box can be distributed in the both sides of cell piece matrix 1000, so as to reduce phase
The dosage of connecting cable between adjacent component, reduces power station cost.
Below, the solar cell of embodiment according to a fourth aspect of the present invention is described.
Solar cell includes the cell piece matrix 1000 of above-mentioned third aspect embodiment.For example, solar cell is from sensitive side
It can include successively to backlight side：First panel, the first tack coat, cell piece matrix 1000, the second tack coat, Yi Ji
Two panels.Wherein, first panel be located at cell piece 100 sensitive side and can be made of glass material glass panel with
Avoid shading, second panel is located at the backlight side of cell piece 100 and can be Normal back plate, or second panel can also be
The glass panel made of glass material, now solar cell can be solar double-glass assemblies.First tack coat is located at first panel
Between cell piece 100 and for first panel to be bonded into cell piece 100, now, the first tack coat can use EVA
(Ethylene Vinyl Acetate abbreviation, i.e. ethene-vinyl acetate copolymer) material is made or using transparent silica gel etc.
Material is made, to ensure good translucent effect.Second tack coat is located between second panel and cell piece 100 and for inciting somebody to action
Second panel is bonded to cell piece 100, and now, the second tack coat can use EVA (Ethylene Vinyl Acetate contractings
Write, i.e. ethene-vinyl acetate copolymer) material is made or is made of materials such as transparent silica gels, to ensure good printing opacity
Effect.Thus, the power of solar cell is more preferable, efficiency is more preferable, processing is easier, cost is lower.
Below, the solar cell according to two specific embodiments of the invention is briefly described.
Embodiment one,
Solar cell includes：The first panel that is set gradually from sensitive side to backlight side, the first insulating barrier, cell piece matrix
1000th, the second insulating barrier and second panel, wherein, cell piece matrix 1000 is above-mentioned first battery chip arrays 100A,
That is multiple cell pieces 100 according to same pose pattern (such as smooth surface backwards, the pendulum directed downwardly of lateral electrode 3
Put form), be arranged in order and concatenate connected.
Now, because multiple cell pieces 100 in single-row are put according to same form of, therefore, each cell piece 100
Second electrode 5 is adjacent with the first electrode 4 of a cell piece 100 thereon, in other words, the first of each cell piece 100
Electrode 4 is adjacent with the second electrode 5 of its next cell piece 100, thus, it is possible to (such as be welded using conductive strips 1001
Band) second electrode 5 of two adjacent cell pieces 100 and first electrode 4 are connected electrically in along the length direction of silicon chip 1
Together, to reach the purpose of series connection.
Certainly, the invention is not restricted to this, width of the conductive strips 1001 (such as welding) along silicon chip 1 can also be incited somebody to action
The second electrode 5 and first electrode 4 of two adjacent cell pieces 100 are electrically connected.Certainly, this is also not limited to, example
Such as, the second electrode 5 of two adjacent cell pieces 100 and first electrode 4 can also be serially connected using second panel,
Specifically, in this embodiment, there can be perforation on the second insulating barrier, second panel can include through perforation with by phase
Adjacent second electrode 5 and the electric conductor of the series connection conducting of first electrode 4, thus, electric conductor in second panel can will be adjacent
Two cell pieces 100 be serially connected.I will not elaborate deformation program.
Thus, when encapsulating above-mentioned battery, following steps can be used：First, by the single-row multirow battle array of multiple cell pieces 100
Row arrangement, two adjacent cell pieces 100 then be cascaded to obtain battery using conductive strips 1001 (such as welding)
Piece matrix 1000, and draw busbar 1002.Then, according to order from top to bottom, lay successively first panel (such as
Glass), the first insulating barrier (such as EVA), cell piece matrix 1000, the second insulating barrier (such as EVA) and second
Panel (such as battery back-sheet), and laminating machine laminating is put into, so as to realize the encapsulation of solar cell, obtain solar cell.
Embodiment two,
Embodiment two is substantially the same with embodiment one, the difference is that only：Cell piece matrix 1000 is the 3rd battery chip arrays
100C.Such as the first battery chip arrays 100A can be formed into the 3rd cell piece battle array by the way of " first three and again two going here and there "
Arrange 100C.Thus, when encapsulating above-mentioned back contact battery, following steps can be used：First, by multiple cell pieces 100
Single-row multirow array arrangement, two adjacent cell pieces 100 are then connected on one using conductive strips 1001 (such as welding)
Rise and obtain the first battery chip arrays 100A, it is then using busbar 1002 that six the first battery chip arrays 100A tri- or three are in parallel
Into two the second battery chip arrays 100B, two the second battery chip arrays 100B are then connected into the 3rd battery chip arrays again
100C, so as to obtain cell piece matrix 1000, then by both positive and negative polarity respectively from the extraction of the both ends of cell piece matrix 1000.
Then, according to order from top to bottom, lay successively first panel (such as glass), the first insulating barrier (such as EVA),
Cell piece matrix 1000, the second insulating barrier (such as EVA) and second panel (such as battery back-sheet or glass), and put
Enter laminating machine laminating, terminal box and frame are installed, so as to realize the encapsulation of solar cell and making, obtain solar cell.
Here, it is necessary to which explanation, the set location of terminal box can be set according to actual requirement, preferably to meet actual requirement,
Such as it can design at 1,000 two edges of cell piece matrix, 1,000 two close sides of cell piece matrix can also be arranged on
Back side of edge etc..
In summary, cell piece 100 and cell piece matrix 1000 according to embodiments of the present invention, there is following several respects advantage.
Firstth, because first electrode 4 and second electrode 5 are respectively positioned on the backlight side of silicon chip 11, so as to efficiently solve
First electrode 4 to the Problem of Shading of the smooth surface of silicon chip 11, with improve the power of cell piece 100, reduce silver paste dosage,
Production cost is reduced, simultaneously because by front gate line layer 2 by the way of lateral electrode 3 is set on the side surface of silicon chip 11
First electrode 4 of the charge transfer of collection to backlight side, so as to greatly simplifie the production technology of cell piece 100, reduce
The manufacture difficulty and production cost of cell piece 100 so that cell piece 100 can be with scale of mass production.
However, in the prior art, EWT (emitter circulating back contact battery), MWT (metal-wraparound back contact battery),
The back contact batteries such as IBC (full back contact battery), although smooth surface can not have grid line completely or be reduced just without main gate line
Face shading, still, the manufacture craft of the back contact battery such as EWT, MWT, IBC are considerably complicated, such as MWT battery and
EWT batteries need to carry out laser boring on silicon chip, and electrode or launch site are manufactured into cell backside through hole, make
Difficulty is big, and cost is high, makes component and is also required to expend substantial amounts of solder, and IBC batteries require high to manufacture craft, only
Can small-scale production.
Secondth, the backlight side of cell piece 100 is respectively positioned on due to second electrode 5 and first electrode 4 and is located at silicon chip 11 respectively
Both sides on width, so as to which two adjacent cell pieces 100 can need not be stacked, arrange, directly connect successively, from
And reduce welding spoilage, it might even be possible to reduce the solder usage amount compared to existing about 2/3 and then significantly reduce and lead
Electric band 1001 (such as welding) thermal losses, effectively increases the power of cell piece matrix 1000, is additionally, since adjacent two
The second electrode 5 of individual cell piece 100 can connect with first electrode 4 in the backlight side of cell piece 100, so as to reduce phase
Gap between adjacent two cell pieces 100, and busbar 1002 directly can be drawn from cell piece 100, and then reduce
The total area of cell piece matrix 1000, adds the effective area of cell piece matrix 1000, and then adds cell piece square
The power of battle array 1000.
However, in the prior art, have and arrange mode tin cream by the backplate of cell piece and adjacent electricity according to tile type
The Joining Technology of the overlapping series connection of front electrode of pond piece, although however, such a mode can eliminate substantial amounts of welding material,
Thermal losses is reduced, still, the method that the tile type mode of arranging makes component is easy in welding process and follow-up lamination work
The broken damage of cell piece is caused in skill, and the cell piece at stratification position can not participate in generating electricity, and cause to waste, influence group
Part power.
3rd, because cell piece matrix 1000 can use series connection and combined structure in parallel, and then can be effectively reduced
Production cost so that positive and negative terminal box can be distributed in the both sides of cell piece matrix 1000, reduce cable dosage, reduce power station
Cost.
However, in the prior art, all cell pieces in cell piece matrix are both needed to be sequentially connected in series, so as to need additionally to add
Diode carries out bypass protection, and not only reliability is not high, complicated but also production cost is high, is unfavorable for high-volume and puts into
Production.
4th, due to cell piece 100 the back side can also light generate electricity, so as to improve the power of cell piece 100, and
The solar cell that is fabricated to, such as solar double-glass assemblies can not only performance attractive in appearance but also excellent.
In the description of the invention, it is to be understood that the orientation of instruction such as term " on ", " under ", "front", "rear" or
Position relationship is based on orientation shown in the drawings or position relationship, is for only for ease of the description present invention and simplifies description, without
It is instruction or implies that signified device or element there must be specific orientation, with specific azimuth configuration and operation, therefore not
It is understood that as limitation of the present invention.
In the present invention, unless otherwise clearly defined and limited, term " installation ", " connected ", " connection ", " fixation "
It should be interpreted broadly Deng term, for example, it may be being joined directly together, can also be indirectly connected by intermediary, can be two
The connection of individual element internal or the interaction relationship of two elements.For the ordinary skill in the art, Ke Yigen
Understand the concrete meaning of above-mentioned term in the present invention according to concrete condition.In the present invention, unless otherwise clear and definite regulation and limit
Fixed, fisrt feature can be that the first and second features directly contact "above" or "below" second feature, or first and second
Feature passes through intermediary mediate contact.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specific example ",
Or the description of " some examples " etc. means to combine specific features, structure, material or the feature that the embodiment or example describe
It is contained at least one embodiment or example of the present invention.In this manual, need not to the schematic representation of above-mentioned term
Identical embodiment or example must be directed to.Moreover, specific features, structure, material or the feature of description can be with office
Combined in an appropriate manner in one or more embodiments or example.In addition, in the case of not conflicting, this area
Technical staff can be tied the different embodiments or example and the feature of different embodiments or example described in this specification
Close and combine.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Do not departing from
In the case of the principle and objective of the present invention a variety of change, modification, replacement and modification, this hair can be carried out to these embodiments
Bright scope is limited by claim and its equivalent.
Claims (21)
- A kind of 1. cell piece (100), it is characterised in that including：Silicon chip (1), the silicon chip (1) include silicon chip (11), positive first kind diffusion layer (12), the back side first kind and expanded Layer (14) and the back side the second class diffusion layer (15) are dissipated, wherein, the shady face of the silicon chip (11) includes not connecing mutually Tactile first area and second area, the positive first kind diffusion layer (12) are located at the smooth surface of the silicon chip (11) Upper, described back side first kind diffusion layer (14) is only defined and is covered with the first area, the class of the back side second diffusion Layer (15) be only defined and be covered with the second area, wherein, the back side first kind diffusion layer (14) with it is described just The type of face first kind diffusion layer (12) is identical, and the second class of back side diffusion layer (15) is spread with the positive first kind The type of layer (12) is different；Front gate line layer (2), the front gate line layer (2) are located on the positive first kind diffusion layer (12)；Lateral electrode (3), the lateral electrode (3) be located on the side surface of the silicon chip (1) and with the front gate line layer (2) electrically connect；First electrode (4), the first electrode (4) be located on the back side first kind diffusion layer (14) and with the side electricity Pole (3) electrically connects；Back side grid line layer (6) and second electrode (5), the back side grid line layer (6) and the second electrode (5) electrical connection And it is each provided on the second class of back side diffusion layer (15).
- 2. cell piece (100) according to claim 1, it is characterised in that along the thickness direction of the silicon chip (1) Projection, the outward flange of the first electrode (4) are all fallen within the contour line of the first area.
- 3. cell piece (100) according to claim 1, it is characterised in that the back side grid line layer (6) and described Second electrode (5) is not mutually stacked and contacts connected.
- 4. cell piece (100) according to claim 3, it is characterised in that along the thickness direction of the silicon chip (1) The overall outward flange of projection, the back side grid line layer (6) and the second electrode (5) all falls within the wheel of the second area On profile.
- 5. cell piece (100) according to claim 1, it is characterised in that the back side grid line layer (6) includes edge Perpendicular to the sub- grid line in a plurality of back side (61) of the second electrode (5) length direction extension.
- 6. cell piece (100) according to claim 1, it is characterised in that the front gate line layer (2) includes edge Perpendicular to a plurality of positive face grid line (21) of the lateral electrode (3) length direction extension.
- 7. cell piece (100) according to claim 1, it is characterised in that the silicon chip (1) further comprises setting Side first kind diffusion layer (13) on the silicon chip (11) side surface, the lateral electrode (3) are located at the side On first kind diffusion layer (13), wherein, the side first kind diffusion layer (13) and the positive first kind diffusion layer (12) Type it is identical.
- 8. cell piece (100) according to claim 1, it is characterised in that the first area and the second area In it is at least one be non-discrete region.
- 9. the cell piece (100) according to any one of claim 1-8, it is characterised in that the silicon chip (1) exists Span on the lateral electrode (3) direction is 20mm~60mm.
- 10. cell piece (100) according to claim 9, it is characterised in that the silicon chip (1) is rectangle lamellar body, The first electrode (4) and the second electrode (5) recline respectively the silicon chip (1) two long sides set and along institute The length direction extension of silicon chip (1) is stated, the lateral electrode is located at the neighbouring first electrode (4) of the silicon chip (1) On the long side side surface of side.
- 11. cell piece (100) according to claim 1, it is characterised in that the silicon chip (11) is p-type, The positive first kind diffusion layer (12) is phosphorus-diffused layer, and the second class of back side diffusion layer (15) is diffused layer of boron.
- 12. cell piece (100) according to claim 1, it is characterised in that the silicon chip (11) is N-type, The positive first kind diffusion layer (12) is diffused layer of boron, and the second class of back side diffusion layer (15) is phosphorus-diffused layer.
- 13. cell piece (100) according to claim 1, it is characterised in that including：Anti-reflection layer (101), the anti-reflection layer (101) are located at the positive first kind diffusion layer (12) and the front gate line Between layer (2).
- 14. cell piece (100) according to claim 13, it is characterised in that the anti-reflection layer (101) is also located at Between the lateral electrode (3) and the silicon chip (11).
- 15. cell piece (100) according to claim 1, it is characterised in that including：Passivation layer (102), the passivation layer (102) are located at the second class of back side diffusion layer (15) and the back side grid line Between layer (6).
- 16. cell piece (100) according to claim 15, it is characterised in that the passivation layer (102) sets respectively On the back side first kind diffusion layer (14) and the back side the second class diffusion layer (15) and it is filled in the back side Between a kind of diffusion layer (14) and the back side the second class diffusion layer (15).
- 17. a kind of preparation method of cell piece (100), it is characterised in that appoint for preparing according in claim 1-16 Cell piece (100) described in one, the silicon chip include side interlayer, and the side interlayer is located at the silicon chip (11) Side surface on, the lateral electrode is located on the side interlayer, and the preparation method comprises the following steps：A：Obtain the silicon chip (11)；B：The positive first kind diffusion layer (12), the side interlayer, the back of the body are prepared on the silicon chip (11) Face first kind diffusion layer and the back side the second class diffusion layer (15) obtain the silicon chip (1)；C：The first electrode (4), the back side grid line layer (6), the second electrode are prepared on the silicon chip (1) (5), the front gate line layer (2) and the lateral electrode (3).
- 18. the preparation method of cell piece (100) according to claim 17, it is characterised in that the step A tools Body is：The conventional silicon chip body of square is split at least once, to obtain multiple silicon chips according to the constant rule of length (11)。
- 19. the preparation method of cell piece (100) according to claim 17, it is characterised in that the side interlayer To be covered with the side first kind diffusion layer (13) on the side surface, the step B is specially：Prepared on the smooth surface of the silicon chip (11), the side surface and the first area first kind diffusion layer, To obtain the positive first kind diffusion layer (12), the side first kind diffusion layer (13), back side first kind diffusion Layer (14), the back side the second class diffusion layer is prepared on the second area, to obtain the second class of back side diffusion layer (15).
- 20. a kind of cell piece matrix (1000), it is characterised in that as multiple according to any one of claim 1-16 Cell piece (100) series connection and/or be formed in parallel.
- 21. a kind of solar cell, it is characterised in that including according to the cell piece matrix (1000) described in claim 20.
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| US4897123A (en) * | 1987-11-28 | 1990-01-30 | Mitsubishi Denki Kabushiki Kaisha | Solar cells and method for producing solar cells |
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