CN107564878B - Salient point enhanced packaging structure - Google Patents
Salient point enhanced packaging structure Download PDFInfo
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- CN107564878B CN107564878B CN201710694122.9A CN201710694122A CN107564878B CN 107564878 B CN107564878 B CN 107564878B CN 201710694122 A CN201710694122 A CN 201710694122A CN 107564878 B CN107564878 B CN 107564878B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The invention discloses a salient point enhanced packaging structure, which can increase the wrapping area of a polymer supporting material wrapping the root base part of a salient point by designing the size of an opening on a solder mask layer into a structure larger than the sizes of a bonding pad and the salient point and wrapping the polymer supporting ring between the salient point and the side wall of the opening and on the outer side surface of the salient point on the solder mask layer, and can reduce the pulling stress at the salient point so as to improve the reliability of a welding point. Preferably, an annular groove surrounding the bonding pad is formed on the dielectric layer or the insulating layer around the bonding pad, so that the polymer support ring is extended and filled into the annular groove, the polymer wrapping area can be further increased, the reliability of welding spots is improved, the stress at the bonding pad can be improved, and the circuit breakage caused by a cold and hot impact test is prevented. And better, the reinforcing layer is laid on the solder mask layer, the size of the opening of the reinforcing layer is designed to be larger than the sizes of the bonding pad and the bump, the polymer supporting material quantity and the wrapping height can be further ensured, and the reliability of the welding spot is further improved.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a bump-enhanced packaging structure of a semiconductor packaging chip.
Background
Wafer level chip scale packaged chips, when connected to an integrated circuit board, are typically attached to the board by way of chip bumps. At present, WLCSP packaging board level reliability is one of key problems which puzzles product performance, and after SMT drop test, bias TCT (Power-on Cold thermal cycle test) is easy to have bump fracture, and cannot meet high reliability requirements of vehicle-mounted, security protection, intelligent wearing and the like.
Patent document CN106653721A discloses a bump structure surrounding a sealing ring, which includes a chip, the chip has a first surface and a second surface opposite to the first surface, the first surface or the second surface of the chip is provided with at least one metal layer, the metal layer is provided with a solder mask layer, the solder mask layer is provided with a pad exposing the metal layer, the pad is provided with a polymer adhesive and a bump, the polymer adhesive forms a sealing ring having a 3-D polymer network structure after reflow, and the sealing ring wraps a root of the bump on the solder mask layer. Therefore, the sealing ring is surrounded at the root part of the salient point on the solder mask layer, the bonding force between the salient point and the bonding pad is enhanced, the thrust strength of the salient point is greatly increased, the reworkability is good, the reliable connection of the salient point is optimized, and a packaging structure with better reliability is required for vehicle-mounted, security and other product packaging with more rigorous requirements.
Disclosure of Invention
In order to solve the technical problems, the invention provides a salient point enhanced packaging structure, which increases the polymer wrapping area and simultaneously reduces the pulling stress at the salient point, thereby improving the reliability of the welding point at the salient point and meeting the high reliability requirements of vehicle-mounted, security protection, intelligent wearing and the like.
The technical scheme of the invention is realized as follows:
the utility model provides a bump enhancement mode packaging structure, includes a basement, have the pad as the electric derivation point on the basement, just laid the solder mask layer on the basement, it exposes to reserve on the solder mask layer the first opening of pad on the basement, first open-ended radial dimension is greater than the radial dimension of pad, the preparation has the bump on the pad in the first opening, the bump reaches the pad with between the first opening lateral wall and the cladding has the polymer support ring on the bump lateral surface on the solder mask layer.
Further, the substrate is a chip substrate, the front surface of the chip substrate is provided with a dielectric layer and a plurality of welding pads which are positioned in the dielectric layer and electrically connected with metal circuits inside the chip, the dielectric layer is provided with a second opening for exposing the welding pads, and the solder mask layer and the welding pads are formed on the dielectric layer; the welding pad is directly arranged on the exposed welding pad or a metal redistribution layer electrically connected with the welding pad is arranged between the solder mask layer and the dielectric layer, and the welding pad is arranged on the metal redistribution layer; an annular groove surrounding the bonding pad is formed in the dielectric layer, and the polymer support ring extends and is filled into the annular groove.
Furthermore, the base is a chip substrate, an insulating layer and a metal redistribution layer are formed on the back of the chip substrate, the solder mask layer and the bonding pad are formed on the metal redistribution layer, an annular groove surrounding the bonding pad is formed on the insulating layer, and the polymer support ring is filled in the annular groove in an extending mode.
Furthermore, the substrate is a packaging body, the packaging body is provided with an insulating layer and a metal redistribution layer, the solder mask layer and the bonding pad are formed on the metal redistribution layer, an annular groove surrounding the bonding pad is formed in the insulating layer, and the polymer support ring is filled in the annular groove in an extending mode.
Furthermore, a reinforcing layer is laid on the anti-welding layer around the first opening, a third opening for accommodating the salient points is reserved on the reinforcing layer, and the polymer support ring fills gaps between the third opening and the salient points and covers the outer side faces of the salient points on the reinforcing layer.
Further, the thickness of the reinforcing layer is 10-50 μm, and the reinforcing layer is made of photoresist or a dry film.
Furthermore, the salient point is one of a solid solder ball, a hollow solder ball, a plastic core solder ball and a copper core solder ball, and the salient point is arranged on the bonding pad and wraps the bonding pad.
Further, the polymer support ring is formed after reflow soldering of a polymer adhesive.
Further, the diameter of the first opening is 10-100 μm larger than the diameter of the bonding pad.
The invention has the beneficial effects that: the invention provides a salient point enhanced packaging structure, which can increase the wrapping area (height) of a polymer supporting material wrapping the root base part of a salient point by designing the size of an opening on a solder mask layer into a structure larger than the sizes of a bonding pad and the salient point and wrapping the polymer supporting ring between the salient point and the side wall of a first opening and on the outer side surface of the salient point on the solder mask layer, and can reduce the pulling stress at the salient point so as to improve the reliability of a welding point between the salient point and the bonding pad. Preferably, an annular groove surrounding the bonding pad is formed on the dielectric layer or the insulating layer around the bonding pad, so that the polymer support ring is extended and filled into the annular groove, the polymer wrapping area can be further increased, the reliability of welding spots is improved, the stress at the bonding pad can be improved, the stress at the line connection position at the bonding pad is further reduced, and the line fracture caused by a cold-hot impact test is prevented. Preferably, the reinforcing layer is laid on the solder mask layer, the size of the opening of the reinforcing layer is designed to be larger than the size of the bonding pad and the size of the salient point, the polymer support ring is made to fill the gap between the third opening and the salient point and cover the outer side surface of the salient point on the reinforcing layer, the amount of the polymer support material and the wrapping height can be further ensured, and the reliability of the welding point is further improved. Preferably, a reinforcing layer is laid on the solder mask layer, and an annular groove surrounding the bonding pad is formed on the dielectric layer or the insulating layer around the bonding pad, so that the polymer support ring is extended and filled into the annular groove.
Drawings
FIG. 1 is a schematic structural diagram of a bump-enhanced package structure according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a bump enhanced package structure according to another embodiment of the present invention;
FIG. 3 is a schematic top view of a bump enhanced package structure according to another embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a bump enhanced package structure according to another embodiment of the present invention;
fig. 5 is a schematic structural diagram of a bump-enhanced package structure according to still another embodiment of the invention.
Fig. 6 is a schematic structural diagram of an embodiment of a bump-enhanced package structure having an annular groove according to the present invention.
Fig. 7 is a schematic structural diagram of an embodiment of a bump-enhanced package structure having both a ring groove and a stiffener.
Detailed Description
In order to make the present invention comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. For convenience of description, the components in the structures of the drawings of the embodiments are not normally scaled, and therefore do not represent the actual relative sizes of the structures in the embodiments. The upper side or upper side of the structure or surface includes the case where other layers are interposed.
Example 1
As shown in fig. 1, a bump enhanced package structure includes a substrate, which is a chip substrate 101, the front surface of the chip substrate is provided with a dielectric layer 102 and a plurality of welding pads 103 which are positioned in the dielectric layer and electrically connected with metal circuits inside the chip, a second opening exposing the bonding pad is formed on the dielectric layer, a bonding pad 104 serving as an electrical lead-out point is formed on the bonding pad in the second opening on the dielectric layer, a solder mask layer 105 is laid on the dielectric layer, a first opening for exposing the bonding pad is reserved on the solder mask layer, the radial dimension of the first opening is larger than that of the bonding pad, a bump 106 is formed on the bonding pad in the first opening (i.e. a long bump, such as a solder ball, is formed on the bonding pad), and polymer support rings 107 are coated on the salient points, the space between the pad and the side wall of the first opening and the outer side surfaces of the salient points on the solder mask layer. Therefore, the size of the first opening on the solder mask layer is designed to be larger than the size of the bonding pad and the bump, and the polymer support ring is coated between the bump and the side wall of the first opening and on the outer side surface of the bump on the solder mask layer, so that the coating area (height) of the polymer support material coating the root base part of the bump can be increased, the pulling stress at the bump can be reduced, and the reliability of a welding spot between the bump and the bonding pad can be improved.
Example 2
As shown in fig. 2, the present embodiment 2 has most of the technical features of the embodiment 1, and is different in that a metal redistribution layer (see fig. 3, the cutting plane E-E' is not on the line of the metal redistribution layer) for electrically connecting a pad is disposed between a solder mask layer and a dielectric layer, and the pad is disposed on the metal redistribution layer; the bonding pad is not directly arranged on the exposed bonding pad, but is arranged on the metal redistribution layer, and the electrical property of the bonding pad of the chip is led out to the bonding pad and the salient point through the metal redistribution layer.
Example 3
As shown in fig. 4, the present embodiment 2 has most of the technical features of the embodiment 1, and is different in that a solder mask layer and a pad are formed on the back surface of a chip substrate, that is, an insulating layer 202 and a metal redistribution layer are formed on the back surface of the chip substrate, and the solder mask layer and the pad are formed on the metal redistribution layer. In this embodiment, metal redistribution is often performed on the back surface of the chip, for example, the chip is electrically led to the back surface of the chip through the through-silicon via or the slot, then the insulating layer, the metal redistribution layer and the solder mask layer are formed on the back surface of the chip, the bumps are used as electrical lead-out points and formed at the position of a preset opening on the solder mask layer, and the opening is internally provided with a pad corresponding to the metal redistribution layer.
Example 4
The present embodiment 2 has most of the technical features of the embodiment 1, and is different from the present embodiment in that the substrate is a package body, the package body has an insulating layer and a metal redistribution layer thereon, the solder mask layer and the pad are formed on the metal redistribution layer, an annular groove surrounding the pad is formed on the insulating layer, and the polymer support ring is extended and filled into the annular groove. In this embodiment, a situation that a chip interposer, a stacked chip package, and a multilayer rewiring on the front or back of a chip are often used, and a bump on the RDL on the outermost layer of the package is stacked or connected to another chip or a circuit board. Here, the dielectric layer is also replaced by an insulating layer, and an annular groove surrounding the pad may be formed on the insulating layer, and the polymer support ring is extended to fill the annular groove.
As a further improvement of the above-described embodiments, other preferred embodiments are provided below.
Preferably, as shown in fig. 5, an annular groove 108 is formed on the dielectric layer or the insulating layer and surrounds the bonding pad, and the polymer support ring extends and fills the annular groove. Therefore, the annular groove surrounding the bonding pad is formed on the dielectric layer or the insulating layer around the bonding pad, so that the polymer support ring is extended and filled into the annular groove, the polymer wrapping area can be further increased, the reliability of welding spots is improved, the stress at the bonding pad can be improved, the stress at the line connection position at the bonding pad is further reduced, and the line fracture caused by a cold-hot impact test is prevented. The depth of the annular groove may be 5-30 μm, and the outer circumference of the annular groove is preferably slightly smaller than the first opening size. The annular groove can enter and extend into a chip substrate under the condition of not damaging a chip metal circuit preset in a dielectric layer or an insulating layer, and the chip substrate can be a silicon substrate and the like.
Preferably, as shown in fig. 6, a reinforcing layer 109 is laid on the solder mask layer around the first opening, a third opening for accommodating the bump is reserved on the reinforcing layer, and the polymer support ring fills a gap between the third opening and the bump and covers the outer side surface of the bump on the reinforcing layer. Therefore, the reinforcing layer is laid on the solder mask layer, the size of the opening of the reinforcing layer is designed to be larger than the size of the bonding pad and the size of the salient point, the polymer support ring is made to fill the gap between the third opening and the salient point and cover the outer side surface of the salient point on the reinforcing layer, the amount of the polymer support material and the wrapping height can be further ensured, and the reliability of the welding point is further improved.
Preferably, the thickness of the reinforcing layer is 10-50 μm, and the material is photoresist or dry film. For example, after the welding-proof layer is laid, a layer of glue can be coated on the welding-proof layer to increase the using amount of the polymer support ring and ensure the wrapping height.
More preferably, as shown in fig. 7, an annular groove 108 surrounding the bonding pad is formed in the dielectric layer or the insulating layer, the polymer support ring extends and fills the annular groove, meanwhile, a reinforcement layer 109 is laid on the solder mask layer around the first opening, a third opening for accommodating the bump is reserved on the reinforcement layer, and the polymer support ring fills a gap between the third opening and the bump and covers an outer side surface of the bump on the reinforcement layer; the method can better ensure the polymer supporting material quantity and the wrapping height, and better improve the reliability of the welding spot.
Preferably, the salient point is one of a solid solder ball, a hollow solder ball, a plastic core solder ball and a copper core solder ball, and the salient point is arranged on the bonding pad and wraps the bonding pad. Therefore, when the solder ball is formed on the bonding pad, the solder ball wraps the bonding pad, and the pulling stress at the convex point can be reduced.
Preferably, the polymeric support ring is formed from a polymeric adhesive after reflow soldering. The specific implementation mode can adopt that polymer adhesive and salient points are arranged on the welding pads, and the polymer adhesive forms a polymer support ring wrapping the periphery of the salient points after reflowing. Here, the polymer adhesive removes the metal oxide layer on the bump or/and the conductive pad during the reflow process and may also function as a fluxing agent. Preferably, the polymer binder material has a viscosity of 60CP to 40000 CP. The polymer adhesive is a lead-free bump adhesive.
Preferably, the diameter of the first opening is 10 to 100 μm larger than the diameter of the pad. Namely, the diameter of the opening of the solder mask layer is 10-100 μm larger than the diameter of the bonding pad. The specific size can be selected according to the wiring space of the chip. The size of the third opening is preferably the same as the first opening, but is not limited thereto, and may be larger or smaller than the first opening.
The substrate of the present invention may be a chip substrate or a chip package, and the solder mask layer and the bonding pad may be formed on the front surface of the chip substrate or the chip package, or on the back surface opposite to the front surface, and may specifically be electronic components (electronic components) of integrated circuits such as active components (active elements) or passive components (passive elements), digital circuits or analog circuits, Micro Electro Mechanical Systems (MEMS), Micro fluidic Systems (Micro fluidic Systems), or physical sensors (physical sensors) that measure changes in physical quantities such as heat, light, and pressure, a surface acoustic wave device, or a pressure sensor, but not limited thereto.
The above embodiments have been described in detail with reference to the accompanying drawings. Those skilled in the art can make various modifications and changes to the above embodiments without departing from the spirit of the invention, and the scope of the invention is covered thereby.
Claims (6)
1. A bump-enhanced packaging structure is characterized by comprising a substrate, wherein a bonding pad serving as an electrical lead-out point is arranged on the substrate, a solder mask layer is laid on the substrate, a first opening exposing the bonding pad on the substrate is reserved on the solder mask layer, the radial dimension of the first opening is larger than that of the bonding pad, bumps are manufactured on the bonding pad in the first opening, and polymer support rings are wrapped between the bumps and the side wall of the bonding pad and on the outer side surface of the bumps on the solder mask layer; the substrate is a chip substrate, the front surface of the chip substrate is provided with a dielectric layer and a plurality of welding pads which are positioned in the dielectric layer and electrically connected with metal circuits inside the chip, the dielectric layer is provided with a second opening for exposing the welding pads, and the solder mask layer and the welding pads are formed on the dielectric layer; the welding pad is directly arranged on the exposed welding pad or a metal redistribution layer electrically connected with the welding pad is arranged between the solder mask layer and the dielectric layer, and the welding pad is arranged on the metal redistribution layer; an annular groove surrounding the bonding pad is formed in the dielectric layer, and the polymer support ring is filled in the annular groove in an extending mode; or the base is a chip substrate, an insulating layer and a metal redistribution layer are formed on the back surface of the chip substrate, the solder mask layer and the bonding pad are formed on the metal redistribution layer, an annular groove surrounding the bonding pad is formed on the insulating layer, and the polymer support ring is filled in the annular groove in an extending manner; or the substrate is a packaging body, the packaging body is provided with an insulating layer and a metal redistribution layer, the solder mask layer and the bonding pad are formed on the metal redistribution layer, an annular groove surrounding the bonding pad is formed on the insulating layer, and the polymer support ring is filled in the annular groove in an extending mode.
2. The bump-enhanced package structure of claim 1, wherein: and a reinforcing layer is laid on the anti-welding layer around the first opening, a third opening for accommodating the salient points is reserved on the reinforcing layer, and the polymer support ring fills gaps between the third opening and the salient points and coats the outer side surfaces of the salient points on the reinforcing layer.
3. The bump-enhanced package structure of claim 2, wherein: the thickness of the reinforcing layer is 10-50 μm, and the reinforcing layer is made of photoresist or a dry film.
4. The bump-enhanced package structure of claim 1, wherein: the salient point is one of a solid solder ball, a hollow solder ball, a plastic core solder ball and a copper core solder ball, and is arranged on the bonding pad and wraps the bonding pad.
5. The bump-enhanced package structure of claim 1, wherein: the polymeric support ring is formed after reflow soldering of a polymeric adhesive.
6. The bump-enhanced package structure of claim 1, wherein: the diameter of the first opening is 10-100 μm larger than the diameter of the pad.
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| CN114424334A (en) * | 2020-05-29 | 2022-04-29 | 深圳市汇顶科技股份有限公司 | Chip packaging structure, method and chip module |
| CN115135020A (en) * | 2021-03-25 | 2022-09-30 | 庆鼎精密电子（淮安）有限公司 | Exposure system, circuit board, preparation method of circuit board, backlight plate and display device |
| CN118016536A (en) * | 2022-11-09 | 2024-05-10 | 矽磐微电子(重庆)有限公司 | Chip packaging method and packaging structure |
| CN115881675B (en) * | 2023-02-08 | 2024-04-02 | 荣耀终端有限公司 | Packaging substrate, preparation method thereof, packaging structure and electronic equipment |
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