CN107547070B - PMOS tube driving circuit adopting active bleeder technology and design method thereof - Google Patents
PMOS tube driving circuit adopting active bleeder technology and design method thereof Download PDFInfo
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Abstract
The invention discloses a PMOS tube driving circuit adopting an active bleeder technology, which comprises an NPN triode Q2, an NMOS tube Q3, a Schottky diode D2, a capacitor C2, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the grid electrode of the NMOS tube Q3 is connected with one end of the resistor R3, and the drain electrode of the NMOS tube Q3 is connected with one end of the resistor R2; the base electrode of the NPN triode Q2 is connected with the drain electrode of the NMOS tube Q3 through a capacitor C2, the collector electrode of the NPN triode Q2 is connected with the source electrode of the PMOS tube to be driven, and the emitter electrode of the NPN triode Q2 is connected with the other end of the resistor R2 and the grid electrode of the PMOS tube to be driven; the invention also discloses a design method of the PMOS tube driving circuit adopting the active discharge technology. The invention has the advantages of convenient realization, low cost and simple design method steps, and can effectively ensure the quick on and off of the PMOS tube.
Description
Technical Field
The invention belongs to the technical field of switching power supplies, and particularly relates to a PMOS tube driving circuit adopting an active discharge technology and a design method thereof.
Background
With the rapid development of the electronic market, the requirements on the switching power supply are increasing, and meanwhile, the requirements on the performance of the switching power supply are also increasing. The fully-controlled power transistor is one of the core parts of the switching power supply, and the running state and the safety of the fully-controlled power transistor directly influence the performance of the switching converter. The fully controlled power transistors may be classified into Giant Transistors (GTR), insulated Gate Bipolar Transistors (IGBT), power field effect transistors (VDMOS), gate turn-off thyristors (GTO). The power MOS transistor is one of the widest frequency bands in the fully controlled device, so that the power MOS transistor is paid attention to in the high-frequency process, and has the characteristics of short channel, high-resistance drift region, vertical conduction and the like, so that the voltage resistance and the current carrying capacity of the power MOS transistor are greatly improved, and the power MOS transistor is widely applied to the field of switch transformation.
The driving circuit is an interface between the main circuit and the control circuit, and is mainly used for improving the static characteristic and the dynamic characteristic of the device, and the driving circuit should ensure that the power device is completely turned on and reliably turned off so as to reduce the on and off loss of the device, and the driving circuit is used as a power switch to hope to shorten the switching time and reduce the power loss. The power MOS switch tube is a unipolar voltage control device with majority carriers conductive, and has the remarkable advantages of high switching speed, good high-frequency performance, high input impedance, small driving power, no secondary breakdown problem and the like, so that the power MOS switch tube has more advantages as a switch device.
According to the type of the conductive carriers, the power MOS device can be divided into an NMOS device and a PMOS device, wherein most of the carriers in the NMOS tube are electrons, and most of the carriers in the PMOS tube are holes, and the mobility of the electrons is larger than that of the holes, so that under the condition that the geometric dimension and the absolute value of the working voltage are equal, the transconductance of the NMOS tube is large, the speed is high, and the current is large. Therefore, the NMOS tube has wider application range than the PMOS tube, and the switching device in the switching power supply generally adopts the NMOS tube as the switching tube. However, the NMOS transistor is turned on under the condition that the gate-source voltage is at least greater than the threshold voltage, which makes it necessary to generate a higher level than the input voltage on the gate when the source is connected to the highest input level, which requires a bootstrap circuit, an isolation driving circuit or an integrated driving circuit, but the NMOS transistor has the disadvantages of large size, complex circuit structure, and the like, which is not practical.
The most appropriate method for solving the problem is to use a PMOS tube as a switch tube, and when the source electrode is connected with the highest input level, the PMOS tube can be conducted only by pulling the grid electrode level low. However, since parasitic capacitances exist in the gate source, the gate drain and the source drain of the power MOS transistor, the charge and discharge time of the power MOS transistor not only delays the on and off time of the MOS transistor, but also increases the power loss of the circuit. Therefore, in order to enable the PMOS tube to be rapidly turned on and off in the switch circuit, a negative pulse signal is required to be applied between the grid electrode and the source electrode, meanwhile, enough charges are required to be injected and extracted into the grid electrode of the PMOS tube, the PMOS tube can be rapidly turned on and off in the switch circuit, and the voltage at two ends of the parasitic capacitor in the PMOS tube can be rapidly increased and decreased to a required voltage value in the shortest time, so that the switching loss of the PMOS tube is reduced, and the switching efficiency is improved.
In the chinese patent publication with patent application number of 201010509695.8, a PMOS transistor driving circuit and a driving method thereof are disclosed, in which when the PMOS transistor is turned on, the shunt capacitor C2 charges to store charges, and when the PMOS transistor is turned off, the shunt capacitor C2 releases charges, so as to force the NPN transistor Q1 to be turned on, and the gate charges of the PMOS transistor are extracted to be turned off rapidly, thereby improving the turn-off speed of the PMOS transistor. However, the values of the resistors R2 and R3 in the circuit are very difficult, firstly, the resistors R2 and R3 must meet a certain voltage division ratio to ensure that the voltage across the resistor R3 is greater than the threshold voltage of the PMOS transistor, and meanwhile, the voltage across the resistor R2 determines the voltage value when the shunt capacitor C2 is charged to a steady state, and the voltage must be capable of making the NPN transistor Q1 saturated and turned on when the PMOS transistor is turned off. And secondly, if the values of the resistors R2 and R3 are smaller, the charging time of the parasitic capacitance of the grid source of the PMOS tube can be increased, so that the efficiency of the switching circuit is improved, but the currents flowing through the resistors R3 and D1 during the conduction period of the PMOS tube can be increased, so that the switching loss of the circuit is increased.
In the chinese patent publication of patent application No. 200810240744.5, a driving circuit of a P-channel MOSFET in a BUCK regulator is disclosed, the driving circuit includes an upper tube Q1 driving and a lower tube Q2 driving, when the upper tube Q1 is turned on, the lower tube Q2 is controlled to be turned off to turn on an NPN transistor VT1, a larger charging current is provided for a capacitor C1, and the lower tube Q1 is forced to be turned on rapidly; during the period that the upper tube Q1 is turned off, the lower tube Q2 is controlled to be turned on so as to cut off the NPN triode VT1, and the upper tube Q1 is reliably turned off. However, in the period of turning off the Q1 tube, the gate-source parasitic capacitance needs to be discharged through the resistor R1, the discharging speed is slow, the driving circuit needs to control the Q1 tube and the Q2 tube to be alternately turned on, two paths of driving signals need to be reasonably arranged, and the circuit structure is complex.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the PMOS tube driving circuit which adopts the active bleeder technology and has the advantages of simple structure, novel and reasonable design, convenient realization, low cost, high working efficiency, small switching loss, high working reliability and strong practicability.
In order to solve the technical problems, the invention adopts the following technical scheme: the PMOS tube driving circuit adopting the active discharge technology is characterized in that: the high-voltage power supply comprises an NPN triode Q2, an NMOS tube Q3, a Schottky diode D2, a capacitor C2, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the grid electrode of the NMOS tube Q3 is connected with one end of the resistor R3, the other end of the resistor R3 is an input end of an external PWM driving signal, the source electrode of the NMOS tube Q3 is grounded, and the drain electrode of the NMOS tube Q3 is connected with one end of the resistor R2; the base electrode of the NPN triode Q2 is connected with the drain electrode of the NMOS tube Q3 through a capacitor C2, the collector electrode of the NPN triode Q2 is connected with the positive output end of an external power supply and the source electrode of the PMOS tube to be driven, and the emitter electrode of the NPN triode Q2 is connected with the other end of the resistor R2 and the grid electrode of the PMOS tube to be driven; the resistor R1 is connected in parallel between the collector and the emitter of the NPN triode Q2, and the resistor R4 is connected in parallel between the grid and the source of the NMOS tube Q3; the anode of the schottky diode D2 is connected to the emitter of the NPN transistor Q2, and the cathode of the schottky diode D2 is connected to the base of the NPN transistor Q2.
The PMOS transistor driving circuit adopting the active bleeder technique is characterized in that: the LED further comprises a zener diode D1, wherein the anode of the zener diode D1 is connected with the drain electrode of the NMOS tube Q3, and the cathode of the zener diode D1 is connected with the emitter electrode of the NPN triode Q2.
The PMOS transistor driving circuit adopting the active bleeder technique is characterized in that: the model of the NPN triode Q2 is ZTX651.
The PMOS transistor driving circuit adopting the active bleeder technique is characterized in that: the model of the NMOS tube Q3 is IRF510.
The PMOS transistor driving circuit adopting the active bleeder technique is characterized in that: the schottky diode D2 is of the type SS14.
The invention also provides a design method of the PMOS tube driving circuit adopting the active bleeder technology, which has the advantages of simple steps, convenient realization, improved working efficiency of the circuit and reduced switching loss of the circuit, and is characterized by comprising the following steps:
step one, selecting an NPN triode Q2, an NMOS tube Q3 and a Schottky diode D2 with proper types, wherein the specific process is as follows:
step 101, selecting an NPN triode with the amplification factor larger than 100 as an NPN triode Q2;
102, selecting an NMOS tube with current smaller than 10A and drain-source breakdown voltage smaller than or equal to 100V as an NMOS tube Q3;
step 103, selecting a Schottky diode with the rated current smaller than 0.5A and the reverse recovery time smaller than 30ns as a Schottky diode D2;
selecting a resistor R1, a resistor R2, a resistor R3 and a resistor R4 with proper parameters, wherein the specific process is as follows:
step 201, selecting resistance values of a resistor R1 and a resistor R2 between 1kΩ and 10kΩ;
step 202, according to the formulaSelecting the resistance value of a resistor R3, wherein Vcc is the power supply voltage of a PWM control chip in a switching power supply circuit where a PMOS tube to be driven is positioned, I max The peak current of a PWM control chip in a switching power supply circuit where a PMOS tube to be driven is located, t is the switching delay time of an NMOS tube Q3, and C is the parasitic capacitance between the grid electrode and the source electrode of the NMOS tube Q3;
step 203, selecting the resistance value of the resistor R4 according to the formula r4=100deg.r3;
step three, selecting a capacitor C2 with proper parameters, wherein the specific process is as follows:
step 301, according to the formulaCalculating collector current i of NPN triode Q2 in saturated conduction C(Q2) Wherein beta is (Q2) Is the amplification factor of NPN triode Q2, V C2 Steady state value and V for charging capacitor C2 when PMOS tube Q1 is turned on C2 ＝V D1 -V D2 ，V D1 Is the voltage stabilizing value of the voltage stabilizing diode D1, V D2 Is the voltage across the schottky diode D2;
step 302, according to the formulaCalculating the time t from the start of the cut-off of the NMOS tube Q3 to the discharge of the parasitic capacitance C1 between the grid electrode and the source electrode of the PMOS tube to be driven to the voltage of the two ends equal to zero off1 Wherein V is i The input voltage of the switching power supply circuit where the PMOS tube to be driven is positioned;
step 303, according to the formulaSelecting the capacitance value of the capacitor C2;
step four, connecting an NPN triode Q2, an NMOS tube Q3, a Schottky diode D2, a capacitor C2, a resistor R1, a resistor R2, a resistor R3 and a resistor R4 to form a PMOS tube rapid switch driving circuit; the specific process is as follows:
step 401, connecting a gate of an NMOS transistor Q3 with one end of a resistor R3, using a lead wire led out from the other end of the resistor R3 as an input end of an external PWM driving signal, grounding a source of the NMOS transistor Q3, and connecting a drain of the NMOS transistor Q3 with one end of a resistor R2;
step 402, connecting a base electrode of an NPN triode Q2 with one end of a capacitor C2, connecting the other end of the capacitor C2 with a drain electrode of an NMOS tube Q3, connecting a collector electrode of the NPN triode Q2 with an anode output end of an external power supply and a source electrode of a PMOS tube to be driven, and connecting an emitter electrode of the NPN triode Q2 with the other end of a resistor R2 and a grid electrode of the PMOS tube to be driven;
step 403, one end of a resistor R1 is connected with a collector of an NPN transistor Q2, the other end of the resistor R1 is connected with an emitter of the NPN transistor Q2, one end of a resistor R4 is connected with a gate of an NMOS transistor Q3, and the other end of the resistor R4 is connected with a source of the NMOS transistor Q3;
step 404, connecting the anode of the schottky diode D2 with the emitter of the NPN transistor Q2, and connecting the cathode of the schottky diode D2 with the base of the NPN transistor Q2;
step 405, connect the anode of the zener diode D1 with the drain of the NMOS transistor Q3, and connect the cathode of the zener diode D1 with the emitter of the NPN transistor Q2.
The method is characterized in that: in step 302, the parasitic capacitance C1 between the gate and the source of the PMOS transistor to be driven has a value of 1000 pF-2000 pF.
Compared with the prior art, the invention has the following advantages:
1. the PMOS tube driving circuit adopting the active discharge technology has the advantages of simple circuit structure, novel and reasonable design, convenient realization, low cost and strong practicability.
2. According to the PMOS tube driving circuit adopting the active discharge technology, the working state of the circuit is changed by introducing the voltage-stabilizing diode D1, the values of the resistor R1 and the resistor R2 are not limited, and the constant energy storage of the capacitor C2 during the conduction period of the PMOS tube Q1 is ensured, so that the phenomenon of mistaken conduction of the NPN triode Q2 is prevented.
3. The design method of the PMOS tube driving circuit adopting the active discharging technology has simple steps, only needs to select the size of the capacitor C2, the values of the resistor R1 and the resistor R2 are not limited, the values of the resistor R3 and the resistor R4 are simple, the implementation is convenient, the PMOS tube can be effectively ensured to be opened and closed quickly, the working efficiency of the circuit is improved, and the switching loss of the circuit is reduced.
4. The PMOS tube driving circuit adopting the active discharging technology is convenient to control, safe and reliable, and effectively solves the problem that the PMOS tube cannot be rapidly turned on and off, so that the PMOS tube can effectively and reliably work when the existing external PWM controller works at high frequency.
In conclusion, the circuit disclosed by the invention has the advantages of simple structure, convenience in implementation, low cost and simple design method steps, can effectively ensure the rapid on and off of the PMOS tube, and has the advantages of high circuit working effect, high working reliability, strong practicability and wide market prospect.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
FIG. 1 is a schematic circuit diagram of a PMOS tube driving circuit employing active bleed techniques according to the present invention.
FIG. 2 is a flow chart of the method for designing the PMOS transistor driving circuit by adopting the active drain technique.
FIG. 3 is a diagram illustrating an embodiment of an active bleeder technique for a PMOS transistor driver circuit according to the present invention.
Fig. 4A is a waveform diagram of a voltage between a gate and a source measured by an oscilloscope when a PMOS transistor driving circuit employing an active bleeder technique drives a PMOS transistor Q1 to turn on.
Fig. 4B is a test waveform diagram of the voltage between the gate and the source measured by the oscilloscope when the PMOS transistor driving circuit of the present invention drives the PMOS transistor Q1 to turn off.
Fig. 4C is a test waveform diagram of the voltage between the gate and the drain of the PMOS transistor Q1 driven by the PMOS transistor driving circuit according to the present invention using the active drain technique.
Fig. 4D is a test waveform diagram of the voltage between the gate and the drain tested by the oscilloscope when the PMOS transistor driving circuit of the present invention drives the PMOS transistor Q1 to turn off.
Detailed Description
As shown in fig. 1, the PMOS transistor driving circuit adopting the active bleeder technique of the present invention includes an NPN transistor Q2, an NMOS transistor Q3, a schottky diode D2, a capacitor C2, a resistor R1, a resistor R2, a resistor R3, and a resistor R4, wherein a gate of the NMOS transistor Q3 is connected to one end of the resistor R3, the other end of the resistor R3 is an input end of an external PWM driving signal, a source of the NMOS transistor Q3 is grounded, and a drain of the NMOS transistor Q3 is connected to one end of the resistor R2; the base electrode of the NPN triode Q2 is connected with the drain electrode of the NMOS tube Q3 through a capacitor C2, the collector electrode of the NPN triode Q2 is connected with the positive output end of an external power supply and the source electrode of the PMOS tube to be driven, and the emitter electrode of the NPN triode Q2 is connected with the other end of the resistor R2 and the grid electrode of the PMOS tube to be driven; the resistor R1 is connected in parallel between the collector and the emitter of the NPN triode Q2, and the resistor R4 is connected in parallel between the grid and the source of the NMOS tube Q3; the anode of the schottky diode D2 is connected to the emitter of the NPN transistor Q2, and the cathode of the schottky diode D2 is connected to the base of the NPN transistor Q2.
In specific implementation, the drain electrode of the PMOS transistor to be driven is the voltage output terminal Vout.
In this embodiment, as shown in fig. 1, the PMOS transistor to be driven is a PMOS transistor Q1. In fig. 1, C1 is a parasitic capacitance between the gate and the source of the PMOS transistor Q1.
In this embodiment, as shown in fig. 1, the PMOS fast switch driving circuit further includes a zener diode D1, an anode of the zener diode D1 is connected to a drain of the NMOS Q3, and a cathode of the zener diode D1 is connected to an emitter of the NPN transistor Q2. The voltage stabilizing diode D1 can provide large injection current for charging the parasitic capacitor C1 in the PMOS tube Q1 when the PMOS tube Q1 is turned on, so that the conduction efficiency of the PMOS tube Q1 is improved, and the conduction loss of the PMOS tube Q1 is reduced; in addition, the zener diode D1 is introduced into the driving circuit, so that the values of the resistor R1 and the resistor R2 are not limited, and the capacitor C2 is ensured to store constant energy during the conduction period of the PMOS transistor Q1, so as to prevent the NPN transistor Q2 from being turned on by mistake.
In this embodiment, the model of the NPN transistor Q2 is ZTX651.
In this embodiment, the model of the NMOS Q3 is IRF510. The NMOS tube is a unipolar voltage control device which depends on majority carrier conduction and has the advantage of high switching speed, so that the NMOS tube Q3 with low voltage and small current is selected in the driving circuit, and the influence on the switching speed of the PMOS tube Q1 is reduced.
In this embodiment, the schottky diode D2 is of the type SS14.
The invention adopts the active bleeder techniqueThe working principle of the PMOS tube driving circuit is as follows: when the external PWM driving signal outputs a high level, the NMOS tube Q3 is saturated and conducted, the input voltage is charged for the parasitic capacitor C1 through the parasitic capacitor C1, the resistor R2 and the branch of the NMOS tube Q3, and meanwhile, the parasitic capacitor C1 is rapidly charged through the parasitic capacitor C1, the Schottky diode D2, the capacitor C2 and the branch of the NMOS tube Q3. In the parasitic capacitance C1 charging branch, because the resistance value of the resistor R1 is larger, the shunt effect on the parasitic capacitance C1 charging branch is smaller, the parasitic capacitance C1 charges faster, and meanwhile, the parasitic capacitance C1, the schottky diode D2, the capacitor C2 and the NMOS transistor Q3 branch also charge the capacitor C2. Therefore, the voltages at the two ends of the parasitic capacitor C1 and the capacitor C2 are increased, and the drain-source voltage of the NMOS tube Q3 is reduced; when the voltage at both ends of the capacitor C2 rises to a value equal to the regulated voltage of the zener diode D1, the voltage at both ends of the capacitor C2 is constant, the zener diode D1 breaks down reversely, at this time, the input voltage is rapidly charged only by the parasitic capacitor C1, the zener diode D1 and the branch of the NMOS transistor Q3 as the parasitic capacitor C1, the voltage at both ends of the parasitic capacitor C1 rises rapidly, the drain-source voltage of the NMOS transistor Q3 continues to drop until V A ≤V C1 -V TH (V A The voltage between the source electrode and the drain electrode of the NMOS tube Q3; v (V) C1 Is the voltage across the parasitic capacitance C1; v (V) TH Threshold voltage of the NMOS transistor Q3), the NMOS transistor Q3 is turned on linearly, and when the parasitic capacitor C1 is charged to a voltage equal to V at both ends i -V D1 (V i The input voltage V of the switching power supply circuit where the PMOS tube to be driven is D1 A voltage stabilizing value of the voltage stabilizing diode D1), the PMOS tube Q1 is completely conducted; when the output of the external PWM driving signal is at a low level, the NMOS tube Q3 is cut off, the shunt capacitor C2 discharges, the base driving current is provided for the NPN triode Q2, the NPN triode Q2 is saturated and conducted, meanwhile, the resistor R1 is short-circuited, the parasitic capacitor C1 discharges rapidly, and the PMOS tube Q1 is cut off rapidly. The zener diode D1 is used for injecting charges into the parasitic capacitor C1 during the conduction period of the PMOS transistor Q1 to make the parasitic capacitor C1 rapidly conduct, so that the values of the resistor R1 and the resistor R2 are not limited; and the constant energy stored in the capacitor C2 during the conduction period of the PMOS tube Q1 is also ensured, so that the phenomenon that the NPN triode Q2 is turned on by mistake is prevented.
As shown in fig. 2, the design method of the PMOS transistor driving circuit adopting the active bleeder technology of the present invention includes the following steps:
step one, selecting an NPN triode Q2, an NMOS tube Q3 and a Schottky diode D2 with proper types, wherein the specific process is as follows:
step 101, selecting an NPN triode with the amplification factor larger than 100 as an NPN triode Q2; therefore, the discharging speed of the parasitic capacitor C1 in the PMOS tube Q1 can be improved when the PMOS tube Q1 is turned off only by small base current; in this embodiment, the model of the NPN transistor Q2 is ZTX651;
102, selecting an NMOS tube with current smaller than 10A and drain-source breakdown voltage smaller than or equal to 100V as an NMOS tube Q3; in this embodiment, the model of the NMOS transistor Q3 is IRF510;
step 103, selecting a Schottky diode with the rated current smaller than 0.5A and the reverse recovery time smaller than 30ns as a Schottky diode D2; in this embodiment, the schottky diode D2 is SS14;
selecting a resistor R1, a resistor R2, a resistor R3 and a resistor R4 with proper parameters, wherein the specific process is as follows:
step 201, selecting resistance values of a resistor R1 and a resistor R2 between 1kΩ and 10kΩ; in this embodiment, the resistance values of the resistor R1 and the resistor R2 are 1kΩ;
step 202, according to the formulaSelecting the resistance value of a resistor R3, wherein Vcc is the power supply voltage of a PWM control chip in a switching power supply circuit where a PMOS tube to be driven is positioned, I max The peak current of a PWM control chip in a switching power supply circuit where a PMOS tube to be driven is located, t is the switching delay time of an NMOS tube Q3, and C is the parasitic capacitance between the grid electrode and the source electrode of the NMOS tube Q3; in this embodiment, vcc=15v, i max =1a, t=50ns, c=125 pF, according to the formula +.>Calculating to obtain 15 omega < R3 < 400 omega, and selectingThe resistance value of the resistor R3 is 100 omega;
step 203, selecting the resistance value of the resistor R4 according to the formula r4=100deg.r3; the resistor R4 is used to prevent the NMOS transistor Q3 from being turned on by mistake by an interference signal, and in this embodiment, the resistance value of the resistor R4 is selected to be 10kΩ;
step three, selecting a capacitor C2 with proper parameters, wherein the specific process is as follows:
step 301, according to the formulaCalculating collector current i of NPN triode Q2 in saturated conduction C(Q2) Wherein beta is (Q2) Is the amplification factor of NPN triode Q2, V C2 Steady state value and V for charging capacitor C2 when PMOS tube Q1 is turned on C2 ＝V D1 -V D2 ，V D1 Is the voltage stabilizing value of the voltage stabilizing diode D1, V D2 Is the voltage across the schottky diode D2; in this embodiment, beta (Q2) ＝100，V D1 ＝3.6V，V D2 =0.7v, according to formula V C2 ＝V D1 -V D2 Calculating to obtain V C2 =2.9v, according to the formulaCalculating to obtain i C(Q2) ＝0.29A；
Step 302, according to the formulaCalculating the time t from the start of the cut-off of the NMOS tube Q3 to the discharge of the parasitic capacitance C1 between the grid electrode and the source electrode of the PMOS tube to be driven to the voltage of the two ends equal to zero off1 Wherein V is i The input voltage of the switching power supply circuit where the PMOS tube to be driven is positioned; in the present embodiment, V i ＝15V，V D1 ＝3.6V，C1＝1050pF，i C(Q2) =0.29A, according to the formula +.>Calculating t off1 ＝41ns；
Step 303, according to the formulaSelecting the capacitance value of the capacitor C2; in this embodiment, t off1 =41 ns, r2=1kΩ, according to the formula +.>Calculated 41pF < C 2 < 1050pF, therefore, the capacitance of the capacitor C2 is selected to be 1000pF;
step four, connecting an NPN triode Q2, an NMOS tube Q3, a Schottky diode D2, a capacitor C2, a resistor R1, a resistor R2, a resistor R3 and a resistor R4 to form a PMOS tube rapid switch driving circuit; the specific process is as follows:
step 401, connecting a gate of an NMOS transistor Q3 with one end of a resistor R3, using a lead wire led out from the other end of the resistor R3 as an input end of an external PWM driving signal, grounding a source of the NMOS transistor Q3, and connecting a drain of the NMOS transistor Q3 with one end of a resistor R2;
step 402, connecting a base electrode of an NPN triode Q2 with one end of a capacitor C2, connecting the other end of the capacitor C2 with a drain electrode of an NMOS tube Q3, connecting a collector electrode of the NPN triode Q2 with an anode output end of an external power supply and a source electrode of a PMOS tube to be driven, and connecting an emitter electrode of the NPN triode Q2 with the other end of a resistor R2 and a grid electrode of the PMOS tube to be driven;
step 403, one end of a resistor R1 is connected with a collector of an NPN transistor Q2, the other end of the resistor R1 is connected with an emitter of the NPN transistor Q2, one end of a resistor R4 is connected with a gate of an NMOS transistor Q3, and the other end of the resistor R4 is connected with a source of the NMOS transistor Q3;
step 404, connecting the anode of the schottky diode D2 with the emitter of the NPN transistor Q2, and connecting the cathode of the schottky diode D2 with the base of the NPN transistor Q2;
step 405, connect the anode of the zener diode D1 with the drain of the NMOS transistor Q3, and connect the cathode of the zener diode D1 with the emitter of the NPN transistor Q2.
In this embodiment, in step 302, the parasitic capacitance C1 between the gate and the source of the PMOS transistor to be driven is 1000 pF-2000 pF. Preferably, in step 302, the parasitic capacitance C1 between the gate and the source of the PMOS transistor to be driven has a value of 1050pF.
According to the formulaCalculating the value i of the current flowing through the zener diode D1 during the conduction period of the PMOS tube Q1 D1 Wherein P is the rated power of the zener diode D1 during normal operation, V D1 Is the voltage stabilizing value of the voltage stabilizing diode D1; in this embodiment, p=0.5 w, v D1 =3.6v, according to the formula +.>And rounding to obtain i D1 ＝0.14A；
According to the formulaCalculating the charge from the conduction of the NMOS transistor Q3 to the parasitic capacitor C1 to the voltage value equal to V i -V D1 Time t required on1 Wherein V is i The input voltage of the switching power supply circuit where the PMOS tube to be driven is positioned is C1, which is parasitic capacitance between the grid electrode and the source electrode of the PMOS tube to be driven; in the present embodiment, V i ＝15V，V D1 ＝3.6V，C1＝1050pF，i D1 =0.14a, according to the formula +.>And rounding to obtain t on1 =86 ns; thus, the circuit on time is 86ns.
According to the above calculation, t off1 ＝41ns，t on1 The PMOS transistor can be turned on and off rapidly as shown in 86ns.
For example, as shown in fig. 3, the PMOS transistor driving circuit adopting the active bleeder technique of the present invention is applied to a BUCK switching converter, where the BUCK switching converter includes a PMOS transistor Q1, an inductor L, a switching diode D3, and a capacitor C3, one end of the inductor L and a cathode of the switching diode D3 are both connected to a drain of the PMOS transistor Q1, and the other end of the inductor L is an output end of the BUCK switching converter and is connected to one end of the capacitor C3, and both an anode of the switching diode D3 and the other end of the capacitor C3 are grounded.
The working principle of the BUCK switching converter is as follows: during the conduction period of the PMOS tube Q1, the switching diode D3 is cut off due to the reverse voltage, and an external power supply supplies energy to a load through the inductor L and simultaneously stores energy for the inductor L; during the period that the PMOS tube Q1 is turned off, the switching diode D3 is turned on for freewheeling, and the inductor L supplies energy to the load and the capacitor C3 so as to maintain the stability of the output voltage.
FIG. 4A is a waveform diagram of a voltage test between a grid electrode and a source electrode by an oscilloscope when a PMOS tube driving circuit adopting an active discharge technology drives a PMOS tube Q1 to be conducted, wherein each small cell on the ordinate represents 2V voltage; FIG. 4B is a waveform diagram of a voltage between a grid electrode and a source electrode tested by an oscilloscope when a PMOS tube driving circuit adopting an active discharge technology drives a PMOS tube Q1 to be turned off, wherein each small cell on the ordinate represents 2V voltage; FIG. 4C is a waveform diagram of a voltage between the gate and the drain of the PMOS transistor Q1 driven by the PMOS transistor driving circuit using the active drain technique, wherein each cell on the ordinate represents a voltage of 5V; FIG. 4D is a waveform diagram of a voltage between the gate and the drain of the PMOS transistor Q1 tested by an oscilloscope when the PMOS transistor Q1 is driven to be turned off by the PMOS transistor driving circuit adopting the active discharging technology, wherein each cell on the ordinate represents 5V voltage; in fig. 4A to 4D, the abscissa indicates the time of the rising edge and the falling edge of the signal of the PMOS transistor Q1 at the moment of turning on and off, so as to improve the voltage amplitude indicated by the PMOS coordinates by using the zener diode and the active bleeder circuit to switch the PMOS transistor in the PMOS transistor driving circuit adopting the active bleeder technology; the input conditions for the test are: the input voltage is 15V, and the switching frequency is 100KHz. As can be seen from FIGS. 4A to 4D, when the working frequency of the circuit switch is 100KHz, the on and off time of the PMOS tube Q1 is less than 100ns.
In summary, the PMOS transistor driving circuit of the present invention uses the zener diode and the active bleeder circuit to perform switching control on the PMOS transistor, thereby improving the dynamic characteristics of the PMOS transistor as the switching transistor and improving the switching efficiency of the PMOS transistor. The high-current characteristic of the diode and the triode during conduction is adopted to inject and extract charges in the parasitic capacitance of the grid source of the PMOS tube, so that the parasitic capacitance of the grid source of the PMOS tube is rapidly charged and discharged, the switching efficiency of the PMOS tube is improved, the switching loss of the PMOS tube is reduced, and meanwhile, the control complexity of the PMOS tube driving circuit is reduced.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and any simple modification, variation and equivalent structural changes made to the above embodiment according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (6)
1. The design method of the PMOS tube driving circuit adopting the active discharge technology comprises an NPN triode Q2, an NMOS tube Q3, a Schottky diode D2, a capacitor C2, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the grid electrode of the NMOS tube Q3 is connected with one end of the resistor R3, the other end of the resistor R3 is an input end of an external PWM driving signal, the source electrode of the NMOS tube Q3 is grounded, and the drain electrode of the NMOS tube Q3 is connected with one end of the resistor R2; the base electrode of the NPN triode Q2 is connected with the drain electrode of the NMOS tube Q3 through a capacitor C2, the collector electrode of the NPN triode Q2 is connected with the positive output end of an external power supply and the source electrode of the PMOS tube to be driven, and the emitter electrode of the NPN triode Q2 is connected with the other end of the resistor R2 and the grid electrode of the PMOS tube to be driven; the resistor R1 is connected in parallel between the collector and the emitter of the NPN triode Q2, and the resistor R4 is connected in parallel between the grid and the source of the NMOS tube Q3; the anode of the Schottky diode D2 is connected with the emitter of the NPN triode Q2, and the cathode of the Schottky diode D2 is connected with the base of the NPN triode Q2; the method is characterized in that: the method comprises the following steps:
step one, selecting an NPN triode Q2, an NMOS tube Q3 and a Schottky diode D2 with proper types, wherein the specific process is as follows:
step 101, selecting an NPN triode with the amplification factor larger than 100 as an NPN triode Q2;
102, selecting an NMOS tube with current smaller than 10A and drain-source breakdown voltage smaller than or equal to 100V as an NMOS tube Q3;
step 103, selecting a Schottky diode with the rated current smaller than 0.5A and the reverse recovery time smaller than 30ns as a Schottky diode D2;
selecting a resistor R1, a resistor R2, a resistor R3 and a resistor R4 with proper parameters, wherein the specific process is as follows:
step 201, selecting resistance values of a resistor R1 and a resistor R2 between 1kΩ and 10kΩ;
step 202, according to the formulaSelecting the resistance value of a resistor R3, wherein Vcc is the power supply voltage of a PWM control chip in a switching power supply circuit where a PMOS tube to be driven is positioned, I max The peak current of a PWM control chip in a switching power supply circuit where a PMOS tube to be driven is located, t is the switching delay time of an NMOS tube Q3, and C is the parasitic capacitance between the grid electrode and the source electrode of the NMOS tube Q3;
step 203, selecting the resistance value of the resistor R4 according to the formula r4=100deg.r3;
step three, selecting a capacitor C2 with proper parameters, wherein the specific process is as follows:
step 301, according to the formulaCalculating collector current i of NPN triode Q2 in saturated conduction C(Q2) Wherein beta is (Q2) Is the amplification factor of NPN triode Q2, V C2 Steady state value and V for charging capacitor C2 when PMOS tube Q1 is turned on C2 ＝V D1 -V D2 ，V D1 Is the voltage stabilizing value of the voltage stabilizing diode D1, V D2 Is the voltage across the schottky diode D2;
step 302, according to the formulaCalculation from NMOS tube Q3 to cut-offThe parasitic capacitance C1 between the grid electrode and the source electrode of the PMOS tube to be driven is discharged to the time t required by the voltage of the two ends to be equal to zero off1 Wherein V is i The input voltage of the switching power supply circuit where the PMOS tube to be driven is positioned;
step 303, according to the formulaSelecting the capacitance value of the capacitor C2;
step four, connecting an NPN triode Q2, an NMOS tube Q3, a Schottky diode D2, a capacitor C2, a resistor R1, a resistor R2, a resistor R3 and a resistor R4 to form a PMOS tube rapid switch driving circuit; the specific process is as follows:
step 401, connecting a gate of an NMOS transistor Q3 with one end of a resistor R3, using a lead wire led out from the other end of the resistor R3 as an input end of an external PWM driving signal, grounding a source of the NMOS transistor Q3, and connecting a drain of the NMOS transistor Q3 with one end of a resistor R2;
step 402, connecting a base electrode of an NPN triode Q2 with one end of a capacitor C2, connecting the other end of the capacitor C2 with a drain electrode of an NMOS tube Q3, connecting a collector electrode of the NPN triode Q2 with an anode output end of an external power supply and a source electrode of a PMOS tube to be driven, and connecting an emitter electrode of the NPN triode Q2 with the other end of a resistor R2 and a grid electrode of the PMOS tube to be driven;
step 403, one end of a resistor R1 is connected with a collector of an NPN transistor Q2, the other end of the resistor R1 is connected with an emitter of the NPN transistor Q2, one end of a resistor R4 is connected with a gate of an NMOS transistor Q3, and the other end of the resistor R4 is connected with a source of the NMOS transistor Q3;
step 404, connecting the anode of the schottky diode D2 with the emitter of the NPN transistor Q2, and connecting the cathode of the schottky diode D2 with the base of the NPN transistor Q2;
step 405, connect the anode of the zener diode D1 with the drain of the NMOS transistor Q3, and connect the cathode of the zener diode D1 with the emitter of the NPN transistor Q2.
2. The method for designing the PMOS transistor driving circuit by using the active bleeder technique according to claim 1, wherein: the LED further comprises a zener diode D1, wherein the anode of the zener diode D1 is connected with the drain electrode of the NMOS tube Q3, and the cathode of the zener diode D1 is connected with the emitter electrode of the NPN triode Q2.
3. The method for designing a PMOS transistor driving circuit according to claim 1 or 2, wherein the method is characterized in that: the model of the NPN triode Q2 is ZTX651.
4. The method for designing a PMOS transistor driving circuit according to claim 1 or 2, wherein the method is characterized in that: the model of the NMOS tube Q3 is IRF510.
5. The method for designing a PMOS transistor driving circuit according to claim 1 or 2, wherein the method is characterized in that: the schottky diode D2 is of the type SS14.
6. The method for designing the PMOS transistor driving circuit by using the active bleeder technique according to claim 1, wherein: in step 302, the parasitic capacitance C1 between the gate and the source of the PMOS transistor to be driven has a value of 1000 pF-2000 pF.
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| CN108768355B (en) * | 2018-04-10 | 2022-08-19 | 上海空间电源研究所 | Quick-conduction Pmos tube driving circuit and implementation method |
| CN109194319B (en) * | 2018-08-13 | 2022-07-05 | 北方电子研究院安徽有限公司 | PMOS tube driving circuit |
| CN109525206B (en) * | 2018-12-28 | 2021-12-28 | 中科特思信息技术(深圳)有限公司 | Real-time monitoring protection circuit of radio frequency power amplifier |
| CN112436720B (en) * | 2021-01-27 | 2021-04-09 | 上海南麟电子股份有限公司 | NMOS power tube driving circuit |
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