CN107528569A - A kind of controllable power supply circuit of sequential - Google Patents
A kind of controllable power supply circuit of sequential Download PDFInfo
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- CN107528569A CN107528569A CN201711005559.3A CN201711005559A CN107528569A CN 107528569 A CN107528569 A CN 107528569A CN 201711005559 A CN201711005559 A CN 201711005559A CN 107528569 A CN107528569 A CN 107528569A
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- 230000003111 delayed effect Effects 0.000 claims abstract description 9
- 230000000630 rising effect Effects 0.000 claims abstract description 7
- 230000005611 electricity Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00293—Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Logic Circuits (AREA)
Abstract
It is sequentially provided with the invention discloses a kind of controllable power supply circuit of sequential from input to output：Input circuit, input signal and output services voltage are received to delay circuit；Delay circuit, receive the operating voltage and export time delayed signal to output circuit；Output circuit, reception delay signal simultaneously export controllable electric power signal；It is characterized in that：The delay circuit includes the first delay circuit and the second delay circuit, first delay circuit enters line delay to the rising edge of signal and produces the time delayed signal that a delay input quickly exports, second delay circuit enters line delay to signal trailing edge and produces a time delayed signal for rapidly inputting delay output, has the function that control sequential with this.
Description
Technical field
The invention belongs to vehicle electric field, more particularly to a kind of controllable power supply circuit of sequential.
Background technology
At present in automobile electronic controller product, being substantially all needs to carry out different sequential to the power supply of integrated circuit
Control, for example, by different electrifying timing sequences, is being power-up in the delay time section of startup, can be to the inside electricity of integrated circuit
Road is initialized under different sequential so as to avoid integrated circuit from breaking down.It is possible thereby to make its safe, economical, durable and
Normal work, is monitored to power supply and control becomes particularly important.
The content of the invention
, can be in the rising of input signal the technical problem to be solved in the present invention is to provide a kind of controllable control circuit of sequential
Edge and trailing edge carry out the delay of different sequential, produce new sequential, and the present invention solves the technical problem in the following way：
A kind of controllable power supply circuit of sequential, it is sequentially provided with from input to output：
Input circuit, input signal and output services voltage are received to delay circuit；
Delay circuit, receive the operating voltage and export time delayed signal to output circuit；
Output circuit, reception delay signal simultaneously export controllable electric power signal；
The delay circuit includes the first delay circuit and the second delay circuit, and first delay circuit is to the upper of signal
The time delayed signal quickly exported along the one delay input of line delay and generation is entered is risen, second delay circuit is to signal trailing edge
Enter line delay and produce the time delayed signal that a delay output is rapidly input, control sequential is haveed the function that with this.
As a kind of preferred embodiment of the present invention, the input circuit includes first be connected in parallel with input signal
Input circuit and the second input circuit, first input circuit include resistance R1, resistance R2 and triode Q1, triode Q1
Emitting stage be connected with dc source Vcc, base stage is connected with resistance R1 output ends, and R1 inputs are then connected with input signal, electricity
Resistance R2 one end is connected to dc source Vcc, and the other end is connected between Q1 base stages and resistance R1, and Q1 colelctor electrode is defeated as first
The output end for entering circuit is connected with the input of the first delay circuit.
Second input circuit includes FET Q7, triode Q3, resistance R6, resistance R7, resistance R10, Q3 base
Pole is connected with resistance R6 output end, and resistance R6 input is connected with input signal, Q3 emitting stage and dc source Vcc phases
Even, resistance R7 one end is connected to dc source Vcc, and the other end is connected between Q3 base stage and resistance R6, Q7 grid with it is defeated
Enter signal to be connected, source ground, second input circuit prolongs using Q3 colelctor electrode or Q7 drain electrode as output end and with second
When circuit input be connected.
As a kind of preferred embodiment of the present invention, the output circuit includes the first output circuit and the second output electricity
Road, first output circuit include FET Q4, resistance R4, resistance R5, triode Q2, Q4 source ground, grid with
First delay circuit output end connects, and drain electrode is connected with R4 one end, and the R4 other end is connected with Q2 base stage, Q2 emitting stage
It is connected with dc source Vcc, R5 one end is connected to Vcc, and the other end is connected between Q2 base stages and resistance R4, and Q2 current collection is extremely
Output end output voltage Vcc1.
Second output circuit includes resistance R8, resistance R9, triode Q5, FET Q6, Q6 grid and second
The output end of delay circuit is connected, source ground, and drain electrode is connected with resistance R8 input, the resistance R8 output end and three poles
Pipe Q5 base stage connection, Q5 emitting stage are connected with dc source Vcc, and resistance R9 one end and Q5 colelctor electrode are as output end
Output voltage Vcc2.
As a kind of preferred embodiment of the present invention, first delay circuit includes the electric capacity C1 and resistance being in parallel
R3, electric capacity C1 one end ground connection, the other end are connected to the output end of first input circuit, and the resistance R3 mono- is terminated
Ground, the other end are connected to the input of the first output circuit；
Second delay circuit includes the electric capacity C2 that is serially connected and resistance R10, the resistance R10 inputs with it is described
Second input circuit output end is connected, and output end is connected with described electric capacity C2 one end, the electric capacity C2 other ends ground connection, output end
By being drawn between the electric capacity C2 and resistance R10 and being connected to the input of the second output circuit.
As a kind of preferred embodiment of the present invention, described triode Q1, Q2, Q3, Q5 are PNP type triode, described
FET Q4, Q6, Q7 are N-channel FET.
The present invention operates as follows:
The delay of signal trailing edge：When input signal is low level, Q1 conductings, Vcc charges to electric capacity C1, and electric capacity C1 is defeated
Going out high level turns on Q4 and exports a low level in drain electrode, and the low level inputs Q2 base stage, and Q2 is turned on and in Q2 collection
Electrode exports an output voltage Vcc1 for being approximately equal to Vcc, and when input signal is high level, Q1 cut-offs, electric capacity C1 passes through electricity
Resistance R3 is discharged, and when electric capacity C1 voltage is decreased below Q4 threshold voltage Vgs, Q4 cut-offs, at the same time Q2 is also cut
Only, output voltage Vcc1 is low level, and the speed that electric capacity discharges is adjusted by controlling electric capacity C1 capacitance with resistance R3 resistance
Degree, enters line delay to signal trailing edge, thus reaches the purpose that sequential regulation is carried out to input signal.
The delay of signal rising edge：When input signal is low level, triode Q3 conductings, Vcc is by resistance R10 to electricity
Hold C2 to be charged, when the voltage VG2 on electric capacity C2 is higher than FET Q6 threshold voltage Vgs, FET Q6 conductings,
Low level and output triode Q5 base stages are produced in drain electrode, triode Q5 conductings, one and input voltage are exported in colelctor electrode
Similar voltage vcc 2, when incoming level is a high level, triode Q3 cut-offs, FET Q7 conductings, FET
A low level value is exported at Q7 drain electrode to FET Q6 grid, ends FET Q6, triode Q5 is also therewith
Cut-off, output voltage Vcc2 is low level, is controlled by controlling resistance R10 resistance with electric capacity C2 capacitance on electric capacity C2
Rate of voltage rise, line delay is entered to signal rising edge, to reach the effect of regulation sequential.
To sum up, power supply circuit used in the present invention, the delay of signal rising edge and the delay of signal trailing edge are provided simultaneously with
Effect, so as to carry out the control of different sequential to the power supply of integrated circuit.
Brief description of the drawings
Fig. 1 is the schematic diagram of the present invention；
Fig. 2 is the circuit diagram of the present invention；
Fig. 3 is the work wave schematic diagram of the present invention.
Embodiment
It is preferred embodiment below, and become apparent from intactly illustrating the present invention with reference to accompanying drawing：
As shown in figure 1, the power supply circuit that a kind of sequential is controllable, including one rapidly inputs delay output circuit and one is prolonged
When input quick output circuit, it is described to rapidly input delay output circuit and include the first input circuit successively from output is input to,
First delay circuit, the first output circuit.
As shown in Fig. 2 wherein, the first input circuit includes resistance R1, resistance R2 and triode Q1, triode Q1's
Emitting stage is connected with dc source Vcc, and base stage is connected with resistance R1 one end, and R1 inputs are connected with output signal, resistance R2 mono-
End is connected to Vcc, and the other end is connected between Q1 base stages and resistance R1, the output end of Q1 colelctor electrode as the first input circuit
It is connected with the input of the first delay circuit,
First delay circuit includes electric capacity C1 and resistance R3, and electric capacity C1 is in parallel with resistance R3 and Q1 colelctor electrodes and ground
Between, Q1 colelctor electrode is connected as the output end of the first delay circuit with the input of the first output circuit.
First output circuit includes N-channel FET Q4, resistance R4, resistance R5, triode Q2, Q4 source ground,
Grid and Q1 colelctor electrode connect, drain electrode be connected with R4 one end, the R4 other end is connected with Q2 base stage, Q2 emitting stage and
Dc source Vcc is connected, and the connection of R5 one end and Vcc, the other end are connected between Q2 base stages and resistance R4.Q2 current collection is extremely defeated
Go out to hold output voltage Vcc1.
As shown in figure 3, this rapidly input delay output circuit it is operated as follows, when input signal is low level,
Q1 is turned on, and Vcc charges to electric capacity C1, and electric capacity C1 output high level turns on Q4 and exports a low level, the low electricity in drain electrode
Flat input Q2 base stage, Q2 conductings and the colelctor electrode in Q2 export an output voltage Vcc1 for being approximately equal to Vcc, work as input signal
For high level when, Q1 cut-offs, electric capacity C1 discharged by resistance R3, and electric capacity C1 voltage is decreased below Q4 threshold voltage
Vgs, Q4 end, and Q2 also ends therewith, and output voltage Vcc1 is low level, by controlling electric capacity C1 capacitance and resistance R3 resistance
Value adjusts the speed of electric capacity electric discharge, and the electric capacity velocity of discharge is slower, then the delay time of signal trailing edge is longer, thus reach pair
Input signal carries out the purpose of sequential regulation.
The delay, which inputs quick output device, includes the second input circuit, the second delay circuit, the second output circuit.
Wherein, the second input circuit includes N-channel FET Q7, PNP type triode Q3, resistance R6, resistance R7, resistance
R10, Q3 base stage are connected with resistance R6 one end, and the resistance R6 other end is connected with input signal, Q3 emitting stage and direct current
Power Vcc is connected, and the connection of resistance R7 one end is connected between Q3 base stage and resistance R6 with dc source Vcc, the other end, Q3's
Colelctor electrode is connected with resistance R10 input, and Q7 grid is connected with input signal, source ground, is connected on resistance R10 output
On end, this second can input circuit exported by Q3 colelctor electrode or Q7 drain electrode.
Second delay circuit includes resistance R10 and electric capacity C2, and resistance R10 one end is connected with Q3 colelctor electrode, another
End is connected with electric capacity C2, electric capacity C2 one end ground connection, the output end of the second delay circuit is drawn between resistance R10 and electric capacity C2 simultaneously
It is connected with the input of the second output circuit.
Second output circuit includes resistance R8, resistance R9, PNP type triode Q5, N-channel FET Q6, Q6 grid
Pole is connected with the output end of the second delay circuit, source ground, and drain electrode is connected with resistance R8 input, resistance R8 output
End is connected with triode Q5 base stage, and Q5 emitting stage is connected with dc source Vcc, and resistance R9 one end and Q5 colelctor electrode are made
For output end output voltage Vcc2.
The delay inputs quick output circuit and operated in the following way, when output signal is low level, three-level
Pipe Q3 is turned on, and dc source is charged by resistance R10 to electric capacity C2, when the voltage VG2 on electric capacity C2 is higher than FET
During Q6 threshold voltage Vgs, FET Q6 conductings, and low level and output triode Q5 base stages, three poles are produced in drain electrode
Pipe Q5 is turned on, and a voltage vcc 2 essentially identical with input voltage is exported in colelctor electrode.
When incoming level is a high level, triode Q3 cut-offs, FET Q7 conductings, FET Q7 drain electrode
Place's one low level value of output ends FET Q6, triode Q5 also ends therewith, exports to FET Q6 grid
Voltage vcc 2 is low level.
Electric capacity C2 charging rate, electric capacity charging speed are controlled by controlling resistance R10 resistance with electric capacity C2 capacitance
The delay time of the more slow then signal rising edge of degree is longer, to reach the effect of regulation sequential.
To sum up, power supply circuit used in the present invention, output delay and the effect of input time delay are provided simultaneously with, so as to collection
Power supply into circuit carries out the control of different sequential.
Although the embodiment of the present invention is the foregoing described, it will be appreciated by those of skill in the art that this is only
For example, protection scope of the present invention is to be defined by the appended claims, those skilled in the art without departing substantially from
On the premise of the principle and essence of the present invention, various changes or modifications can be made to these embodiments, but these changes and
Modification each falls within protection scope of the present invention.
Claims (5)
1. a kind of controllable power supply circuit of sequential, it is sequentially provided with from input to output：
Input circuit, input signal and output services voltage are received to delay circuit；
Delay circuit, receive the operating voltage and export time delayed signal to output circuit；
Output circuit, reception delay signal simultaneously export controllable electric power signal；
It is characterized in that：The delay circuit includes the first delay circuit and the second delay circuit, first delay circuit pair
The rising edge of signal enters line delay and produces the time delayed signal that a delay input quickly exports, and second delay circuit is to letter
Number trailing edge enters line delay and produces the time delayed signal that a delay output is rapidly input, and has the function that control sequential with this.
2. sequential controllable time delay circuit according to claim 1, it is characterised in that：The input circuit includes believing with input
Number the first input circuit and the second input circuit that are connected in parallel, first input circuit include resistance R1, resistance R2 and
Triode Q1, triode Q1 emitting stage are connected with dc source Vcc, and base stage is connected with resistance R1 output ends, and R1 inputs are then
It is connected with input signal, resistance R2 one end is connected to dc source Vcc, and the other end is connected between Q1 base stages and resistance R1, Q1
Colelctor electrode be connected as the output end of the first input circuit with the input of the first delay circuit；
Second input circuit include FET Q7, triode Q3, resistance R6, resistance R7, resistance R10, Q3 base stage with
Resistance R6 output end is connected, and resistance R6 input is connected with input signal, and Q3 emitting stage is connected with dc source Vcc,
Resistance R7 one end is connected to dc source Vcc, and the other end is connected between Q3 base stage and resistance R6, and Q7 grid and input are believed
Number it is connected, source ground, second input circuit is using Q3 colelctor electrode or Q7 drain electrode as output end and electric with the second delay
The input on road is connected.
3. sequential controllable time delay circuit according to claim 1, it is characterised in that：The output circuit includes the first output
Circuit and the second output circuit, first output circuit include FET Q4, resistance R4, resistance R5, triode Q2, Q4's
Source ground, grid are connected with the first delay circuit output end, and drain electrode is connected with R4 one end, the R4 other end and Q2 base stage
Be connected, Q2 emitting stage is connected with dc source Vcc, and R5 one end is connected to dc source Vcc, the other end be connected to Q2 base stages and
Between resistance R4, Q2 current collection extremely output end output voltage Vcc1；
Second output circuit includes resistance R8, resistance R9, triode Q5, FET Q6, Q6 grid and the second delay
The output end of circuit is connected, source ground, and drain electrode is connected with resistance R8 input, the resistance R8 output end and triode Q5
Base stage connection, Q5 emitting stage is connected with dc source Vcc, and resistance R9 one end and Q5 colelctor electrode are as output end output
Voltage vcc 2.
4. sequential controllable time delay circuit according to claim 1, it is characterised in that：First delay circuit is included mutually simultaneously
The electric capacity C1 of connection and resistance R3, electric capacity C1 one end ground connection, the other end are connected to the output end of first input circuit, institute
Resistance R3 one end ground connection is stated, the other end is connected to the input of the first output circuit；
Second delay circuit includes the electric capacity C2 and resistance R10 being serially connected, the resistance R10 inputs and described second
Input circuit output end is connected, and output end is connected with described electric capacity C2 one end, and the electric capacity C2 other ends ground connection, output end is by institute
State the input drawn between electric capacity C2 and resistance R10 and be connected to the second output circuit.
5. the sequential controllable time delay circuit according to Claims 2 or 3 or 4, it is characterised in that：The triode Q1, Q2,
Q3, Q5 are PNP type triode, and described FET Q4, Q6, Q7 are N-channel FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711005559.3A CN107528569B (en) | 2017-10-25 | 2017-10-25 | Time sequence controllable power supply circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711005559.3A CN107528569B (en) | 2017-10-25 | 2017-10-25 | Time sequence controllable power supply circuit |
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| CN107528569A true CN107528569A (en) | 2017-12-29 |
| CN107528569B CN107528569B (en) | 2024-03-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711005559.3A Active CN107528569B (en) | 2017-10-25 | 2017-10-25 | Time sequence controllable power supply circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112713760A (en) * | 2020-12-01 | 2021-04-27 | 北京无线电测量研究所 | Parallel redundant ferrite switch driver |
| CN112803930A (en) * | 2020-12-30 | 2021-05-14 | 合肥市芯海电子科技有限公司 | Edge adjusting circuit, integrated circuit and electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07162284A (en) * | 1993-12-07 | 1995-06-23 | Toshiba Corp | Output buffer circuit |
| US20080290922A1 (en) * | 2007-05-24 | 2008-11-27 | Nanya Technology Corporation | Delay circuit |
| CN101777892A (en) * | 2009-01-13 | 2010-07-14 | 鸿富锦精密工业（深圳）有限公司 | Time delay device |
| CN103326706A (en) * | 2013-05-27 | 2013-09-25 | 上海奔赛电子科技发展有限公司 | Filter circuit of integrated circuit and integrated circuit |
| CN207910746U (en) * | 2017-10-25 | 2018-09-25 | 上海伟世通汽车电子系统有限公司 | A kind of controllable power supply circuit of sequential |
-
2017
- 2017-10-25 CN CN201711005559.3A patent/CN107528569B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07162284A (en) * | 1993-12-07 | 1995-06-23 | Toshiba Corp | Output buffer circuit |
| US20080290922A1 (en) * | 2007-05-24 | 2008-11-27 | Nanya Technology Corporation | Delay circuit |
| CN101777892A (en) * | 2009-01-13 | 2010-07-14 | 鸿富锦精密工业（深圳）有限公司 | Time delay device |
| CN103326706A (en) * | 2013-05-27 | 2013-09-25 | 上海奔赛电子科技发展有限公司 | Filter circuit of integrated circuit and integrated circuit |
| CN207910746U (en) * | 2017-10-25 | 2018-09-25 | 上海伟世通汽车电子系统有限公司 | A kind of controllable power supply circuit of sequential |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112713760A (en) * | 2020-12-01 | 2021-04-27 | 北京无线电测量研究所 | Parallel redundant ferrite switch driver |
| CN112713760B (en) * | 2020-12-01 | 2022-03-04 | 北京无线电测量研究所 | Parallel redundant ferrite switch driver |
| CN112803930A (en) * | 2020-12-30 | 2021-05-14 | 合肥市芯海电子科技有限公司 | Edge adjusting circuit, integrated circuit and electronic device |
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| CN107528569B (en) | 2024-03-08 |
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