CN107527820A - A kind of preparation method of PMOS device - Google Patents
A kind of preparation method of PMOS device Download PDFInfo
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- CN107527820A CN107527820A CN201710716430.7A CN201710716430A CN107527820A CN 107527820 A CN107527820 A CN 107527820A CN 201710716430 A CN201710716430 A CN 201710716430A CN 107527820 A CN107527820 A CN 107527820A
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- 239000000758 substrate Substances 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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Abstract
The invention provides a kind of preparation method of PMOS device, belong to power semiconductor device technology field.The present invention in deep groove structure by introducing gate electrode and the strain dielectric layer located at gate electrode periphery, so as to which semiconductor material regions apply compression strain where flow channel, hole mobility is lifted by compression strain, device hole current in forward conduction is caused to flow through the lower path of conducting resistance, so as to reduce the conducting resistance of device；Simultaneously as drift region produces the transverse electric field of assisted depletion drift region with introducing gate electrode, it is possible to increase device it is reverse pressure-resistant.The present invention compares the preparation technology of existing super-junction structure, avoids the problem of technological requirement difficulty present in multiple extension alignment precision and charge balance control is big, thus has inexpensive and simple to operate advantage, is advantageous to the production of Large scale processes metaplasia.
Description
Technical field
The invention belongs to power semiconductor technologies field, and in particular to a kind of preparation method of PMOS device.
Background technology
Power metal-oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field-
Effect Transistor, MOSFET) two key parameters be breakdown voltage BV and conducting resistance Ron.Due to MOSFET devices
Part belongs to monopole type device, and its breakdown voltage is relevant with drift region thickness and drift doping concentration, and high breakdown voltage needs
Thick drift region and low drift doping concentration, but such that its conducting resistance RonIncrease.Conducting resistance RonWith it is resistance to
Relation be present between pressure BV：Ron∝BV2.5, i.e. the silicon limit.Therefore, as the pressure-resistant increase of device, conducting resistance exponentially increase
Trend, power consumption greatly increase.Especially, conducting resistance is mainly determined by drift zone resistance in typical high voltage MOSFET element.
Therefore while device electric breakdown strength performance is not influenceed by reduce drift zone resistance reduce conducting resistance have it is important
Meaning.Researcher is improved based on conventional MOS FET structure, and the Chen Xing academicians et al. that assist propose longitudinal super-junction structure, by
The P areas being arranged alternately and N areas are introduced in the drift region of conventional MOSFET device using the original lightly doped district of replacement as drift region,
The introducing of transverse electric field causes longitudinal electric field because two dimensional electric field effect from triangle (or trapezoidal profile) is changed into distributed rectangular, from
And breakdown voltage is improved, break the silicon limit, it is Ron ∝ BV to realize the optimized relation between conducting resistance and breakdown voltage1.32, this
The conducting resistance of power MOSFET device and the relation of breakdown voltage are significantly improved, i.e., in enhancing device breakdown voltage property
The conducting resistance of device is also reduced simultaneously.However, realize that the difficulty of high performance power MOS device is still higher at present, first,
For VDMOS device, pressure-resistant more high then longitudinal P Xing Zhu areas and NXing Zhu areas are deeper, and conventional super-junction structure is using repeatedly outer
Prolong, repeatedly inject and anneal and form the alternatively distributed PXing Zhu areas in longitudinal direction and NXing Zhu areas, on the one hand this manufacture craft makes
Need extension and the number of injection many when the PXing Zhu areas and NXing Zhu areas of big depth, cause that technology difficulty is big and cost is high；Separately
On the one hand, it is difficult to be formed high concentration and high density using this manufacture craft (i.e. ZhaiPXing Zhu areas and ZhaiNXing Zhu areas intersects
For), therefore limit the further reduction of device on-resistance.Secondly, the electric property of superjunction devices is to charge imbalance ten
Divide sensitivity, this means that the width and concentration for needing to be precisely controlled PXing Zhu areas and NXing Zhu areas in technique, otherwise causes device electric
Performance degradation is learned, the difficulty of technique is also increased for this point.Furthermore the junction increase of device inside transverse p/n junction, makes
The defects of recovering to be hardened into device body diode reverse, and can exist in applied to high current occasion reliability decrease and
Because transverse p/n junction depletion layer expands the problem of causing conducting resistance to decline.
The content of the invention
The technical problems to be solved by the invention are：It is low and can low on-resistance and height to provide a kind of craft precision requirement
The preparation method of pressure-resistant performance PMOS device.
In order to solve the above-mentioned technical problem, technical scheme provided by the invention is as follows：
A kind of preparation method of PMOS device, including：
Semiconductor base formed with deep slot grid structure is provided, metallizing source, warp are formed on the surface of semiconductor base
Metalized drain is formed after semiconductor base and metalized backside is thinned；It is characterized in that：The step of forming deep slot grid structure is wrapped
Include：
Strain dielectric layer (5), the material tool of the strain dielectric layer (5) are formed in the bottom sidewall and bottom wall of deep trouth (4)
There is compression strain characteristic；Dielectric layer (6) is formed on the surface of the strain dielectric layer (5)；Then the is formed in deep trouth (4) bottom
One gate electrode (71)；The upper surface of the first gate electrode (71) and the upper surface of dielectric layer (6) and strain dielectric layer (5) weight
Close；Formed again in deep trouth (4) positioned at first gate electrode (71), dielectric layer (6) and the oxide layer for straining dielectric layer (5) upper surface
(8)；Deep trouth side wall on the oxide layer (8) forms gate dielectric layer (9)；Then etching oxidation layer (8) is to expose first
Gate electrode (71)；The second gate electrode (72) contacted with the two is formed on first gate electrode (71) and oxide layer (8) again；Most
Spacer medium layer (12) is formed between the second gate electrode (72) and source metal (15) afterwards.
It is further that the concrete operations that strain dielectric layer is formed in the present invention are as follows：
Deoxidation treatment is carried out to substrate under 800~900 DEG C of temperature conditionss, then in 700~760 DEG C of temperature conditionss
Lower one layer of cushion of extension, the extension strain dielectric layer (5) under 600~650 DEG C of temperature conditionss.
It is further there is compression strain characteristic to strain dielectric layer (5), the thickness for straining dielectric layer (5) is small
In its critical thickness.
Be further, in order to prevent body bias effect and it is pressure-resistant when open parasitic triode, the present invention formed it is mutually only
Vertical P+Source region (11) and N+During contact zone (14), by etching N+The upper surface of contact zone (13) is less than P+Source region (11)
Upper surface, and N+The lower surface junction depth of contact zone (14) is more than P+The lower surface junction depth of source region (11) so that source metal
While and P (15)+Source region (11) and NXing Ti areas (9) contact.
It is further that the material of the strain dielectric layer (5) is preferably SiGe.
It is further that the upper surface junction depth of the second gate electrode (72) is less than P in the present invention+The lower surface knot of source region (11)
Deep, the lower surface junction depth of the second gate electrode (72) is more than the lower surface junction depth of NXing Ti areas (10) in the present invention.
It is further to be contacted to prevent from straining dielectric layer (5) with the second gate electrode (72), oxide layer in the present invention
(8) it is respectively greater than thickness and gate dielectric layer (9) of the strain dielectric layer (5) on the inside of deep trouth in deep trouth in the thickness of deep trouth inwall
The thickness of wall.
It is further that, in order to ensure that between grid leak enough voltage can be born, oxide layer (8) is longitudinal along deep trouth in the present invention
The thickness in direction is not less than the thickness of dielectric layer (6).
It is further that, in order that the threshold voltage absolute value for obtaining device is smaller, the strain dielectric layer (5) is in deep trouth
The thickness of wall is more than thickness of the gate dielectric layer (9) in deep trouth inwall.
It is further that the material of the first gate electrode (71) and the second gate electrode (72) is preferably polycrystalline silicon material.
Compared with prior art, the beneficial effects of the present invention are：
(1) has high withstand voltage performance and low on-resistance with PMOS device made from preparation method of the present invention；This hair
It is bright by deep groove structure introduce gate electrode and located at gate electrode periphery strain dielectric layer, due to strain dielectric layer be located at
Can be that semiconductor material regions apply compression stress where flow channel in PMOS device in the flow channel of hole current,
Again because strain dielectric layer has the mobility that compression stress can increase hole, so forming hole accumulation in dielectric layer is strained
Layer and then the resistance for reducing strain dielectric layer, cause device hole current in forward conduction to flow through the lower road of conducting resistance
Footpath, so as to reduce the conducting resistance of device；Simultaneously as drift region produces the horizontal stroke of assisted depletion drift region with introducing gate electrode
To electric field, it is possible to increase device it is reverse pressure-resistant, and then cause device can use higher drift region concentration, so as to reduce device
Conducting resistance.
(2) is avoided existing the invention provides a kind of method for preparing high withstand voltage performance and low on-resistance PMOS device
Have use technological requirement difficulty present in multiple extension alignment precision and charge balance control big in super-junction structure preparation technology
Problem, thus the present invention has inexpensive and simple to operate advantage.
Brief description of the drawings
Fig. 1 is a kind of method flow diagram of PMOS device provided by the invention；
Fig. 2 is the structural representation that PMOS device is made according to technological process provided by the invention；
Fig. 3 provides a kind of concrete technology flow process figure of PMOS device for the present invention；
Wherein, it is according to schematic diagram of the embodiment of the present invention in substrate Epitaxial growth drift region to scheme (3-1)；
Figure (3-2) is the schematic diagram for etching deep trouth on drift region according to the embodiment of the present invention；
It is the schematic diagram according to epitaxial growing strain dielectric layer material of the embodiment of the present invention to scheme (3-3)；
It is the schematic diagram according to dielectric layer deposited material of the embodiment of the present invention to scheme (3-4)；
It is the schematic diagram that grid material is deposited according to the embodiment of the present invention to scheme (3-5)；
Figure (3-6) is to etch to form first gate electrode, dielectric layer and the signal for straining dielectric layer according to the embodiment of the present invention
Figure；
It is the schematic diagram according to deposited oxide layer material of the embodiment of the present invention to scheme (3-7)；
Figure (3-8) is that the schematic diagram to form oxide layer is etched according to the embodiment of the present invention；
It is the schematic diagram according to the thermally grown gate oxide material of the embodiment of the present invention to scheme (3-9)；
Figure (3-10) is the schematic diagram for exposing first gate electrode according to etching oxidation layer of the embodiment of the present invention；
Figure (3-11) is to deposit grid material on first gate electrode (71) and oxide layer (8) according to the embodiment of the present invention
Schematic diagram；
Figure (3-12) is that the schematic diagram to form the second gate electrode and form body area and source region is etched according to the embodiment of the present invention；
It is the schematic diagram that spacer medium layer is deposited according to the embodiment of the present invention to scheme (3-13)；
Figure (3-14) is that the signal to form source contact openings and NSD injections are carried out to porose area is etched according to the embodiment of the present invention
Figure；
It is the schematic diagram that source metal, organic semiconductor device, back face metalization are deposited according to the embodiment of the present invention to scheme (3-15).
In figure：1 is P+Substrate, 2 be P drift area, and 3 be mask layer, and 4 be deep trouth, and 5 be strain dielectric layer, and 6 be medium
Layer, 71 be first gate electrode, and 72 be the second gate electrode, and 8 be oxide layer, and 9 be gate dielectric layer, and 10 be NXing Ti areas, and 11 be P+Source
Area, 12 be spacer medium layer, and 13 be source contact openings, 14 N+Contact zone, 15 be source metal, and 16 be drain metal.
Embodiment
The present invention is described more fully with reference to the accompanying drawings, identical label represents identical or phase in the accompanying drawings
As component or element.
Idea of the invention is to provide a kind of method for preparing strain PMOS device, passes through the stream in device hole current
Strain dielectric layer is introduced in dynamic passage, causes semiconductor material regions where straining the flow channel that dielectric layer is hole current to apply
Pressurize stress under compression, and then improves the mobility in hole.
There is NXing Ti areas 10, NXing Ti areas 10 are located at deep trouth grid both sides or periphery in semiconductor base provided by the invention
Semiconductor substrate surface below, there is P in NXing Ti areas 10+Source region 11 and N+Contact zone 14.
Semiconductor base provided by the invention can have insulating barrier on silicon or silicon upper epitaxial layer structure and remaining appoint
What suitable structure.
The manufacture method of PMOS device of the present invention is described in detail with reference to specific embodiment, as shown in Figure 1
The preparation flow figure of embodiment 1 is provided, including：In P+P drift area 2 is formed on substrate 1 and etches the step for forming deep trouth 4
Suddenly；In the bottom of deep trouth 4 the strain dielectric layer 5, the and of dielectric layer 6 that are distributed from outside to inside are formed through epitaxial growth or deposit, etching
The step of first gate electrode 71；Through depositing, etching the step of oxide layer 8 are formed in deep trouth；In the deep trouth on oxide layer 8
Wall forms the step of gate dielectric layer 9；Anti-carve oxide layer 8 expose first gate electrode 71 and oxide layer 8 and first gate electrode 71 it
On through depositing, etching the step of forming the second gate electrode 72；NXing Ti areas 10 are formed in the P drift area 2 of the both sides of deep trouth 4 and in N
P is formed in Xing Ti areas 10+Source region 11 and N+The step of contact zone 14；And form spacer medium in the upper surface of the second gate electrode 72
The step of layer 12 and deposition source metal, organic semiconductor device and substrate back metallize.
The present invention in the bottom of deep trouth 4 through epitaxial growth or deposit, etching by " forming from outside to inside compared with prior art
The strain dielectric layer 5 of distribution, dielectric layer 6 and first gate electrode 71 " this technological means cause PMOS device to have low electric conduction
Resistance and high withstand voltage performance, and there is inexpensive and simple to operate advantage compared to the existing technique for preparing super-junction structure.
Further illustrated with reference to the making corresponding structural profile illustration of each step of PMOS device illustrated in fig. 3
Manufacture craft of the present invention：
Embodiment：
As shown in figure 3, the specific embodiment of the invention provides a kind of preparation method of PMOS device, comprise the following steps：
Step 1：As shown in figure 3-1, in P+The Epitaxial growth P drift area 2 of substrate 1, then grows field oxide, and carve
Lose the field oxide of active area；The present embodiment backing material is preferably body silicon materials.
Step 2：As shown in figure 3-2, the active area in P drift area 2 etches deep trouth；Manufacture craft of the present invention to deep trouth
It is not limited, can adopts and form deep trouth in any suitable manner.
Step 3：As shown in Fig. 3-3, one layer of SiGe alloy firm of epitaxial growth is as dielectric layer 5 is strained in deep trouth, originally
Invention is not limited to the material and its manufacture craft that strain dielectric layer 5, can use any suitable material and any suitable
Mode formed strain dielectric layer 5；The present embodiment uses CVD epitaxial growing strain dielectric layer 5, and concrete operations are as follows：
Deoxidation treatment is carried out to silicon substrate under 850 DEG C of temperature conditionss, then the extension one under 750 DEG C of temperature conditionss
Layer silicon buffer layer, one layer of SiGe alloy firm of extension under 650 DEG C of temperature conditionss；
Because the lattice constant of SiGe alloys is more than body silicon materials, the epitaxial growth of SiGe alloy firms on body silicon substrate,
The sige material with compression strain characteristic can be then obtained, in order to ensure that sige material has compression strain characteristic, this implementation will
The thickness of SiGe alloy firms is asked to be less than its critical thickness, it can be seen from general knowledge known in this field：The definition of critical thickness is：When
When the growth thickness of SiGe alloy firms is less than a certain specific thicknesses, distortion of lattice can be accommodated by elastic deformation, and when super
When crossing the thickness, all or part of distortion of lattice will be discharged by introducing the form of misfit dislocation in heterojunction boundary, this
One thickness is then the critical thickness of film.
Step 4：As shown in Figure 3-4, in the strain surface deposition dielectric material of dielectric layer 5；In order to realize preferably every
From effect, the material of dielectric layer 6 of the present invention is silica or any suitable high relative dielectric constant material, preferably
Ground, the material of dielectric layer 6 of the present invention include but is not limited to HfO2、Si3N4, high relative dielectric constant material is advantageous to straining
Hole accumulation layer is formed in dielectric layer 5.
Step 5：As in Figure 3-5, grid material is deposited in the bottom of deep trouth 4；Grid material is preferably polysilicon, root
Understood according to this area formula general knowledge：It can be any suitable conductive material.
Step 6：As seen in figures 3-6, semiconductor surface unnecessary strain dielectric layer material, dielectric layer material and grid are removed
Material, etched technique form first gate electrode 71；The present invention is not limited for etching technics, and the present embodiment is carved using dry method
Erosion, the grid material at the top of deep trouth is specially etched first and forms first gate electrode 71, is then stop with first gate electrode 71
Dielectric layer material at the top of etching deep trouth and strain dielectric layer material and then formation dielectric layer 6 and strain dielectric layer 5 in succession, etching
The upper surface for forming dielectric layer 6, strain dielectric layer 5 and first gate electrode 71 is respectively positioned on same plane.
Step 7：As shown in fig. 3 to 7, the deposited oxide layer material in obtained deep trouth 4 is handled through step 6；
Step 8：As shown in figures 3-8, oxide layer materials are anti-carved, remove all oxide layer materials of semiconductor surface, and make
In deep trouth 4 thickness of remaining oxide layer not less than dielectric layer 6 relative to the thickness on deep trouth inwall, with this come ensure grid leak it
Between can bear enough voltage.
Step 9：As shown in figs. 3-9, the gate dielectric layer 9 of the thermally grown layer of deep trouth side wall on oxide layer 8, this
Invention is not limited to the forming method of gate dielectric layer 9, enables to gate dielectric layer comparatively dense using thermally grown.
Step 10：As shown in figs. 3-10, etching removes the oxide layer 8 of middle body, to expose the upper table of first gate electrode
Face or portion of upper surface；The etched oxide layer 8 left should at least blanket dielectric layer 6 and strain dielectric layer 5, to prevent grid leak
Break-through；Due to being influenceed by lithographic accuracy, the etched oxide layer 8 left can cover the portion of upper surface of first gate electrode 71；
Step 11：As shown in Fig. 3-11, the grid material contacted with the two is deposited on first gate electrode 71 and oxide layer 8
Material；Grid material as described above is preferably polysilicon, it can be seen from the formula general knowledge of this area：It can be any suitable conduction material
Material.
Step 12：As shown in Fig. 3-12, etching removes the unnecessary grid material of semiconductor surface, then in deep trouth both sides
NXing Ti areas 10 and P are prepared in drift region+Source region 11, the present invention is to preparing NXing Ti areas 10 and P+The method of source region 11 is not limited,
Any suitable method can be used to realize that specifically, the present embodiment uses phosphonium ion or arsenic ion according to general knowledge known in this field
Injection and then progress high temperature are promoted in semiconductor surface NXing Ti areas 10 formed below, and ion can be used after NXing Ti areas are formed
The doping concentration in injection method regulation NXing Ti areas, is then injected using boron ion low energy, is then handled through short annealing, in N-type
Body surface P formed below+Source region 11.
Step 13：As shown in Fig. 3-13, deposit spacer medium layer material is in the second polysilicon 72 and P+The upper table of source region 11
Face forms spacer medium layer 12, and dielectric layer material is isolated in the present embodiment using boron-phosphorosilicate glass BPSG, BPSG in 800 DEG C of high temperature
There is preferable mobility at~950 DEG C, be widely used as the good interlayer dielectric of semiconductor surface flatness；It is public with reference to this area
Know that general knowledge understands that the material of spacer medium layer is not limited to the present embodiment BPSG, can also be any suitable material.
Step 14：As shown in figs. 3-14, photoetching, etching processing spacer medium layer 12 and source contact openings 13, and using certainly
Alignment carries out N+Contact zone 14 injects, and concrete operations are as follows：
Source contact openings 13 are connect using dry etching or remaining any suitable method, source electrode in the present embodiment
The etching depth of contact hole 13 should be more than P+The junction depth of source region 11, make source metal 15 and P+Source region 11 and NXing Ti areas 9 contact simultaneously,
And then prevent body bias effect and it is pressure-resistant when parasitic triode unlatching；
NSD injections are carried out after completing the etching of source contact openings 13, and the bottom of contact hole 13 is formed N by short annealing+Contact zone 14, and then reduce the contact resistance of body area and source metal.
Step 15：As shown in Fig. 3-15, according to deposit, photoetching, the process sequence of metal material is etched in N+Contact zone 14
And the upper surface of spacer medium layer 12 forms source metal 15；Then substrate thinning is carried out, back face metalization processing forms drain electrode
Metal 16, the operation of the present embodiment are specific as follows：
Before source metal 15 is deposited, BPSG high temperature refluxes are carried out, will not because its reflux temperature is less than knot temperature
Considerable influence is produced to Impurity Distribution；Become mellow and full after backflow at the chamfering of spacer medium layer 12, source metal 15 can be reduced herein
The stress at place；
Deposit source metal 15 is divided to for two steps, first deposits the barrier metal of layer, such as metal Co, metal Ti, with
Improve contact reliability；Then the thicker source metal of sputtering, usual source metal use metal Al.Then to source electrode gold
Belong to layer 14 and carry out photoetching and etching, form the structures such as source Pad, grid Pad；Last organic semiconductor device, and overleaf make metal-drain
16。
Using device architecture made from technique produced above as shown in Fig. 2 including：P+Type substrate 1, in the P+Type substrate 1
The back side there is drain metal 16, in the P+The front of type substrate 1 has P drift area 2, under the surface in P drift area 2
Side has NXing Ti areas 10, has deep trouth 4 in the NXing Ti areas 10, and the deep trouth 4 extends to P through NXing Ti areas 10 and bottom
Type drift region 2, the lower face in the NXing Ti areas 10 of the both sides of deep trouth 4 have adjacent P+Source region 11 and N+Contact zone 14, P+Source region
11 upper surface is higher than the N+The upper surface of contact zone 14, in P+Source region 11 and N+It is connected with the surface of contact zone 14 in
The source metal 15 of fluted body structure, the both ends of source metal 15 extend downwardly and P+The side of source region 11 and N+Contact zone 14
Upper surface is in contact；Characterized in that, in the deep trouth 4 have first gate electrode 71, gate dielectric layer 9, the second gate electrode 72, should
Become dielectric layer 5, dielectric layer 6 and oxide layer 8；Second gate electrode 72 and P+Source region 11 passes through spacer medium layer 12 and source metal 15
It is isolated, the upper surface junction depth of second gate electrode 72 is less than P+The lower surface junction depth of source region 11, second gate electrode 72
Lower surface junction depth be more than the lower surface junction depth in NXing Ti areas 10, the deep trouth inwall of the top periphery of the second gate electrode 72 or both sides
Provided with gate dielectric layer 9, the periphery of the bottom of the second gate electrode 72 or both sides deep trouth inwall are provided with the oxygen being in contact with gate dielectric layer 9
Change layer 8, first gate electrode 71 is located at the underface of the second gate electrode 72 and contacted therewith, the periphery of first gate electrode 71 or two
The deep trouth inwall of side is sequentially provided with strain dielectric layer 5 and dielectric layer 6 from outside to inside, and the material of the strain dielectric layer 5 has pressure
Shrinkage strain characteristic；The lower surface of oxide layer 8 or portion lower surface and strain dielectric layer 5 and the upper surface of dielectric layer 6.
It is further that the upper surface junction depth of the second gate electrode 72 is less than P in the present invention+The lower surface junction depth of source region 11,
The lower surface junction depth of the second gate electrode 72 is more than the lower surface junction depth in NXing Ti areas 10 in the present invention.
It is further to be contacted to prevent from straining dielectric layer 5 with the second gate electrode 72, oxide layer 8 is in depth in the present invention
The thickness of groove inwall is respectively greater than the thickness for straining thickness of the dielectric layer 5 on the inside of deep trouth or gate dielectric layer 9 in deep trouth inwall.
It is further that, in order to ensure to bear between grid leak enough voltage, oxide layer 8 is along deep trouth longitudinal direction side in the present invention
To thickness be not less than dielectric layer 6 thickness.
It is further that, in order that the threshold voltage absolute value for obtaining device is smaller, the strain dielectric layer 5 is in deep trouth inwall
Thickness be more than gate dielectric layer 9 deep trouth inwall thickness.
Describe the principle and characteristic of the present invention in detail with reference to device architecture illustrated in Figure 2：
The forward conduction characteristic of device：
PMOS device provided by the invention connected mode of electrode in forward conduction is：Second gate electrode of PMOS device
72 connect negative potential, and drain metal 16 connects negative potential, the connecting to neutral current potential of source metal 15；
When the negative voltage that first gate electrode 71 applies reaches threshold voltage, close to the side of gate dielectric layer 9 in NXing Ti areas 10
Inversion channel is formed, due to the thinner thickness of gate dielectric layer 9, causes the threshold voltage absolute value of device smaller；Now draining
Under the back bias voltage of metal 16, hole is as carrier from P+Source region 11 passes through in NXing Ti areas 10 inversion channel formed；Due to depth
Groove 4 has the second gate electrode 72, therefore forms hole accumulation layer in dielectric layer 5 is strained, and then reduces in strain dielectric layer 5
Resistance, i.e., by strain the implanting p-type drift region 2 of dielectric layer 5 reach again drain metal 16 formed forward current realize PMOS device
Conducting；The SiGe alloy firms formed due to straining the use of dielectric layer 5 in body silicon Epitaxial growth, and the crystalline substance of SiGe alloy firms
Lattice constant is more than body silicon materials, while the epitaxial growth of SiGe alloys can obtain the SiGe conjunctions of compression strain on body silicon materials substrate
Gold thin film, strain dielectric layer 5 is sitting in PMOS device in the flow passage of more electron currents, and more sons of PMOS device are sky
Cave, compression strain can increase the mobility in hole, so as to reduce the conducting resistance of device.
The reverse blocking voltage of device：
PMOS device provided by the invention connected mode of electrode in reverse blocking is：The drain metal 16 of PMOS device
Connect negative potential, the second gate electrode 72 and the short circuit of source metal 15 and connecting to neutral current potential；
When device is in blocking state, drain metal 16 applies back bias voltage, and P drift area 2 starts to exhaust, due to
In PMOS device introduce deep trouth 4, and in deep trouth 4 introduce first gate electrode 71, when reverse blocking so that P drift area 2 with
First gate electrode 71 produces transverse electric field to assisted depletion P drift area 2 and then improves the reverse pressure-resistant of device so that in phase
Under the conditions of pressure-resistant, device of the present invention can use higher drift region concentration, reduce the conducting resistance of device.
Embodiments of the invention are set forth above in association with accompanying drawing, but the invention is not limited in above-mentioned specific
Embodiment, above-mentioned embodiment is only schematical, rather than restricted.One of ordinary skill in the art exists
Under the enlightenment of the present invention, in the case of present inventive concept and scope of the claimed protection is not departed from, many shapes can be also made
Formula, these are belonged within the protection of the present invention.
Claims (9)
1. a kind of preparation method of PMOS device, including：The semiconductor base formed with deep slot grid structure is provided, semiconductor-based
The surface at bottom forms metallizing source, and metalized drain is formed after semiconductor base and metalized backside is thinned；Its feature exists
In：The step of forming deep slot grid structure includes：
Strain dielectric layer (5) is formed in the bottom sidewall and bottom wall of deep trouth (4), the material of the strain dielectric layer (5) has pressure
Shrinkage strain characteristic；Dielectric layer (6) is formed on the surface of the strain dielectric layer (5)；Then the first grid is formed in deep trouth (4) bottom
Electrode (71)；The upper surface of the first gate electrode (71) overlaps with the upper surface of dielectric layer (6) and strain dielectric layer (5)；Again
Formed in deep trouth (4) positioned at first gate electrode (71), dielectric layer (6) and the oxide layer (8) for straining dielectric layer (5) upper surface；
Deep trouth side wall on the oxide layer (8) forms gate dielectric layer (9)；Then etching oxidation layer (8) is electric to expose the first grid
Pole (71)；The second gate electrode (72) contacted with the two is formed on first gate electrode (71) and oxide layer (8) again；Finally exist
Spacer medium layer (12) is formed between second gate electrode (72) and source metal (15).
2. the preparation method of a kind of PMOS device according to claim 1, it is characterised in that form the specific behaviour of strained layer
Make as follows：Deoxidation treatment is carried out to substrate under 800~900 DEG C of temperature conditionss, then in 700~760 DEG C of temperature conditionss
Lower one layer of cushion of extension, the extension strain dielectric layer (5) under 600~650 DEG C of temperature conditionss.
A kind of 3. preparation method of PMOS device according to claim 1, it is characterised in that the strain dielectric layer (5)
Thickness be less than its critical thickness.
A kind of 4. preparation method of PMOS device according to claim 1, it is characterised in that second gate electrode (72)
Upper surface junction depth be less than P+The lower surface junction depth of source region (11), the lower surface junction depth of second gate electrode (72) are more than N-type
The lower surface junction depth in body area (10),.
5. the preparation method of a kind of PMOS device according to claim 1, it is characterised in that oxide layer (8) is in deep trouth
The thickness of wall be respectively greater than strain dielectric layer (5) deep trouth inwall thickness and gate dielectric layer (9) deep trouth inwall thickness.
6. the preparation method of a kind of PMOS device according to claim 1, it is characterised in that oxide layer (8) is indulged along deep trouth
It is not less than thickness of the dielectric layer (6) in deep trouth inwall to the thickness in direction.
A kind of 7. preparation method of PMOS device according to claim 1, it is characterised in that the strain dielectric layer (5)
It is more than thickness of the gate dielectric layer (9) in deep trouth inwall in the thickness of deep trouth inwall.
8. the preparation method of a kind of PMOS device according to claim 1, it is characterised in that the grid material is polycrystalline
Silicon materials.
9. the preparation method of a kind of PMOS device according to claim 1 to 8, it is characterised in that separate being formed
P+Source region (11) and N+In the operation of contact zone (14), by etching N+The upper surface of contact zone (13) is less than P+Source region
(11) upper surface, and N+The lower surface junction depth of contact zone (14) is more than P+The lower surface junction depth of source region (11) so that source electrode gold
Belong to (15) and P+Source region (11) and NXing Ti areas (9) contact.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040178406A1 (en) * | 2003-03-15 | 2004-09-16 | Chu Jack Oon | Dual strain-state SiGe layers for microelectronics |
| CN1574279A (en) * | 2003-06-13 | 2005-02-02 | 株式会社瑞萨科技 | Semiconductor device |
| CN101147265A (en) * | 2005-06-08 | 2008-03-19 | 夏普株式会社 | Trench MOSFET and method for manufacturing same |
| CN104821333A (en) * | 2014-02-04 | 2015-08-05 | 万国半导体股份有限公司 | Thicker bottom oxide for reduced Miller capacitance in trench metal oxide semiconductor field effect transistor (MOSFET) |
-
2017
- 2017-08-21 CN CN201710716430.7A patent/CN107527820A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040178406A1 (en) * | 2003-03-15 | 2004-09-16 | Chu Jack Oon | Dual strain-state SiGe layers for microelectronics |
| CN1574279A (en) * | 2003-06-13 | 2005-02-02 | 株式会社瑞萨科技 | Semiconductor device |
| CN101147265A (en) * | 2005-06-08 | 2008-03-19 | 夏普株式会社 | Trench MOSFET and method for manufacturing same |
| CN104821333A (en) * | 2014-02-04 | 2015-08-05 | 万国半导体股份有限公司 | Thicker bottom oxide for reduced Miller capacitance in trench metal oxide semiconductor field effect transistor (MOSFET) |
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Application publication date: 20171229 |