CN107507780B - Semiconductor packaging method and semiconductor structure - Google Patents

Semiconductor packaging method and semiconductor structure Download PDF

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Publication number
CN107507780B
CN107507780B CN201710677128.5A CN201710677128A CN107507780B CN 107507780 B CN107507780 B CN 107507780B CN 201710677128 A CN201710677128 A CN 201710677128A CN 107507780 B CN107507780 B CN 107507780B
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lead
chip
pin
pins
lead frame
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CN107507780A (en
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徐振杰
曹周
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Great Team Backend Foundry Dongguan Co Ltd
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Great Team Backend Foundry Dongguan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention discloses a semiconductor packaging method and a semiconductor structure, wherein the semiconductor packaging method comprises the following steps: s10, providing a lead frame, wherein the lead frame is provided with a first surface and a second surface which are opposite, performing half-etching treatment on the first surface, and forming a first half-etching area, at least one L-shaped first lead and a plurality of pins on the first surface; s20, performing insulation treatment on the first surface subjected to the half etching treatment; s30, welding the chip on the insulated first lead wire and enabling two ends of the first lead wire to be exposed out of the chip, S40, enabling a plurality of pins to be arranged outside the chip in a surrounding mode, welding one end of the metal lead wire with an electrode of the chip, and welding the other end of the metal lead wire with the pins or the first lead wire exposed out of the chip; s50, post-processing the lead frame after the metal lead is welded to finish semiconductor packaging; one end of the first lead is electrically connected with one pin. The invention can reduce the packaging area of the product by wiring below the chip so as to manufacture a miniaturized semiconductor structure.

Description

Semiconductor packaging method and semiconductor structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging method and a semiconductor structure.
Background
With the development and application requirements of semiconductors, semiconductor devices are developed in the directions of being light, thin, short and small to realize the development trend of miniaturization of semiconductor devices, which requires a package designer to utilize the package space to the maximum extent and reduce the product size. In the conventional semiconductor device, as shown in fig. 1, since the chip 2 ' needs to be insulated from the lead frame 1 ', the lead frame 1 ' cannot pass through the lower part of the chip 2 ', and must surround the chip 2 ', which results in a larger packaging area of the product. For some semiconductor devices having to wire the wires under the chip, the multi-layer PCB is usually used to replace the lead frame in the prior art, and the manufacturing cost of the semiconductor device is very high due to the complex processing of the multi-layer PCB and the price of the multi-layer PCB is much higher than that of the lead frame.
Disclosure of Invention
An object of the present invention is to provide a semiconductor packaging method to make a miniaturized semiconductor structure.
Another object of the present invention is to provide a semiconductor structure with a small package area.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a semiconductor packaging method is provided, including the steps of:
s10, providing a lead frame, wherein the lead frame is provided with a first surface and a second surface which are opposite, the first surface is subjected to half etching treatment, a first half etching area and a first non-etching area are formed on the first surface, and the first non-etching area comprises at least one L-shaped first lead and a plurality of pins;
s20, performing insulation treatment on the first surface subjected to the half etching treatment;
s30, bonding a chip on the insulated first lead and exposing two ends of the first lead to the chip,
s40, arranging the pins around the chip, welding one end of a metal wire with the electrode of the chip, and welding the other end of the metal wire with the pins or the first lead exposed out of the chip;
s50, post-processing the lead frame after the metal lead is welded to finish semiconductor packaging;
wherein one end of the first lead is electrically connected to one of the pins.
As a preferred solution of the semiconductor packaging method, the first non-etching region further includes a passive component seat, the pins include a first pin and a second pin, the first pin is formed at two opposite ends of the lead frame, and the second pin is formed between the passive component seat and the chip;
step S40 further includes: and welding a passive element on the passive element seat subjected to the insulation treatment.
As a preferable scheme of the semiconductor packaging method, a plurality of second leads are further formed on the first surface, the second leads are adjacent to the end parts of the lead frame, and the first leads are located between the second pins and the second leads.
As a preferable scheme of the semiconductor packaging method, the step S20 specifically includes: and coating an insulating material on the first surface, so that the insulating material covers the first half-etching area and the area of the first lead used for mounting the chip.
As a preferable scheme of the semiconductor packaging method, the step S50 specifically includes the following steps:
s51, injecting an epoxy resin packaging material to the first surface;
s52, performing half etching on the second surface;
and S53, performing insulation treatment on the second surface.
As a preferable aspect of the semiconductor packaging method, the second surface includes a first region to be etched and a second region opposite to the pin;
step S52 specifically includes: and performing half etching on the first area, and forming a second half etching area on the second surface to separate a plurality of pins, a first lead and a second lead and a plurality of second leads on the periphery of the chip.
As a preferable scheme of the semiconductor packaging method, the step S53 specifically includes: and coating an insulating material on the second surface, so that the insulating material completely covers the second half-etched region.
On the other hand, a semiconductor structure manufactured by the semiconductor packaging method is also provided, and comprises the following components:
the lead frame is provided with a first surface and a second surface which are opposite, pins and leads are formed on the lead frame through etching, the leads comprise a first lead and a second lead, the first lead is L-shaped, the pins comprise a first pin and a second pin, the first pins are arranged at two opposite ends of the lead frame at intervals, and one end of each lead is electrically connected with the first pin or the second pin;
the chip is welded on the first lead, two ends of the first lead along the length direction of the first lead are exposed out of the chip, a first insulating layer is arranged between the chip and the first lead, and an electrode on the chip is electrically connected with the corresponding pin or the corresponding lead through a metal wire.
As a preferable mode of the semiconductor structure, the semiconductor structure further includes a passive component soldered to the first surface, the second pin is disposed between the passive component and the chip, the second lead is adjacent to an end portion of the lead frame, and the chip is located between the second pin and the second lead.
As a preferable scheme of the semiconductor structure, the first surface is encapsulated with an epoxy resin layer, and the chip, the leads and the passive element are all sealed in the epoxy resin layer;
the second surface is coated with a second insulating layer.
The invention has the beneficial effects that: the chip is welded above the first lead, and the chip is electrically connected with the first lead through the metal lead, which is equivalent to wiring below the chip, so that the packaging area of the product can be reduced, and a miniaturized semiconductor structure can be manufactured. Compared with the prior art, the length of the lead can be shortened, and the influence on the use performance of the semiconductor structure caused by the cross contact of the lead and other leads is avoided.
Drawings
Fig. 1 is a schematic diagram of an internal structure of a conventional semiconductor structure.
Fig. 2 is a flowchart of a semiconductor packaging method according to an embodiment of the invention.
Fig. 3a is a schematic diagram of a first surface structure of a lead frame after a first surface of the lead frame is half-etched according to an embodiment of the invention.
FIG. 3b is a schematic view of the direction A-A in FIG. 3 a.
Fig. 4a is a schematic view of a first surface structure of a lead frame after a first surface insulation treatment according to an embodiment of the invention.
FIG. 4B is a schematic view of the direction B-B of FIG. 4 a.
Fig. 5a is a schematic diagram of a first surface structure of a lead frame after a chip and a passive component are bonded to the first surface of the lead frame according to an embodiment of the invention.
FIG. 5b is a schematic view along line C-C of FIG. 5 a.
Fig. 6a is a schematic view of a first surface structure of a lead frame after metal wires are bonded to the first surface of the lead frame according to an embodiment of the invention.
FIG. 6b is a schematic view of FIG. 6a taken along line D-D.
Fig. 7a is a schematic view of a first surface structure of a lead frame after molding an encapsulating material on the first surface thereof according to an embodiment of the invention.
FIG. 7b is a schematic view of the direction E-E of FIG. 7 a.
Fig. 8a is a schematic diagram of a second surface structure of a lead frame after a first surface of the lead frame is injected with an encapsulating material and a second surface of the lead frame is half-etched according to an embodiment of the invention.
FIG. 8b is a schematic view of FIG. 8a taken along direction F-F.
Fig. 9a is a schematic diagram of a second surface structure of a lead frame after the second surface is half-etched and subjected to an insulation treatment according to an embodiment of the invention.
FIG. 9b is a schematic view of the direction G-G of FIG. 9 a.
Fig. 10 is a schematic structural diagram of a semiconductor structure according to an embodiment of the invention.
In fig. 1:
1', a lead frame; 2', and a chip.
In FIGS. 2 to 10:
1. a lead frame; 11. a first half-etched region; 12. a second half-etched region; 21. a first lead; 22. A second lead; 31. a first pin; 32. a second pin; 4. a chip; 5. a metal wire; 6. a passive component mount; 7. a passive element; 8. a first insulating layer; 9. an epoxy resin layer; 10. a second insulating layer.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
In the description of the present invention, it is to be understood that the terms "inside", "outside", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "fixed" is to be understood broadly, e.g. as being fixedly attached, detachably attached, or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the word "over" a first feature or feature in a second feature may include the word "over" or "over" the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature "under" a second feature may include a first feature that is directly under and obliquely under the second feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
As shown in fig. 2 to 9b, an embodiment of the invention provides a semiconductor packaging method, including the following steps:
s10, providing a lead frame 1, wherein the lead frame 1 is provided with a first surface and a second surface which are opposite, the first surface is subjected to half etching treatment, a first half etching area 11 and a first non-etching area are formed on the first surface, and the first non-etching area is provided with at least one L-shaped first lead 21 and a plurality of pins;
s20, performing insulation treatment on the first surface subjected to the half etching treatment;
s30, soldering the chip 4 on the insulated first lead 21 and exposing the two ends of the first lead 21 to the chip 4;
s40, looping the pins outside the chip 4, and welding one end of the metal wire 5 to the electrode of the chip 4, and welding the other end to the pins or the first leads 21 exposed from the chip;
s50, post-processing the lead frame 1 after the metal lead 5 is welded, and completing semiconductor packaging;
wherein one end of the first lead 21 is electrically connected to one of the pins.
In this embodiment, the first surface of the lead frame 1 is half-etched to form at least one L-shaped first lead 21 and a pin on the first surface, where the first lead 21 is equivalent to an extension of the pin, and after the first surface is coated with an insulating layer, the chip 4 soldered on the first lead 21 is insulated from the first lead 21, and both ends of the first lead 21 are exposed out of the chip 4, so that one electrode on the chip 4 is electrically connected to the first lead 2 through the metal wire 5, compared with the prior art, the length of the lead 5 can be shortened, and the influence on the usability of the semiconductor structure due to the cross contact between the lead 5 and other leads is avoided; the chip 4 in this embodiment is soldered on the first lead 21, and the chip 4 is electrically connected to the first lead 21 through the metal wire 5, which is equivalent to wiring under the chip 4, so that the package area can be reduced, and a miniaturized semiconductor structure can be obtained.
In the present embodiment, the shape of the first lead 21 is not limited to the L shape, and may be a T shape, an arc shape, or the like as long as it satisfies the supporting chip 4.
In step S10, after the first surface is half-etched, the first non-etched region further includes a passive component seat 6, where the pins include a first pin 31 and a second pin 32, the first pin 31 is formed at two opposite ends of the lead frame 1, the second pin 32 is formed between the passive component seat 6 and the chip 4, and when a corresponding electrode on the chip 4 is electrically connected to the pin through a metal wire 5, the length of the metal wire 5 may be shortened, and the package area of the product may be reduced.
Step S40 further includes: and welding a passive element 7 on the passive element seat 6 subjected to the insulation treatment. The passive element 7 refers to a circuit element that does not affect the basic characteristics of the signal but only allows the signal to pass through without being changed, such as a resistor, a capacitor, an inductor, a ceramic oscillator, a crystal oscillator, a transformer, and the like.
A plurality of second leads 22 are further formed on the first surface, the second leads 22 are adjacent to the end portions of the lead frame 1, and the first leads 21 are located between the second pins 32 and the second leads 22, so that the metal wires 5 can be conveniently welded, and the crossing among the metal wires 5 can be avoided.
Step S20 specifically includes: applying an insulating material to the first surface such that the insulating material covers the first half-etched region 11 and the region of the first lead 21 for mounting the chip 4, and completely insulating the chip 4 and the first lead 21 located below the chip 4. Wherein the subsequent steps can be performed after the insulating material is cured.
Step S50 specifically includes the following steps:
s51, injecting an epoxy resin packaging material to the first surface;
s52, performing half etching on the second surface;
and S53, performing insulation treatment on the second surface to obtain the semiconductor structure.
In this embodiment, the second surface includes a first region to be etched and a second region opposite to the pin; the second region is the second non-etched region.
Wherein, step S52 specifically includes: and performing half etching on the first area, and forming a second half-etched area 12 on the second surface to separate a plurality of pins, a plurality of first leads 21 and second leads 22 and a plurality of second leads 22 on the periphery of the chip 4.
Step S53 specifically includes: an insulating material is applied to the second surface such that the insulating material completely covers the second half-etched region 12.
In this embodiment, the following steps are required to be performed after the second surface is coated with the insulating material and cured:
s54, electroplating;
and S55, separating into single particles.
Step S54 and step S55 are conventional in the art, and are not described herein again.
The conductor packaging structure manufactured by the method of the embodiment has a small packaging area so as to adapt to the development trend of miniaturization of semiconductor devices. Compared with the traditional semiconductor structure adopting the base island to support the chip, the packaging area of the conductor packaging structure of the embodiment can be reduced by 20-30%.
As shown in fig. 10, an embodiment of the present invention further provides a semiconductor structure manufactured by the semiconductor packaging method according to the above embodiment, including: the lead frame 1 is provided with a first surface and a second surface which are opposite, pins and leads are formed on the lead frame 1 through etching, the leads comprise a second lead 22 and an L-shaped first lead 21, the pins comprise a first pin 31 and a second pin 32, the first pin 31 is arranged at two opposite ends of the lead frame 1 at intervals, and one end of each lead is electrically connected with the first pin 31 or the second pin 32; the chip 4 is soldered on the first lead 21, two ends of the first lead 21 along the length direction thereof are exposed out of the chip 4, a first insulating layer 8 is arranged between the chip 4 and the first lead 21, and an electrode on the chip 4 is electrically connected with the corresponding pin or the lead through a metal wire 5. Compared with the prior art, the semiconductor structure of the embodiment cancels the design of a base island, the L-shaped first lead 21 and the corresponding pin are integrally connected and molded in an etching manner, the chip 4 is welded on the first lead 21 after the insulating layer 8 is coated on the first lead 21, and meanwhile, two ends of the first lead 21 are exposed out of the chip 4, the electrode which is originally required to be electrically connected with the corresponding pin on the chip 4 can be electrically connected with the first lead 21 exposed out of the chip 4 through the metal wire 5, that is, the electrode on the chip 4 is electrically connected with the corresponding pin through the first lead 21, so that the connection length of the metal wire 5 can be shortened, the packaging area of the semiconductor structure can be reduced, and the influence on the use performance of the semiconductor structure caused by the cross contact of a plurality of metal wires 5 can be avoided.
The semiconductor structure of this embodiment further includes a passive component 7 soldered on the first surface, the second pin 32 is disposed between the passive component 7 and the chip 4, the second lead 22 is adjacent to an end portion of the lead frame 1, and the chip 4 is located between the second pin 32 and the second lead 22, so as to facilitate the electrodes on the chip 4 to be electrically connected to the corresponding pins through the metal wires 5, and further reduce the package area of the product.
The first surface is packaged with an epoxy resin layer 9, the chip 4, the leads and the passive element 7 are all sealed in the epoxy resin layer 9, and meanwhile, the epoxy resin layer 9 can also prevent the chip 4 and the passive element 7 from moving to influence the stability of a product; the second surface is coated with a second insulating layer 10 for sealing the leads exposed at the second surface.
In a specific embodiment of the present invention, as shown in fig. 10, 6 first pins 31 are arranged at intervals at two ends of the lead frame 1 along the width direction thereof, two second pins 32 are arranged between the passive component 7 and the chip 4, and referring to fig. 10, in order from right to left, the second first pin 31 at one end of the lead frame 1 is electrically connected to the first lead 21, that is, one end of the first lead 21 along the length direction thereof is electrically connected to the first pin 31, and the other end extends to the end exposed to the chip 4 and close to the lead frame 1 along the length direction thereof; in order from right to left, the two second leads 22 are electrically connected to the first pin 31 on the right, specifically, one end of the second lead 22 along the length direction thereof is electrically connected to the corresponding first pin 31, the other end extends to the width direction of the lead frame 1 to be close to the first lead 21, the chip 4 is soldered on the L-shaped first lead 21, and the electrodes on the chip 4 are electrically connected to the corresponding first pin 31, second pin 32, first lead 21 or second lead 22.
The semiconductor structure of the embodiment has a small packaging area, and compared with the semiconductor structure of the same type in the prior art, the packaging area can be reduced by 20-30%.
It should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention and the technical principles used, and any changes or substitutions which can be easily conceived by those skilled in the art within the technical scope of the present invention disclosed herein should be covered within the protective scope of the present invention.
The present invention has been described above with reference to specific examples, but the present invention is not limited to these specific examples. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims (9)

1. A semiconductor packaging method, comprising the steps of:
s10, providing a lead frame, wherein the lead frame is provided with a first surface and a second surface which are opposite, the first surface is subjected to half etching treatment, a first half etching area and a first non-etching area are formed on the first surface, the first non-etching area comprises at least one L-shaped first lead and a plurality of pins, the first non-etching area further comprises a passive component seat, the pins comprise a first pin and a second pin, the first pin is formed at two opposite ends of the lead frame, and the second pin is formed between the passive component seat and a chip;
s20, performing insulation treatment on the first surface subjected to the half etching treatment;
s30, soldering the chip on the insulated first lead and exposing two ends of the first lead to the chip;
s40, arranging a plurality of pins around the chip, welding one end of a metal wire with the electrode of the chip, welding the other end of the metal wire with the pins or the first lead exposed out of the chip, and welding a passive element on the passive element seat after insulation treatment;
s50, post-processing the lead frame after the metal lead is welded to finish semiconductor packaging;
wherein one end of the first lead is electrically connected to one of the pins.
2. The semiconductor packaging method according to claim 1, wherein a plurality of second leads are further formed on the first surface, the second leads being adjacent to ends of the lead frame, the first leads being located between the second pins and the second leads.
3. The semiconductor packaging method according to claim 1, wherein the step S20 specifically includes: and coating an insulating material on the first surface, so that the insulating material covers the first half-etching area and the area of the first lead for mounting the chip.
4. The semiconductor packaging method according to claim 2, wherein the step S50 specifically comprises the steps of:
s51, injecting an epoxy resin packaging material to the first surface;
s52, performing half etching on the second surface;
and S53, performing insulation treatment on the second surface.
5. The semiconductor packaging method according to claim 4, wherein the second surface includes a first region to be etched and a second region opposite to the pin;
step S52 specifically includes: and performing half etching on the first area, and forming a second half etching area on the second surface to separate a plurality of pins, a first lead and a second lead and a plurality of second leads on the periphery of the chip.
6. The semiconductor packaging method according to claim 5, wherein the step S53 specifically comprises: and coating an insulating material on the second surface, so that the insulating material completely covers the second half-etched region.
7. A semiconductor structure fabricated by the semiconductor packaging method of any one of claims 1 to 6, comprising:
the lead frame is provided with a first surface and a second surface which are opposite, pins and leads are formed on the lead frame through etching, the leads comprise a first lead and a second lead, the first lead is L-shaped, the pins comprise a first pin and a second pin, the first pins are arranged at two opposite ends of the lead frame at intervals, and one end of each lead is electrically connected with the first pin or the second pin;
the chip is welded on the first lead, two ends of the first lead along the length direction of the first lead are exposed out of the chip, a first insulating layer is arranged between the chip and the first lead, and an electrode on the chip is electrically connected with the corresponding pin or the corresponding lead through a metal wire.
8. The semiconductor structure of claim 7, further comprising a passive component soldered to the first surface, the passive component and the die having the second pin disposed therebetween, the second lead being adjacent an end of the lead frame, and the die being between the second pin and the second lead.
9. The semiconductor structure of claim 8, wherein the first surface is encapsulated with an epoxy layer, and wherein the chip, the leads, and the passive component are all encapsulated within the epoxy layer;
the second surface is coated with a second insulating layer.
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