CN107507759A - Deep trench extension fill process method - Google Patents

Deep trench extension fill process method Download PDF

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Publication number
CN107507759A
CN107507759A CN201710579001.XA CN201710579001A CN107507759A CN 107507759 A CN107507759 A CN 107507759A CN 201710579001 A CN201710579001 A CN 201710579001A CN 107507759 A CN107507759 A CN 107507759A
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CN
China
Prior art keywords
deep trench
gas
reaction chamber
process method
fill process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710579001.XA
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Chinese (zh)
Inventor
伍洲
季伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201710579001.XA priority Critical patent/CN107507759A/en
Publication of CN107507759A publication Critical patent/CN107507759A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

The invention discloses a kind of deep trench extension fill method, and in the filling process, the flow set of carrier gas is 48~52L/Min in reaction chamber, and the flow set of purgative gas is 2.5~3.5L/Min.By adjusting the flow velocity of carrier gas and purge gas in reaction chamber, process gas is set fully to be spread in reaction chamber, you can be effectively increased the deposition rate in wafer centre position, neutralize loading effect influence, lift the homogeneity of epitaxial diposition.

Description

Deep trench extension fill process method
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of deep trench extension fill process method.
Background technology
Deep groove structure obtains relatively broad application in semiconductor technology now.For example, deep trench can be used as every From structure to completely cut off the electronic device of different operating voltage.And for example, deep trench can be applied to super junction MOS transistor (Super Junction MOSFET), reach high-breakdown-voltage performance by exhausting the charge balance of state as PN junction.In semiconductor manufacturing In technical process, the filling of deep trench extension is because by loading effect, (reacting gas is full of whole cavity, centre position The groove of filling in need, corresponding cavity centre position reacting gas are filled to centre position groove.And cavity edge Position do not have groove and need to fill, but gas distribution is uniform in cavity, and marginal portion gas needs also exist for participating in anti- Should, this portion gas can only participate in filling reaction in the groove close to crystal round fringes position, so result in participation close to wafer The reacting gas of marginal position groove is more than the reacting gas for participating in wafer centre position groove, i.e. the groove of marginal position is filled out Fill speed than marginal position trench fill speed faster, the phenomenon is referred to as loading effect) influence, it is widely used at present Deep trench filling technique be use flow velocity as 40L/min hydrogen be used as carrier gas, flow velocity be 5L/min hydrogen conduct clearly Gas washing body.Such setting makes in the range of edge EE10mm that fill rate is very fast, and centre position is slower, so as to cause edge groove Fill up, the groove in wafer centre position, in terms of the cross section of groove, still suffer from deeper " V " type mouth, internal homogeneity is bad. If increase deposition reaction duration merely, can fill up the groove in wafer centre position, but edge can produce because silicon growth is blocked up Defect.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of deep trench extension fill process method, make filling out for deep trench It is more preferable to fill homogeneity.
To solve the above problems, deep trench extension fill process method of the present invention, it is in the filling process, instead The flow set for answering carrier gas in chamber is 48~52L/Min, and the flow set of purgative gas is 2.5~3.5L/Min.
Further, described deep trench, the groove that gash depth is 42~45 μm is referred to.
Further, described carrier gas is hydrogen.
Further, described purgative gas is hydrogen, the atmosphere of stable reaction chamber.
Deep trench extension fill process method of the present invention, by adjusting carrier gas and purge gas in reaction chamber Flow velocity, process gas is set fully to be spread in reaction chamber, you can be effectively increased the deposition rate in wafer centre position, neutralize Loading effect influence, lift the homogeneity of epitaxial diposition.
Embodiment
Deep trench extension fill process method of the present invention, asked for epitaxial diposition in traditional handicraft is uneven Topic, have adjusted deposition process parameters.For example general deposit extension is to be passed through hydrogen in reaction chamber to set as carrier gas, parameter Surely it is carrier gas 40L/min, purgative gas 5L/Min, it is contemplated that the change of board and the difference of different platform, carrier gas scope is 38 ~42L/min, purgative gas scope is in 4.5~5.5L/min in tolerance interval.The present invention is by carrier gas in reaction chamber Flow set is 48~52L/Min, and the flow set of purgative gas is 2.5~3.5L/Min.
In the embodiment of the present invention, outer delay is deposited on the wafer with deep trench, it is reaction chamber in the filling process Hydrogen flowing quantity in room as carrier gas is set as 50L/Min, and the hydrogen flowing quantity as purgative gas is set as 3L/Min.
Above-mentioned technological parameter increases the flow velocity of carrier gas, process gas is fully spread in reaction chamber, you can effectively Increase the deposition rate in wafer centre position, and the flow velocity of purgative gas is reduced, neutralize loading effect influence, lifting is outer Prolong the homogeneity of deposit.
The preferred embodiments of the present invention are these are only, are not intended to limit the present invention.Come for those skilled in the art Say, the present invention there can be various modifications and variations.Within the spirit and principles of the invention, it is any modification for being made, equivalent Replace, improve etc., it should be included in the scope of the protection.

Claims (4)

  1. A kind of 1. deep trench extension fill process method, it is characterised in that:In the filling process, in reaction chamber carrier gas flow It is set as 48~52L/Min, the flow set of purgative gas is 2.5~3.5L/Min.
  2. 2. deep trench extension fill process method as claimed in claim 1, it is characterised in that:Described deep trench, it is dactylotome Groove of the groove depth at 42~45 μm.
  3. 3. deep trench extension fill process method as claimed in claim 1, it is characterised in that:Described carrier gas is hydrogen.
  4. 4. deep trench extension fill process method as claimed in claim 1, it is characterised in that:Described purgative gas is hydrogen, The atmosphere of stable reaction chamber.
CN201710579001.XA 2017-07-17 2017-07-17 Deep trench extension fill process method Pending CN107507759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710579001.XA CN107507759A (en) 2017-07-17 2017-07-17 Deep trench extension fill process method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710579001.XA CN107507759A (en) 2017-07-17 2017-07-17 Deep trench extension fill process method

Publications (1)

Publication Number Publication Date
CN107507759A true CN107507759A (en) 2017-12-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710579001.XA Pending CN107507759A (en) 2017-07-17 2017-07-17 Deep trench extension fill process method

Country Status (1)

Country Link
CN (1) CN107507759A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495294B1 (en) * 1999-10-28 2002-12-17 Denso Corporation Method for manufacturing semiconductor substrate having an epitaxial film in the trench
CN101448977A (en) * 2005-11-04 2009-06-03 应用材料股份有限公司 Apparatus and process for plasma-enhanced atomic layer deposition
US20150325640A1 (en) * 2006-04-11 2015-11-12 Stmicroelectronics S.R.L. Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495294B1 (en) * 1999-10-28 2002-12-17 Denso Corporation Method for manufacturing semiconductor substrate having an epitaxial film in the trench
CN101448977A (en) * 2005-11-04 2009-06-03 应用材料股份有限公司 Apparatus and process for plasma-enhanced atomic layer deposition
US20150325640A1 (en) * 2006-04-11 2015-11-12 Stmicroelectronics S.R.L. Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device

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Application publication date: 20171222