CN107507555A - Gate drive circuit - Google Patents
Gate drive circuit Download PDFInfo
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- CN107507555A CN107507555A CN201710906094.2A CN201710906094A CN107507555A CN 107507555 A CN107507555 A CN 107507555A CN 201710906094 A CN201710906094 A CN 201710906094A CN 107507555 A CN107507555 A CN 107507555A
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- 230000000087 stabilizing effect Effects 0.000 claims abstract description 71
- 230000033228 biological regulation Effects 0.000 claims description 57
- 230000005611 electricity Effects 0.000 claims description 11
- 230000000994 depressogenic effect Effects 0.000 claims description 6
- 238000013499 data model Methods 0.000 claims 1
- 230000001105 regulatory effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 8
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present disclosure provides a gate driving circuit, which includes an n + k stage shift register circuit and an n stage shift register circuit. The n + k stage shift register circuit includes an n + k stage secondary voltage stabilizing node. The nth stage shift register circuit comprises an nth stage output circuit, an nth stage voltage stabilizing circuit, an nth stage control circuit and a working circuit. The nth stage output circuit is used for outputting nth stage output voltage. The nth stage of voltage stabilizing circuit is used for providing the second stabilized voltage to the nth stage of operation node. The nth stage control circuit is used for providing the second regulated voltage to the nth stage main regulated node. The working circuit is used for simultaneously providing a first operating voltage to the nth stage operating node and the (n + k) th stage operating node of the (n + k) th stage shift register circuit. The voltage levels of the nth-stage main voltage stabilizing node and the nth + k-stage secondary voltage stabilizing node are substantially the same. The gate driving circuit provided by the disclosure can reduce the problem of bright and dark lines between two stages.
Description
Technical field
This disclosure relates to display technology field, in particular to a kind of gate driving circuit.
Background technology
In existing Display Technique, gate driving circuit substrate (gate driver on array；GOA) technology has made
For reaching the narrow frame effect of display panel.But in the prior art, the charging ability of adjacent two-stage is inconsistent, and this causes grid
Bright concealed wire is easily produced in the drive circuit of pole between two-stage.
The content of the invention
One embodiment of present disclosure is related to a kind of gate driving circuit.Gate driving circuit includes one n-th+k levels
Shift register circuit and one n-th grade of shift register circuit.N-th+k levels shift register circuit includes one n-th+k level voltage stabilizing sections
Point.N-th grade of shift register circuit includes one n-th grade of output circuit, one n-th grade of mu balanced circuit, one n-th grade of control circuit and one
Operating circuit.N-th grade of output circuit exports one n-th grade of output to one first operating voltage according to one n-th grade of running node
Voltage.N-th grade of mu balanced circuit is to one first voltage of voltage regulation, one second voltage of voltage regulation of offer according to one n-th grade of main voltage stabilizing node
To n-th grade of running node.N-th grade of control circuit is to the first operating voltage the second voltage stabilizing of offer according to n-th grade of running node
Voltage is to n-th grade of main voltage stabilizing node.Operating circuit is to the first operating voltage of offer simultaneously to n-th grade of running node and the n-th+k
One n-th+k level running nodes of level shift register circuit.N-th+k levels shift register circuit according to the n-th+k level running nodes the
One operating voltage exports one n-th+k level output voltages.The voltage level of n-th grade of main voltage stabilizing node and the n-th+k level voltage stabilizing nodes
It is substantially identical.
One embodiment of present disclosure is related to a kind of gate driving circuit.Gate driving circuit includes one first displacement
Register circuit, one second shift register circuit and an operating circuit.First shift register circuit include one first output circuit,
One first mu balanced circuit and a first control circuit.First output circuit is to one first behaviour according to one first running node
Make the output voltage of voltage output one first.First mu balanced circuit is to one first voltage of voltage regulation according to one first main voltage stabilizing node
One second voltage of voltage regulation to the first running node is provided.First control circuit is to the first operation electricity according to the first running node
Pressure provides the second voltage of voltage regulation to the first main voltage stabilizing node.Second shift register circuit includes one second output circuit, one second
Mu balanced circuit and a second control circuit.Second output circuit is defeated to the first operating voltage according to one second running node
Go out one second output voltage.Second mu balanced circuit is steady to provide second according to the second voltage of voltage regulation of one second main voltage stabilizing node
Piezoelectricity is depressed into the second running node.Second control circuit is steady to provide second according to the first operating voltage of the first running node
Piezoelectricity is depressed into the first main voltage stabilizing node.Operating circuit is to offer the first operating voltage to the first running node simultaneously and the second behaviour
Make node.
In summary, operating circuit simultaneously provide the first operating voltage to the first running node (such as：N-th grade of operation section
Point) and the second running node (such as：N-th+k levels running node).In this way, can reduce the first output voltage (such as：N-th grade
Output voltage) and the second output voltage (such as：N-th+k levels output voltage) voltage difference, and then reduce two-stage between bright concealed wire
The problem of.
Brief description of the drawings
For above and other purpose, feature, advantage and the embodiment of the disclosure can be become apparent, Figure of description
It is described as follows：
Fig. 1 is the schematic diagram according to a kind of gate driving circuit shown by the disclosure some embodiments；
Fig. 2A is wherein one-level shift LD in the gate driving circuit according to Fig. 1 shown by the disclosure some embodiments
The circuit diagram of circuit；
Fig. 2 B are another grade of shift LD electricity in the gate driving circuit according to Fig. 1 shown by the disclosure some embodiments
The circuit diagram on road；And
Fig. 3 is the timing diagram of part signal in the gate driving circuit according to Fig. 1 shown by the disclosure some embodiments.
Description of reference numerals：
100：Gate driving circuit
120 [1]~120 [16], 120 [n], 120 [n+k], 120 [i]：Shift register circuit
HC (1)~HC (16), HC (i), HC (n), HC (n+k), HC (17)：Clock signal
LC1、LC2：Control signal
G (1)~G (16), G (i), G (n), G (n+k), G (n+k+3), G (n+k+4), G (13), G (14)：Output voltage
ST、ST(n)、ST(n-2)、ST(n+k)、ST(n+k+3)、ST(n+k+4)、ST(11)、ST(12)、ST(16)、ST
(17)：Trigger signal
220：Output circuit
240：Mu balanced circuit
260：Control circuit
280：Operating circuit
T12、T21、T41、T31、T43、T33、T35、T42、T32、T34、T55、T56、T52、T54、T51、T53、T11、
T13、T44：Switch
C1：Electric capacity
P(n)、P(n+k)、P(13)、P(14)：Voltage stabilizing node
Q(n)、Q(n+k)、Q(13)、Q(14)：Running node
VGH、VSSQ、VSSG、VH、VL、V1、V2：Voltage
T1~T7：Time
Embodiment
Be hereafter for embodiment coordinate Figure of description elaborate, but the embodiment provided and be not used to limitation this
Open covered scope, and the description of structure operation is not used to limit its order performed, it is any to be reconfigured by element
Structure, the produced device with impartial technique effect, is all the scope that the disclosure is covered.In addition, accompanying drawing is only with explanation
Purpose, and mapped not according to full size.To make to readily appreciate, similar elements or similar components will be accorded with identical in the description below
Number sign and explain.
In word (terms) used in full piece specification and claim, in addition to having and especially indicating, generally have each
Word using in this area, in content disclosed herein with the usual meaning in special content.
It refer to Fig. 1.Fig. 1 is the schematic diagram according to a kind of gate driving circuit 100 shown by the embodiment of the disclosure one.
In certain embodiments, gate driving circuit 100 includes multiple grades of shift register circuit 120 [1]~120 [i], and i is positive integer.
By taking the 1st grade of shift register circuit 120 [1] as an example, the 1st grade of shift register circuit 120 [1] receives the 1st grade of clock signal HC (1),
And export the 1st grade of output voltage G (1) according to the 1st grade of clock signal HC (1).Other grade of shift register circuit has similar framework,
Repeated no more in this.
Please also refer to Fig. 2A and Fig. 2 B.Fig. 2A is driven according to the grid of Fig. 1 shown by the disclosure some embodiments
The circuit diagram of n-th grade of shift register circuit 120 [n] in dynamic circuit 100.Fig. 2 B are according to shown by the disclosure some embodiments
The circuit diagram of n-th+k levels shift register circuit 120 [n+k] in Fig. 1 gate driving circuit 100.In certain embodiments, n with
And k is all positive integer.In certain embodiments, k is equal to 1, but present disclosure is not limited system.It is equal to 1 these realities in k
Apply in example, Fig. 2A n-th grade of shift register circuit 120 [n] and Fig. 2 B the n-th+k levels shift register circuit 120 [n+k] are phase
The shift register circuit of adjacent two-stage.
For Fig. 2A examples, shift register circuit 120 [n] includes n-th grade of output circuit, 220, n-th grades of mu balanced circuits
240th, n-th grade of control circuit 260 and operating circuit 280.In some other embodiments, operating circuit 280 is configured at n-th
The outside of level shift register circuit 120 [n].
In certain embodiments, n-th grade of output circuit 220 is transmitted to the first of n-th grade of running node Q (n) to foundation
Operating voltage VGH, export n-th grade of output voltage G (n).In certain embodiments, n-th grade of mu balanced circuit 240 is to according to transmission
To n-th grade of main voltage stabilizing node P (n) the first voltage of voltage regulation (such as：Control signal LC1 high-voltage level), there is provided second is steady
Piezoelectricity presses VSSQ to n-th grades of running node Q (n).In certain embodiments, n-th grade of control circuit 260 is to according to transmitting to the
N level running node Q (n) the first operating voltage VGH, there is provided second voltage of voltage regulation VSSQ to n-th grades main voltage stabilizing node P (n).
Specifically, n-th grade of output circuit 220 includes switch T21 and switch T12.T21 first end is switched connecing
N-th grade of clock signal HC (n) is received, T21 the second end is switched to export n-th grade of output voltage G (n), switchs T21 control terminal
It is electrically connected with n-th grade of running node Q (n).T12 first end is switched to receive n-th grade of clock signal HC (n), switchs T12's
To export n-th grade of trigger signal ST (n), the control terminal for switching T12 is electrically connected with n-th grade of running node Q (n) at the second end.
Operationally, switch T21 and switch voltage level on or off of the T12 according to n-th grade of running node Q (n).
For example, when operating circuit 280 transmits the first operating voltage VGH to n-th grade of running node Q (n), switch T21 and open
Close T12 conductings.When switch T21 conductings, switch T21 transmits n-th grade of clock signal HC (n) and is used as n-th grade of output voltage G (n).When
T12 conductings are switched, switch T12 transmits n-th grade of clock signal HC (n) and is used as n-th grade of trigger signal ST (n).
N-th grade of mu balanced circuit 240 includes switch T42, switch T32, switchs T34, switchs T43, switch T33 to switch T35.
Switch T42, switch T32 and switch T34 control terminal n-th grade of main voltage stabilizing node P (n) of electric connection.Switch T43, switch T33
And switch T35 control terminal is electrically connected with the n-th level voltage stabilizing node P (n+k).Switch T42 and switch T43 first end electricity
Property n-th grade of running node Q (n) of connection, switch T42 and switch T43 the second end receiving the second voltage of voltage regulation VSSQ.Open
Close T32 and switch T33 first end and be electrically connected with electric capacity C1 and to receive n-th grade of output voltage G (n), switch T32 and
T33 the second end is switched receiving the 3rd voltage of voltage regulation VSSG.Switch T34 and T35 first end is switched receiving n-th
Level trigger signal ST (n), switch T34 and switch T35 the second end receiving the second voltage of voltage regulation VSSQ.
Operationally, T42, switch T32 are switched and switchs voltage levels of the T34 according to n-th grade of main voltage stabilizing node P (n)
On or off.For example, when n-th grade of control circuit 260 transmits the control signal LC1 with high-voltage level to n-th
The main voltage stabilizing node P (n) of level, switch T42, switch T32 and switch T34 conductings.Switch T43, T33 is switched to switch T35 foundations
N-th level voltage stabilizing node P (n+k) voltage level on or off.For example, when Fig. 2 B control circuit 260 will have
The control signal LC2 of high-voltage level is transmitted to the main voltage stabilizing node P (n+k) of the n-th+k levels, Fig. 2A switch T43, switch T33 with
And switch T35 conductings.When switch T42 or switch T43 conductings, the second voltage of voltage regulation VSSQ is provided by switching T42 or switch T43
To n-th grade of running node Q (n).For equivalent, T42 or switch T43 are switched by under n-th grade of running node Q (n) voltage level
It is pulled to the second voltage of voltage regulation VSSQ.When switch T32 or switch T33 conductings, T32 or switch T33 are switched by n-th grade of output voltage G
(n) voltage level is pulled down to the 3rd voltage of voltage regulation VSSG.When switch T34 or switch T35 conductings, switch T34 or switch T35 will
N-th grade of trigger signal ST (n) voltage level is pulled down to the second voltage of voltage regulation VSSQ.In certain embodiments, the 3rd voltage stabilizing electricity
Press VSSG and the second voltage of voltage regulation VSSQ substantially the same.
N-th grade of control circuit 260 includes switch T51, switch T53, switch T55, switch T56, switch T52 and switch
T54.T51 first end and control terminal are switched to receive control signal LC1, the second end for switching T51 is electrically connected with switch
T53 control terminal.Switch T51 and form diode (diode-connected) transistor.Switch T53 first end to
Control signal LC1 is received, the second end for switching T53 is electrically connected with n-th grade of main voltage stabilizing node P (n).Switch T55 and switch T56
Control terminal be electrically connected with the n-th+k level running node Q (n+k).Switch T52 and switch T54 n-th grade of control terminal electric connection
Running node Q (n).Switch T55 and switch T52 first end electric connection switch T53 control terminal, switch T55 and open
T52 the second end is closed receiving the second voltage of voltage regulation VSSQ.Switch T56 and switch T54 n-th grade of first end electric connection
Main voltage stabilizing node P (n), switch T56 and switch T54 the second end receiving the second voltage of voltage regulation VSSQ.
Operationally, T51 is switched according to control signal LC1 on or off.When switch T51 foundations have high-voltage level
Control signal LC1 conducting, switch T51 by control signal LC1 transmit to switch T53 control terminal.It is high according to having to switch T53
The control signal LC1 conductings of voltage level.When switch T53 conductings, T53 is switched by the control signal LC1 with high-voltage level
Transmit to n-th grade of main voltage stabilizing node P (n).Switch T52 and switch T54 are led according to n-th grade of running node Q (n) voltage level
Logical or cut-off.For example, when operating circuit 280 transmits the first operating voltage VGH to n-th grade of running node Q (n), switch
T52 or switch T54 conductings.Switch T55 and switch T56 according to the n-th+k level running node Q (n+k) voltage level conducting or
Cut-off.When switch T52 or switch T55 conductings, switch T52 or the voltage level for the control terminal for switching T53 is pulled down to by switch T55
Second voltage of voltage regulation VSSQ.When switch T54 or switch T56 conductings, the second voltage of voltage regulation VSSQ is by switching T54 or switch T56
There is provided to n-th grade of voltage stabilizing node P (n).For equivalent, T54 or switch T56 are switched by the voltage of n-th grade of main voltage stabilizing node P (n)
Level is pulled down to the second voltage of voltage regulation VSSQ.
In certain embodiments, operating circuit 280 triggers according to (n-2) level from (n-2) shift register circuit
Signal ST (n-2) while offer the first operating voltage VGH to n-th grades of running node Q (n) and the n-th+k level running node Q (n+
k).Specifically, operating circuit 280 includes first switch T11 and second switch T13.First switch T11 and second switch
T13 first end is receiving the first operating voltage VGH.In certain embodiments, the first operating voltage VGH voltage level is high
In the second voltage of voltage regulation VSSQ or the 3rd voltage of voltage regulation VSSG voltage level.First switch T11 and second switch T13 control
End processed is receiving (n-2) level trigger signal ST (n-2).First switch T11 the second end is electrically connected with n-th grade of running node
Q(n).Second switch T13 the second end is electrically connected with the n-th+k level running node Q (n+k) (being illustrated in Fig. 2 B).
Operationally, first switch T11 and second switch T13 according to (n-2) level trigger signal ST (n-2) conductings or
Cut-off.When first switch T11 is turned on, first switch T11 transmits the first operating voltage VGH to n-th grade of running node Q (n).When
Second switch T13 is turned on, and second switch T13 transmits the first operating voltage VGH to (n+k) level running node Q (n+k).By
Identical signal, therefore n-th grade of operation are all received in first switch T11 and second switch T13 control terminal and first end
Node Q (n) and (n+k) level running node Q (n+k) voltage level are substantially the same.N-th grade of shift register circuit 120 [n]
N-th grade of output voltage G (n) is exported according to the first operating voltage VGH transmitted to n-th grade of running node Q (n).N-th+k levels shift
Register circuit 120 [n+k] according to transmit to the n-th+k level running node Q (n+k) the first operating voltage VGH export the n-th+k levels it is defeated
Go out voltage G (n+k).
As noted previously, as n-th grade of running node Q (n) and (n+k) level running node Q (n+k) voltage level essence
Upper identical, n-th grade of shift register circuit 120 [n] and the charging ability of the n-th+k levels shift register circuit 120 [n+k] reach unanimity
It is or close.In this way, n-th grade of output voltage G (n) and the n-th+k level output voltage G (n+k) voltage difference are minimized, and then drop
Between low two-stage the problem of bright concealed wire.
In certain embodiments, n-th grade of shift register circuit 120 [n] is also comprising switch T44, switch T41 and switch
T31.The first end for switching T44 is electrically connected with n-th grade of running node Q (n), switchs T44 control terminal to receive trigger signal
ST, T44 the second end is switched to receive the second voltage of voltage regulation VSSQ.The first end for switching T41 is electrically connected with n-th grade of operation section
Point Q (n), switch T41 control terminal to receive the n-th+k+3 level trigger signal ST (n+k+3), switch T41 the second end to
Receive the second voltage of voltage regulation VSSQ.T31 first end is switched to receive n-th grade of output voltage G (n), switchs T31 control terminal
To receive the n-th+k+3 level output signal G (n+k+3), T31 the second end is switched to receive the 3rd voltage of voltage regulation VSSG.
Operationally, T41 is switched according to n-th+k+3 level trigger signals ST (n+k+3) on or off.When switch T41 is led
Logical, n-th grade of running node Q (n) voltage level is pulled down to the second voltage of voltage regulation VSSQ by switch T41.Switch T31 foundations n-th+
K+3 level output signals G (n+k+3) on or off.When switch T31 conductings, switch T31 pulls down n-th grade of output voltage G (n)
To the 3rd voltage of voltage regulation VSSG.
In certain embodiments, in addition to operating circuit 280, Fig. 2 B the n-th+k levels shift register circuit 120 [n+k] with
Fig. 2A n-th grade of shift register circuit 120 [n] has similar circuit framework.For ease of the purpose of understanding, in Fig. 2 B with figure
Similar element is by specified identical label in 2A.It is described below only for Fig. 2 B and the Main Differences in Fig. 2A.
Fig. 2A switch T42, switch T32 and the voltage level conducting for switching T34 n-th grade of main voltage stabilizing node P (n) of foundation
Or cut-off.Fig. 2 B switch T42, switch T32 and switch T34 are the voltage electricity according to the main voltage stabilizing node P (n+k) of the n-th+k levels
Flat on or off.
Fig. 2A switch T43, switch T33 and switch T35 is according to the n-th level voltage stabilizing node (i.e. main voltage stabilizing section of the n-th+k levels
Point P (n+k)) voltage level on or off.In other words, the voltage level of the n-th level voltage stabilizing node is essentially the same as n-th
The voltage level of the main voltage stabilizing node P (n+k) of+k levels.
Fig. 2 B switch T43, switch T33 and switch T35 is according to n-th+k level voltage stabilizings node (i.e. n-th grade of main voltage stabilizing
Node P (n)) voltage level on or off.In other words, the voltage level of the n-th+k level voltage stabilizing nodes is essentially the same as
The voltage level of n-th grade of main voltage stabilizing node P (n).
Accordingly, when n-th grade of main voltage stabilizing node P (n) voltage level for it is high (such as：Logical value 1) when, the switch in Fig. 2A
T42, switch T32 and switch T34 can be turned on, with respectively by n-th grade of running node Q (n), n-th grade of output voltage G (n) and
N-th grade of trigger signal ST (n) is pulled down to the second voltage of voltage regulation VSSQ or the 3rd voltage of voltage regulation VSSG.Meanwhile the switch in Fig. 2 B
T43, switch T33 and switch T35 can be turned on, with respectively by the n-th+k level running node Q (n+k), the n-th+k level output voltage G (n
+ k) and the n-th+k level trigger signal ST (n+k) be pulled down to the second voltage of voltage regulation VSSQ or the 3rd voltage of voltage regulation VSSG.It is equivalent and
Speech, the voltage level of n-th grade of main voltage stabilizing node P (n) can n-th grade of shift register circuit 120 [n] and figures in control figure 2A simultaneously
The pulling operation of n-th+k levels shift register circuit 120 [n+k] in 2B, to reach shared node and double control pulling operation
Technique effect.
Similarly, when the voltage level of the main voltage stabilizing node P (n+k) of the n-th+k levels is high, switch T42, switch in Fig. 2 B
T32 or switch T34 can be turned on, with respectively by the n-th+k level running node Q (n+k), the n-th+k level output voltage G (n+k) or the n-th+k
Level trigger signal ST (n+k) is pulled down to the second voltage of voltage regulation VSSQ or the 3rd voltage of voltage regulation VSSG.Meanwhile the switch in Fig. 2A
T43, switch T33 or switch T35 can turn on, with respectively by n-th grade of running node Q (n), n-th grade output voltage G (n) or n-th grade
Trigger signal ST (n) is pulled down to the second voltage of voltage regulation VSSQ or the 3rd voltage of voltage regulation VSSG.For equivalent, the n-th main voltage stabilizing of+k levels
Node P (n+k) voltage level can the n-th+k levels in n-th grade of shift register circuit 120 [n] and Fig. 2 B in control figure 2A simultaneously
The pulling operation of shift register circuit 120 [n+k], to reach the technique effect of shared node and double control pulling operation.
Control circuit 260 on Fig. 2A how to control n-th grade of main voltage stabilizing node P (n) voltage level will in it is following enter
Row description.When control signal LC1 voltage level is high, switch T51 conductings.Switch T51 transmits control signal LC1 to opening
Close T53 control terminal.When switch T53 conductings, switch T53 transmits control signal LC1 to n-th grade of main voltage stabilizing node P (n).
Because how Fig. 2 B control circuit 260 controls the voltage level of the main voltage stabilizing node P (n+k) of the n-th+k levels to have phase
Above-mentioned content is similar to, therefore is repeated no more in this.
It refer to Fig. 3.Fig. 3 is part in the gate driving circuit 100 according to Fig. 1 shown by the disclosure some embodiments
The timing diagram of signal.For ease of the purpose of understanding, it will be equal to by n exemplified by 13 and k is equal to 1 illustrate below.In other words, exist
In these examples, Fig. 2A n-th grade of shift register circuit 120 [n] is the 13rd grade of shift register circuit, and Fig. 2 B the n-th+k levels
Shift register circuit 120 [n+k] is the 14th grade of shift register circuit.
Fig. 3 show the 1st grade of clock signal HC (1) to the 17th grade of clock signal HC (17), trigger signal ST (11) and
ST (12), positioned at the voltage signal of the 13rd grade of running node Q (13) and the 14th grade of running node Q (14), positioned at the 13rd grade of master
Voltage stabilizing node P (13) and the voltage signal of the 14th grade of main voltage stabilizing node P (14), the 13rd grade of output signal G (13), the 14th grade it is defeated
Go out signal G (14), trigger signal ST (16) and ST (17).Clock signal described above corresponds to voltage VH and voltage VL.
In addition, clock signal described above is in units of 8 grades.For example, the 1st grade of clock signal HC (1) and the 9th grade of clock signal HC
(9) it is substantially synchronized or identical.
In time T1, trigger signal ST (11) voltage level switchs to high-voltage level.13rd grade of shift register circuit
The first switch T11 and second switch T13 of operating circuit 280 are according to trigger signal ST (11) conductings.First operating voltage VGH
Transmitted respectively by first switch T11 and second switch T13 to the 13rd grade of running node Q (13) and the 14th grade of running node
Q(14).Accordingly, the voltage level positioned at the 13rd grade of running node Q (13) and positioned at the 14th grade of running node Q (14) rises to
First operating voltage VGH.For equivalent, in time T1 to time T2, the 13rd grade of running node Q (13) and the 14th grade of operation section
Point Q (14) while the first operating voltage VGH is changed over by the second voltage of voltage regulation VSSQ.
In addition, in time T1 to time T2, due to Fig. 2A switch T54 and Fig. 2 B switch T56 according to being located at the 13rd
Level running node Q (13) voltage level is gradually turned on, thus the 13rd grade of voltage stabilizing node P (13) be pulled down by switching T54 and
14th grade of voltage stabilizing node P (14) is pulled down to the second voltage of voltage regulation VSSQ by switching T56.In other words, the 13rd grade of voltage stabilizing node P
(13) and the 14th grade of voltage stabilizing node P (14) by the first voltage of voltage regulation V1 (such as：Control signal LC1 high-voltage level) change
For the second voltage of voltage regulation VSSQ.Due to being pulled down positioned at the voltage level of the 14th grade of voltage stabilizing node P (14), therefore opening in Fig. 2 B
Closing T43 can end.Operating circuit 280 persistently provides the first operating voltage VGH to the 14th grades of running node Q (14) so that the 14th
Level running node Q (14) changes over the first operating voltage VGH by the second voltage of voltage regulation VSSQ.
In time T3, the 13rd grade of clock signal HC (13) voltage level switchs to high-voltage level.Now, the 13rd grade of displacement is posted
The switch T21 of circuit is deposited according to the voltage level conducting positioned at the 13rd grade of running node Q (13).13rd grade of clock signal HC (13)
It is used as the 13rd grade of output voltage G (13) by switching T21 transmission.Accordingly, the 13rd grade of output voltage G (13) begins to ramp up.It is another
Aspect, the 13rd grade of output voltage G (13) can be coupled to the 13rd grade of running node Q (13) by electric capacity C1 or other parasitic capacitances.
Therefore, the voltage level positioned at the 13rd grade of running node Q (13) continues to rise.Positioned at the voltage of the 13rd grade of running node Q (13)
Level rises to voltage V2.
Similar, in time T4, the 14th grade of clock signal HC (14) voltage level switchs to high-voltage level.Now, the 14th
The switch T21 of level shift register circuit is according to the voltage level conducting positioned at the 14th grade of running node Q (14).14th grade of clock letter
Number HC (14) is used as the 14th grade of output voltage G (14) by switching T21 transmission.Accordingly, on the 14th grade of output voltage G (14) starts
Rise.On the other hand, the 14th grade of output voltage G (14) can be coupled to the 14th grade of running node by electric capacity C1 or other parasitic capacitances
Q(14).Therefore, the voltage level positioned at the 14th grade of running node Q (14) continues to rise.Positioned at the 14th grade of running node Q (14)
Voltage level rise to voltage V2.
In time T5, the 13rd grade of clock signal HC (13) voltage level switchs to low voltage level.Accordingly, the 13rd grade of shifting is passed through
The switch T21 of position register circuit, the 13rd grade of output voltage G (13) begin to decline.Meanwhile by the 13rd grade of shift register circuit
Electric capacity C1 or other parasitic capacitances coupling effect, the voltage level positioned at the 13rd grade of running node Q (13) correspondingly starts
Decline.
Similar, in time T6, the 14th grade of clock signal HC (14) voltage level switchs to low voltage level.Accordingly, pass through
The switch T21 of 14th grade of shift register circuit, the 14th grade of output voltage G (14) begin to decline.Meanwhile posted by the 14th grade of displacement
The coupling effect of the electric capacity C1 or other parasitic capacitances in circuit are deposited, the voltage level positioned at the 14th grade of running node Q (14) is opened
Begin to decline.Further, since the switch T12 of the 16th grade of shift register circuit is according to the voltage positioned at the 16th grade of running node Q (16)
Level turns on, and switch T12 transmits the 16th grade of clock signal HC (16) to be used as the 16th grade of trigger signal ST (16).
In time T7, the 17th grade of clock signal HC (17) voltage level switchs to high-voltage level.Accordingly, the 17th grade of shifting is passed through
The switch T21 of position register circuit, the 17th grade of output voltage G (17) are correspondingly improved.Now, in the 13rd grade of shift register circuit
T31 is switched to turn on according to the 17th grade of output voltage G (17).Accordingly, switch T31 and the 13rd grade of output voltage G (13) is pulled down to the
Three voltage of voltage regulation VSSG.Further, since the switch T12 foundations of the 17th grade of shift register circuit are located at the 17th grade of running node Q
(17) voltage level conducting, switch T12 transmit the 17th grade of clock signal HC (17) to be used as the 17th grade of trigger signal ST (17).
In certain embodiments, open relation described above is realized with N-type transistor.In some other embodiments, on
Stating the switch can be realized with P-type transistor.
In summary, operating circuit simultaneously provide the first operating voltage to the first running node (such as：N-th grade of operation section
Point) and the second running node (such as：N-th+k levels running node).In this way, can reduce the first output voltage (such as：N-th grade
Output voltage) and the second output voltage (such as：N-th+k levels output voltage) voltage difference, and then reduce two-stage between bright concealed wire
The problem of.
Although the disclosure is disclosed as above with embodiment, so it is not limited to the disclosure, and any this area tool is logical
Normal skill, in the spirit and scope for not departing from the disclosure, when various variation and retouching, therefore the protection of the disclosure can be made
Scope is worked as to be defined depending on as defined in claim.
Claims (10)
1. a kind of gate driving circuit, comprising：
One n-th+k level shift register circuits, include one n-th+k level voltage stabilizing nodes；And
One n-th grade of shift register circuit, comprising：
One n-th grade of output circuit, to one first operating voltage according to one n-th grade of running node, export one n-th grade of output electricity
Pressure；
One n-th grade of mu balanced circuit, to one first voltage of voltage regulation according to one n-th grade of main voltage stabilizing node, there is provided one second voltage stabilizing
Voltage is to n-th grade of running node；
One n-th grade of control circuit, to first operating voltage according to n-th grade of running node, there is provided second voltage stabilizing electricity
It is depressed into this n-th grade main voltage stabilizing node；And
One operating circuit, to provide first operating voltage to n-th grade of running node and the n-th+k level shift LDs simultaneously
One n-th+k level running nodes of circuit, wherein the n-th+k levels shift register circuit according to the n-th+k level running nodes this
One operating voltage exports one n-th+k level output voltages,
The voltage level of wherein this n-th grade main voltage stabilizing node and the n-th+k level voltage stabilizing nodes is substantially identical.
2. gate driving circuit as claimed in claim 1, wherein the n-th+k level shift register circuits include：
One n-th+k level output circuits, to first operating voltage according to the n-th+k level running nodes, export one n-th+k levels
Output voltage；
One n-th+k level mu balanced circuits, to first voltage of voltage regulation according to the main voltage stabilizing node of one n-th+k levels, there is provided this second
Voltage of voltage regulation is to the n-th+k level running nodes；And
One n-th+k level control circuits, to first operating voltage according to the n-th+k level running nodes, there is provided this is second steady
Piezoelectricity is depressed into the main voltage stabilizing node of the n-th+k levels.
3. gate driving circuit as claimed in claim 1, the wherein operating circuit are also to according to from raster data model electricity
One the n-th -2 grades trigger signals of one the n-th -2 grades shift register circuits on road, while first operating voltage is provided to this n-th grade
The n-th+k level running nodes of running node and the n-th+k level shift register circuits.
4. gate driving circuit as claimed in claim 3, the wherein operating circuit include：
One first end of one first switch, the wherein first switch is to receive first operating voltage, and the one of the first switch
Second end is electrically connected with n-th grade of running node, and a control terminal of the first switch is believed to receive this n-th -2 grades triggerings
Number；And
One first end of one second switch, the wherein second switch is to receive first operating voltage, and the one of the second switch
Second end is electrically connected with the n-th+k level running nodes, and a control terminal of the second switch is believed to receive this n-th -2 grades triggerings
Number.
5. gate driving circuit as claimed in claim 1, wherein n-th grade of output circuit are also receiving one n-th grade of clock
Signal, and according to first operating voltage of n-th grade of running node, one n-th grade of triggering letter is used as using n-th grade of clock signal
Number.
6. gate driving circuit as claimed in claim 1, wherein n-th grade of running node and the n-th+k levels running node are simultaneously
First operating voltage is changed into by second voltage of voltage regulation.
7. gate driving circuit as claimed in claim 1, wherein being changed in this n-th grade main voltage stabilizing node by first voltage of voltage regulation
While being changed into second voltage of voltage regulation, the n-th+k levels running node changes into the first operation electricity by second voltage of voltage regulation
Pressure.
8. a kind of gate driving circuit, comprising：
One first shift register circuit, comprising：
One first output circuit, to one first operating voltage according to one first running node, export one first output voltage；
One first mu balanced circuit, to one first voltage of voltage regulation according to one first main voltage stabilizing node, there is provided one second voltage stabilizing electricity
It is depressed into first running node；And
One first control circuit, to first operating voltage according to first running node, there is provided second voltage of voltage regulation
To the first main voltage stabilizing node；
One second shift register circuit, comprising：
One second output circuit, to first operating voltage according to one second running node, export one second output voltage；
One second mu balanced circuit, to second voltage of voltage regulation according to one second main voltage stabilizing node, there is provided second voltage stabilizing electricity
It is depressed into second running node；And
One second control circuit, to first operating voltage according to first running node, there is provided second voltage of voltage regulation
To the first main voltage stabilizing node；And
One operating circuit, to provide first operating voltage to first running node and second running node simultaneously.
9. gate driving circuit as claimed in claim 8, wherein first running node and the second running node are simultaneously by this
Second voltage of voltage regulation changes into first operating voltage.
10. gate driving circuit as claimed in claim 8, wherein being changed in the first main voltage stabilizing node by first voltage of voltage regulation
While being changed into second voltage of voltage regulation, second running node changes into first operating voltage by second voltage of voltage regulation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106127653A TWI623926B (en) | 2017-08-15 | 2017-08-15 | Gate driving circuit |
| TW106127653 | 2017-08-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107507555A true CN107507555A (en) | 2017-12-22 |
| CN107507555B CN107507555B (en) | 2020-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710906094.2A Active CN107507555B (en) | 2017-08-15 | 2017-09-29 | Gate drive circuit |
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| CN110619839A (en) * | 2019-03-08 | 2019-12-27 | 友达光电股份有限公司 | Gate drive circuit and control method of shift register |
| WO2020124822A1 (en) * | 2018-12-21 | 2020-06-25 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
| CN111341241A (en) * | 2019-09-04 | 2020-06-26 | 友达光电股份有限公司 | Gate drive circuit |
| CN111402828A (en) * | 2020-04-09 | 2020-07-10 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201911274A (en) | 2019-03-16 |
| TWI623926B (en) | 2018-05-11 |
| CN107507555B (en) | 2020-06-23 |
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