CN107492479A - 制造半导体器件的方法和对应的器件 - Google Patents
制造半导体器件的方法和对应的器件 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 50
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 46
- 238000001465 metallisation Methods 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 21
- 239000010931 gold Substances 0.000 claims abstract description 17
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 16
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 12
- 229910052737 gold Inorganic materials 0.000 claims abstract description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000010949 copper Substances 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 44
- 238000005516 engineering process Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 230000002522 swelling effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02697—Forming conducting materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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Abstract
在一个实施例中，一种制造包括金属化结构(例如再布线层－RDL金属化结构)的方法包括：提供封盖堆叠至金属化结构上，其中堆叠包括至少一个镍层，在堆叠中包括镍层的配对，两者之间具有诸如钯或金之类的易延展材料的层。
Description
技术领域
说明书涉及制造半导体器件。
一个或多个实施例可以例如应用于减小例如汽车和消费产品的集成电路中的热-机械应力。
背景技术
各种类型的集成电路(IC)可以采用诸如BCD(双极－CMOS－DMOS)技术的技术。
BCD技术可以有利地用于例如制造具有功率电子器件和逻辑控制电子器件的集成电路。BCD技术提供了一系列硅工艺，每一个将三种不同工艺技术的力量结合至单个芯片上：双极用于精确的模拟功能，CMOS(互补金属氧化物半导体)用于数字设计，以及DMOS(双扩散金属氧化物半导体)用于功率和高电压元件。
实施BCD技术可以包括顶层铜金属互连，其被称作再布线层(RDL)。
这可以包括使用铜RDL模块作为最终金属。该模块可以包括由例如Ni和Pd层或层堆叠所覆盖的Cu线条/焊盘/功率金属化结构(例如10微米－10×10-6米－高)。
同样，氮化硅(SiN)或碳化硅(SiC)可以用于制造IC以为微芯片提供钝化层，例如用于提供针对水分子和微电子器件中腐蚀和不稳定性的其他来源的阻挡层。
考虑由金属性材料(Ni、Pd、Cu、Ti、W)的热-机械膨胀/收缩在钝化材料(例如Si硅化物)上感应形成的机械应力问题可以促进实现令人满意的结果。就此而言，观测到局部应力对钝化层的贡献与Ni膨胀相关，由于Cu/Ni/Pd热膨胀系数失配而应力在热处理期间增大，此时发现这些效应随着Ni厚度增大而增大。
发明内容
一个或多个实施例的目的在于对于考虑前述关键问题所起的贡献。
根据一个或多个实施例，可以借由具有以下权利要求中所述的特征的方法而实现该目的。
一个或多个实施例也可以涉及一种对应的器件。
权利要求是已经在此提供的一个或多个实施例的技术公开的整体部分。
一个或多个实施例可以促进考虑可以由诸如Ni、Pd、Cu、Ti、W之类的金属性材料的热-机械膨胀/收缩诱使的在钝化材料(例如Si氮化物)中的机械应力问题。
一个或多个实施例可以包括Ni/Pd的交替沉积(例如无电电镀或无电镀沉积)以减小应力效果。
甚至不希望受约束于在该方面的任何具体理论，例如Pd夹层的延展性可以帮助在热循环期间吸收机械应力。
在一个或多个实施例中，薄延展(例如Pd)层可以形成在两个Ni层之间，以便于减小并退耦应力贡献。
一个或多个实施例可以受益于可不采用Ni表面化学预处理而实现在Pd上沉积Ni。
一个或多个实施例可以包括在例如RDL铜上Ni Pd无电电镀沉积(简称无电镀)多层沉积：以交替顺序沉积Ni和Pd的四个层(Ni/Pd/Ni/Pd)以便于减小在热循环之上的机械应力。
一个或多个实施例可以采用不同于(例如Cu)Ni-Pd-Ni-Pd的其他类型(例如无电镀)沉积。
诸如(Cu)Ni-Pd-Ni-Pd-Au、(Cu)Ni-Au-Ni-Pd、(Cu)Ni-Au-Ni-Pd-Au的沉积是该备选沉积选项的示例。
附图说明
现在将纯粹借由示例、参照附图描述一个或多个实施例，其中：
－图1是可以包括一个或多个实施例的堆叠设置的顶视图，
－图2是跨常规(单个)堆叠设置的SEM显微剖面的复制品，以及
－图3是根据实施例的跨(双重)堆叠设置的SEM显微剖面的复制品。
应该知晓的是为了表达清楚的目的，附图的某些特征(例如层厚度)可以不按照比例绘制。
具体实施方式
在随后的说明书中，示出了一个或多个具体细节，目的在于提供在本说明书中实施例的示例的深入理解。可以不采用一个或多个具体细节、或者采用其他方法、部件、材料等而获得实施例。在其他情形中，并未详细图示或描述已知的结构、材料或操作，以使得将不会模糊实施例的某些特征方面。
在本说明书的框架中涉及“一实施例”或“一个实施例”意在用于指示关于该实施例所述的特定配置、结构或特性包括在至少一个实施例中。因此，可以存在于本说明书的一个或多个地方的诸如“在一实施例中”或“在一个实施例中”的短语无需涉及一个且相同的实施例。此外，可以在一个或多个实施例中以任何适当的方式组合特定的构造、结构或特性。
纯粹为了方便而提供在此使用的参考并且因此并未限定实施例的保护范围或者范围。
文献EP 1 320 129 B1公开了一种包括半导体材料的裸片和支座的半导体电子器件，半导体材料的裸片包括集成电子电路以及与电子电路相关联并且由引线电连接至支座的多个接触焊盘。每个接触焊盘包括铝、铜或其合金的下层，以及包括选自包括镍、钯或其合金的群组的金属和/或金属合金的至少一个薄膜、并且由无电化学工艺沉积的上层。
尽管并未涉及RDL技术，并且更确切地，在EP 1 320 129 B1的公开的一个或多个实施例中构思的类型未公开多个层提供了关于这些工艺的一些背景信息。
图1是例如由BCD－RDL工艺产生的半导体器件S的一部分的顶视图，其包括可以包含一个或多个实施例的堆叠设置。
半导体器件S(例如集成电路－IC)可以借由RDL工艺而制造，RDL工艺包括(以本质上已知的方式)以下步骤序列，该步骤序列导致形成RDL金属化结构10(例如Cu)，其具有下方的阻挡层12例如TiW或其他阻挡层材料，诸如TiN/Ti/Tin Ta/Tan。
随后可以在金属化结构10的外表面上提供组合(堆叠)的外表面涂层或“封盖”，涂层或封盖具有例如近似2微米(2×10-6m)的厚度。
在如图2中所示例的常规设置中，该堆叠的盖层(也即多层)可以包括例如具有在14处的Ni、在16处的Pd的Ni-Pd层。在其他常规设置中，堆叠的封盖可以包括Ni-Pd-Au或Ni-Au的多层。
尽管成功地用于制造，该Ni/Pd层可以呈现一定量的应力，例如，如果暴露至在例如300℃至400℃范围中的温度。
具体地，可以观测到，该“单个”Ni－Pd堆叠14、16可以在热循环期间在钝化层上诱生过高的应力。
如图3中所示例化的一个或多个实施例可以通过依靠“多个”堆叠设置而减小由于例如Ni层引起的局部应力，多个堆叠设置从金属化结构(例如Cu)10开始包括：
－第一Ni层141，
－第一(薄)Pd层161，
－第二Ni层142，
－第二Pd层162。
在一个或多个实施例中，可以在两个Ni层141、142之间提供易延展材料(例如Pd)的层161(薄，例如0.1-0.5微米0.1-0.5×10-6m)。
在一个或多个实施例中，层161(Pd，或可能的，其他易延展材料诸如例如Au)的存在可以导致Ni应力“退耦”至两个分立的贡献中，由于层161的易延展性而幅度较低。
甚至不希望在该方面受任何具体理论的约束，例如Pd夹层的易延展性可以帮助在热循环期间吸收机械应力。
同样，一个或多个实施例可以受益于在可不采用任何Ni表面化学预处理而实施的例如Pd上沉积Ni。
额外地，参见例如图1的示例性放大图，通过光学检查可以在晶片(裸片)上观测不到差别。
在一个或多个实施例中通过采取在例如铜上交替沉积例如Ni/Pd/Ni/Pd(参见例如141、161、142、162)可以由于在热循环期间可以吸收机械应力的Pd夹层的易延展性而减小应力效果。
一个或多个实施例可以促进满足对于例如用于汽车领域的功率封装的请求规范。
如所示，一个或多个实施例可以包括除了Ni(层141)－Pd(层161)－Ni(层142)－Pd(层162)之外的堆叠沉积。
该交替沉积可以包括例如
－使用另一易延展材料(例如Au)用于层161，和/或
－在堆叠的外表面处的外层(例如如图3中示意性在链线中示出为18的Au)。
诸如(Cu)Ni-Pd-Ni-Pd-Au、(Cu)Ni-Au-Ni-Pd、(Cu)Ni-Au-Ni-Pd-Au之类的沉积因此是该备选沉积选项的示例。
以下可以是对于在根据一个或多个实施例的堆叠中层的示例性厚度数值：
-层141：0.1－0.5微米(0.1-0.5×10-6m)
-层161：0.1－0.5微米(0.1-0.5×10-6m)
-层142：0.5－1.5微米(0.5-1.5×10-6m)
-层162：0.2－0.5微米(0.2-0.5×10-6m)
一个或多个实施例可以因此提供一种制造半导体器件的方法，该半导体器件包括至少一个金属化结构(例如10)，方法包括：
-在所述金属化结构上(例如通过无电沉积)提供封盖堆叠(例如141、161、142、162)，其中所述堆叠包括至少一个镍层，
-在所述堆叠中包括镍层配对(例如141、142)，镍层配对具有夹设在它们之间的易延展性材料的层(例如161)。
在一个或多个实施例中，所述易延展材料可以选自钯(Pd)和金(Au)。
一个或多个实施例可以包括提供所述金属化结构作为铜金属化结构，任选地作为再布线层－RDL金属化结构。
一个或多个实施例可以包括在所述堆叠中、与所述金属化结构相对地提供易延展材料的至少一个外层(例如162，18)。
一个或多个实施例可以包括在所述堆叠中、与所述金属化结构相对地提供包括钯的第一外层(例如162)和包括金的最外层(例如18)。
一个或多个实施例可以包括在所述至少一个金属化结构下方提供阻挡层(例如12)。
在一个或多个实施例中，在所述至少一个金属化结构下方的所述阻挡层可以包括TiW。
一个或多个实施例可以包括提供邻接所述阻挡层(参见例如图3，右下方)的封盖堆叠以提供所述至少一个金属化结构的全面覆盖。
一个或多个实施例可以提供一种半导体器件，包括：
－至少一个金属化结构(例如10)，以及
－封盖堆叠(例如141、161、142、162；18)，被提供在所述金属化结构上，其中所述堆叠包括在它们之间具有易延展材料层的镍层配对。
在一个或多个实施例中：
－所述易延展材料(161)可以选自钯和金，和/或
－堆叠可以包括与所述金属化结构相反的、易延展材料的至少一个外层。
无损于以下原理，相对于纯粹借由示例的方式而并未脱离保护范围已经公开的内容，可以甚至巨大地改变细节和实施例。
保护范围由所附权利要求限定。
Claims (10)
1.一种制造包括至少一个金属化结构(10)的半导体器件的方法，所述方法包括：
－在所述金属化结构(10)上提供封盖堆叠(141、161、142、162)，其中所述堆叠包括至少一个镍层，
－在所述堆叠(141、161、142、162)中包括镍层配对(141，142)，所述镍层配对(141，142)在它们之间具有易延展材料(161)的层。
2.根据权利要求1所述的方法，其中，所述易延展材料(161)选自钯和金。
3.根据权利要求1或权利要求2所述的方法，包括提供所述金属化结构(10)作为铜金属化结构，优选地作为再布线层－RDL金属化结构。
4.根据前述权利要求中任一项所述的方法，包括在所述堆叠中、与所述金属化结构(10)相对地提供易延展材料的至少一个外层(162，18)。
5.根据权利要求4所述的方法，包括，在所述堆叠中、与所述金属化结构(10)相对地提供包括钯的第一外层(162)和包括金的最外层(18)。
6.根据前述权利要求中任一项所述的方法，包括在所述至少一个金属化结构(10)下方提供阻挡层(12)。
7.根据权利要求6所述的方法，包括：
－在所述至少一个金属化结构(10)下方提供包括TiW的所述阻挡层，和/或
－提供与在所述至少一个金属化结构(10)下方的所述阻挡层(12)邻接的所述封盖堆叠(141、161、142、162)，以提供所述至少一个金属化结构(10)的完全覆盖。
8.根据前述权利要求中任一项所述的方法，包括通过无电沉积在所述金属化结构上提供所述堆叠(141、161、142、162)。
9.一种半导体器件，包括：
－至少一个金属化结构(10)，以及
－封盖堆叠(141、161、142、162)，被提供在所述金属化结构(10)上，其中所述堆叠包括镍层配对(141，142)，所述镍层配对(141，142)具有在它们之间的易延展材料(161)的层。
10.根据权利要求9所述的半导体器件，其中：
－所述易延展材料(161)选自钯和金，和/或
－所述堆叠包括与所述金属化结构(10)相对的所述易延展材料的至少一个外层(162，18)。
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| EP16425053.2 | 2016-06-13 | ||
| EP16425053.2A EP3258490A1 (en) | 2016-06-13 | 2016-06-13 | A method of manufacturing semiconductor devices and corresponding device |
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| CN201611226894.1A Pending CN107492479A (zh) | 2016-06-13 | 2016-12-27 | 制造半导体器件的方法和对应的器件 |
| CN201621453923.3U Active CN206711866U (zh) | 2016-06-13 | 2016-12-27 | 半导体器件 |
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| US (1) | US20170358536A1 (zh) |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0030633A1 (en) * | 1979-12-17 | 1981-06-24 | International Business Machines Corporation | Nickel-gold-nickel conductors for solid state devices |
| US5294486A (en) * | 1990-10-22 | 1994-03-15 | International Business Machines Corporation | Barrier improvement in thin films |
| US6544880B1 (en) * | 1999-06-14 | 2003-04-08 | Micron Technology, Inc. | Method of improving copper interconnects of semiconductor devices for bonding |
| US6555912B1 (en) * | 2001-10-23 | 2003-04-29 | International Business Machines Corporation | Corrosion-resistant electrode structure for integrated circuit decoupling capacitors |
| EP1320129A1 (en) * | 2001-12-14 | 2003-06-18 | STMicroelectronics S.r.l. | Semiconductor electronic device and method of manufacturing thereof. |
| US7776660B2 (en) * | 2006-09-27 | 2010-08-17 | Renesas Technology Corp. | Manufacturing method of a semiconductor device |
| US20140332964A1 (en) * | 2013-05-10 | 2014-11-13 | International Business Machines Corporation | Interconnect structures containing nitrided metallic residues |
| CN206711866U (zh) * | 2016-06-13 | 2017-12-05 | 意法半导体股份有限公司 | 半导体器件 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3617816A (en) * | 1970-02-02 | 1971-11-02 | Ibm | Composite metallurgy stripe for semiconductor devices |
-
2016
- 2016-06-13 EP EP16425053.2A patent/EP3258490A1/en not_active Withdrawn
- 2016-12-27 CN CN201611226894.1A patent/CN107492479A/zh active Pending
- 2016-12-27 CN CN201621453923.3U patent/CN206711866U/zh active Active
- 2016-12-28 US US15/392,548 patent/US20170358536A1/en not_active Abandoned
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0030633A1 (en) * | 1979-12-17 | 1981-06-24 | International Business Machines Corporation | Nickel-gold-nickel conductors for solid state devices |
| US5294486A (en) * | 1990-10-22 | 1994-03-15 | International Business Machines Corporation | Barrier improvement in thin films |
| US6544880B1 (en) * | 1999-06-14 | 2003-04-08 | Micron Technology, Inc. | Method of improving copper interconnects of semiconductor devices for bonding |
| US6555912B1 (en) * | 2001-10-23 | 2003-04-29 | International Business Machines Corporation | Corrosion-resistant electrode structure for integrated circuit decoupling capacitors |
| EP1320129A1 (en) * | 2001-12-14 | 2003-06-18 | STMicroelectronics S.r.l. | Semiconductor electronic device and method of manufacturing thereof. |
| US7776660B2 (en) * | 2006-09-27 | 2010-08-17 | Renesas Technology Corp. | Manufacturing method of a semiconductor device |
| US20140332964A1 (en) * | 2013-05-10 | 2014-11-13 | International Business Machines Corporation | Interconnect structures containing nitrided metallic residues |
| CN206711866U (zh) * | 2016-06-13 | 2017-12-05 | 意法半导体股份有限公司 | 半导体器件 |
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| EP3258490A1 (en) | 2017-12-20 |
| US20170358536A1 (en) | 2017-12-14 |
| CN206711866U (zh) | 2017-12-05 |
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