CN107481946A - A kind of method for packing and structure of CIS devices - Google Patents
A kind of method for packing and structure of CIS devices Download PDFInfo
- Publication number
- CN107481946A CN107481946A CN201710720105.8A CN201710720105A CN107481946A CN 107481946 A CN107481946 A CN 107481946A CN 201710720105 A CN201710720105 A CN 201710720105A CN 107481946 A CN107481946 A CN 107481946A
- Authority
- CN
- China
- Prior art keywords
- cis
- groove
- chips
- wafer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
Abstract
The invention provides a kind of method for packing and structure of CIS devices, wherein, method includes：By CIS flip-chips on wafer, at least in the lenticule insertion wafer of CIS chips, CIS chips have through hole, are filled with conductive material in through hole, the pad of CIS chip front sides is connected to the back side of CIS chips by conductive material；It is packaged on wafer, encapsulated layer is formed on the outside of CIS chips；Encapsulated layer is thinned to the conductive material exposed in through hole；Line layer is prepared in CIS chip backs, line layer is connected with conductive material, prepares insulating barrier in circuit layer surface, salient point is prepared at windowing on the insulating layer, salient point is connected with line layer.CIS chips are positioned in wafer by the method for packing of this CIS devices, are combined CIS chips with wafer by encapsulating material, have the advantages of package dimension is small, light transmittance is high, technological operation is simple low with production cost.
Description
Technical field
The present invention relates to field of semiconductor package, and in particular to a kind of method for packing and structure of CIS devices.
Background technology
Microelectronic imaging element is widely used in digital camera (camera), has the unlimited device of image store ability
Or in other purposes.Microelectronic imaging element includes imaging sensor, and imaging sensor is that optical imagery is converted into telecommunications
Number semiconductor devices, generally can be divided into charge coupling device (Charge Coupled Device, CCD) and complementary metal oxygen
Compound semiconductor image sensor (Complementary-Metal-Oxide-Semiconductor Image Sensor,
CIS).Cmos image sensor (CIS) utilizes control circuit and the signal processing circuit around MOS transistor and use
The handoff technique of MOS transistor sequentially detects output, wherein, the quantity of MOS transistor is equal to the quantity of pixel, that is, utilizes
Light is by watch crystal cover plate and printing opacity glue, the photosensitive area being irradiated on chip, completes conversion of the optical signal to electric signal, so as to
The principle of imaging.Cmos image sensor (CIS) can overcome charge coupling device (CCD) manufacturing process complexity and energy consumption is higher
The defects of, can be integrated on the same chip by pixel unit array and peripheral circuit using CMOS fabrication technology so that CIS cores
Piece has the advantages of small volume, in light weight, low-power consumption, convenient, easily controllable and inexpensive programming.
Traditional CIS devices encapsulation includes wafer-level packaging method and chip-scale packaging method, wherein according to packaging technology
It is different be divided into again chip size packages (Chip Scale Package, CSP), chip on board encapsulation (Chip On Board,
COB), Flip-Chip Using (Flip Chip, FC).At present, the CIS chip encapsulation technologies of main flow include COB and CSP.Wafer
Level chip-scale package (Wafer Level Chip Scale Packaging, WLCSP), i.e. wafer stage chip packaged type,
Different from traditional chip package mode (first cut and seal survey again, at least increase the volume of former chip 20% after encapsulation), this kind envelope
Dress is that packaging and testing is first carried out on full wafer wafer, then just cuts into chip particle one by one, therefore the body after encapsulation
Product is equal to the full size of chip bare crystalline, can reduce package dimension, improve integration density and performance.
In CSP wafer scale (Wafer Level) encapsulation process, traditional CIS devices are using first to chip progress
Circuit production, printing opacity glue then is coated on chip photosensitive area surface, adds the mode of glass cover-plate to complete the making of CIS devices.By
In the making that first carry out circuit, consider that later stage chip will be bonded with glass cover-plate, the thickness of chip can not be just made
It is thin.And due to apply printing opacity glue in chip surface, a circle copper wire is also done on chip, photosensitive area is formed cavity, adds
Chip thickness and technological operation difficulty after encapsulation.
The content of the invention
Therefore, the technical problem to be solved in the present invention is to overcome that CIS devices package dimension of the prior art is big, printing opacity
The defects of rate is low, at least one complex operation and production cost height.
Therefore, the present invention provides a kind of method for packing of CIS devices, comprise the following steps：By CIS flip-chips in wafer
On, the lenticule of at least described CIS chips is embedded in the wafer, and the CIS chips have through hole, are filled with the through hole
The pad of the CIS chip front sides is connected to the back side of the CIS chips by conductive material, the conductive material；In the crystalline substance
It is packaged on circle, encapsulated layer is formed on the outside of the CIS chips；The encapsulated layer is thinned to the conduction exposed in the through hole
Material；Line layer is prepared in the CIS chip backs, the line layer is connected with the conductive material, in the line layer table
Face prepares insulating barrier, and salient point is prepared at the windowing on the insulating barrier, and the salient point is connected with the line layer.
Alternatively, it is described by the CIS flip-chips on wafer, described in the insertion of the lenticules of at least described CIS chips
In step in wafer, including：The first groove is prepared on wafer, the first bottom portion of groove prepare the second groove, described second
The width of groove is less than the bottom of first groove, and the outer peripheral width of the CIS chips is less than first groove
Width, more than the width of second groove；The CIS chips are positioned over to the bottom of first groove, the CIS chips
Lenticule is located in second groove.
Alternatively, it is described to be positioned over the CIS chips before the bottom of first groove, it is additionally included in described second
The inside cavity filling light transmissive material that groove is formed.
Alternatively, the packed height of the light transmissive material is more than the depth of second groove.
Alternatively, it is described to be packaged on the wafer, after the step of encapsulated layer is formed on the outside of the CIS chips,
Also include：The wafer is thinned.
Alternatively, described to prepare line layer in the CIS chip backs, the line layer is connected with the conductive material,
Insulating barrier is prepared in the circuit layer surface, salient point, the salient point and the circuit are prepared at the windowing on the insulating barrier
After the step of layer connection, in addition to：The wafer is cut, forms single CIS device.
The present invention also provides a kind of CIS devices prepared using the above method.
The present invention also provides a kind of CIS devices, including wafer layer, and the wafer layer is interior recessed with the first groove and second
Groove, the width of second groove are less than the bottom of first groove, and the outer peripheral width of CIS chips is less than described first
The width of groove, more than the width of second groove, the CIS flip-chips are above second groove and the CIS
The lenticule of chip is embedded in second groove, has encapsulated layer on the outside of the CIS chips, has at least on the CIS chips
One through hole, the inside of the through hole are filled with conductive material, and the conductive material connects the pad of the CIS chips, described
CIS chip backs have line layer, and the line layer is connected with the conductive material, and the circuit layer surface has insulating barrier,
Windowing is provided with the insulating barrier, salient point is provided with the windowing, the salient point is connected with the line layer.
Alternatively, the inside cavity filling light transmissive material that second groove is formed.
Alternatively, the back side of the CIS chips and the notch of first groove maintain an equal level.
Technical solution of the present invention, have the following advantages that：
1. the method for packing of CIS devices provided by the invention, including by CIS flip-chips on wafer, at least described CIS
The lenticule of chip is embedded in the wafer, and the CIS chips have through hole, and conductive material is filled with the through hole, described
The pad of the CIS chip front sides is connected to the back side of the CIS chips by conductive material；It is packaged on the wafer,
Encapsulated layer is formed on the outside of the CIS chips；The encapsulated layer is thinned to the conductive material exposed in the through hole；Described
CIS chip backs prepare line layer, and the line layer is connected with the conductive material, prepare and insulate in the circuit layer surface
Layer, salient point is prepared at the windowing on the insulating barrier, the salient point is connected with the line layer.The encapsulation of this CIS devices
CIS chips are positioned in wafer by method, are combined CIS chips with wafer by encapsulating material, have package dimension it is small,
The advantages of light transmittance is high, technological operation is simple low with production cost.
2. CIS devices provided by the invention, including wafer layer, the wafer layer is interior to have the first groove and the second groove,
The width of second groove is less than the bottom of first groove, and the outer peripheral width of CIS chips is recessed less than described first
The width of groove, more than the width of second groove, the CIS flip-chips are above second groove and the CIS cores
The lenticule of piece is embedded in second groove, has encapsulated layer on the outside of the CIS chips, has at least one on the CIS chips
Individual through hole, the inside of the through hole are filled with conductive material, and the conductive material connects the pad of the CIS chips, the CIS
Chip back has line layer, and the line layer is connected with the conductive material, and the circuit layer surface has insulating barrier, described
Windowing is provided with insulating barrier, salient point is provided with the windowing, the salient point is connected with the line layer.This CIS devices
Package dimension it is small, light transmittance is high, it is simple to prepare and production cost is low.
Brief description of the drawings
, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical scheme of the prior art
The required accompanying drawing used is briefly described in embodiment or description of the prior art, it should be apparent that, in describing below
Accompanying drawing is some embodiments of the present invention, for those of ordinary skill in the art, before creative work is not paid
Put, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of a specific example of the method for packing of CIS devices in the embodiment of the present invention 1；
Fig. 2 is the flow chart of another specific example of the method for packing of CIS devices in the embodiment of the present invention 1；
Fig. 3-Figure 15 is the specific steps schematic diagram of the method for packing of CIS devices in the embodiment of the present invention 1；
Figure 16 is the structure chart of a specific example of CIS devices in the embodiment of the present invention 2；
Figure 17 is the structure chart of another specific example of CIS devices in the embodiment of the present invention 2.
Embodiment
Technical scheme is clearly and completely described below in conjunction with accompanying drawing, it is clear that described implementation
Example is part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
In the description of the invention, it is necessary to explanation, term " " center ", " on ", " under ", "left", "right", " vertical ",
The orientation or position relationship of the instruction such as " level ", " interior ", " outer " be based on orientation shown in the drawings or position relationship, merely to
Be easy to the description present invention and simplify description, rather than instruction or imply signified device or element must have specific orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second ",
" the 3rd " is only used for describing purpose, and it is not intended that instruction or hint relative importance.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected by intermediary, can be with
It is the connection of two element internals, can is wireless connection or wired connection.For one of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.
As long as in addition, technical characteristic involved in invention described below different embodiments non-structure each other
It is be combined with each other into conflict can.
Embodiment 1
The present embodiment provides a kind of method for packing of CIS devices, and flow chart is as shown in Figure 1.One as the present embodiment
Preferred scheme, flow chart is as shown in Fig. 2 comprise the following steps：
S011：Carrier of the wafer 01 as CIS chips 02, some CIS chips 02 can be carried, as shown in figure 3, according to
The characteristic of CIS chips, in the present embodiment, wafer 01 are glass wafer, and certainly, in other embodiments, wafer 01 can also
For the wafer being made up of other transparent materials.In the present embodiment, the front of CIS chips 02 has pad 021, of pad 021
Number is two, has through hole on pad 021, is filled with conductive material 022 in through hole, i.e., has conductive material on pad 021
022, pad 021 is connected to the back side of CIS chips 02 by conductive material 022, and the front of CIS chips 02 is provided with lenticule 023, such as
Shown in Fig. 4, certainly, in other embodiments, the number of pad 021 can be one, or three even more, roots
Rationally set according to needs.In the present embodiment, as shown in figure 5, preparing some first grooves 011 on wafer 01,
The bottom of one groove 011 prepares the second groove 012, and the width of the second groove 012 is less than the bottom of the first groove 011, CIS chips 02
Outer peripheral width be less than the first groove 011 width, more than the width of the second groove 012, the depth of the first groove 011 is small
In the thickness of CIS chips 02, in other embodiments, shape, depth and the big rootlet of the first groove 011 and the second groove 012
Determined according to CIS chips 02, as long as can guarantee that CIS chips 02 are put into the first groove 011, the energy of lenticule 023 on CIS chips 02
Enough it is put into the second groove 012, rationally sets as needed；Certainly, in other embodiments, can also be in wafer
Some grooves 013 are prepared on 01, as shown in fig. 6, the width of groove 013 is less than the outward flange of CIS chips 02, the shape of groove 013
Shape, depth and size determine according to CIS chips 02, as long as can guarantee that the lenticule 023 on CIS chips 02 can be put into groove
In 013, rationally set as needed.
S012：The inside cavity filling light transmissive material 07 that second groove 012 is formed, in the present embodiment, light transmissive material 07
Packed height be more than the second groove 012 depth, as shown in fig. 7, so CIS chips 02 can be fixed, first is recessed
The bottom of groove 011 and light transmissive material 07 can give CIS chips 02 to provide dual support.Certainly, in other embodiments, printing opacity material
The packed height of material 07 can be equal to the depth of the second groove 012, can so save light transmissive material 07, but for control accuracy
It is it is required that higher；Light transmissive material 07 can also be filled inside the groove 013 of preparation, the packed height of light transmissive material 07 is not less than recessed
The depth of groove 013, rationally set as needed.
S013：CIS chips 02 are inverted on wafer 01, CIS chips 02 are positioned over the bottom of the first groove 011, CIS cores
Lenticule 023 on piece 02 is located in the second groove 012, as shown in Figure 8.In the present embodiment, inside due to the second groove 012
Filled with light transmissive material 07, therefore, after CIS chips 02 post on wafer 01, at appropriate temperatures, in the upper of CIS chips 02
Side provides appropriate pressure, and to enable CIS chips 02 and wafer 01 preferably to combine, the light transmissive material 07 of spilling directly stays in
In the gap of first groove 011 and CIS chips 02, as shown in Figure 8.
S02：It is packaged on wafer 01, the outside of CIS chips 02 forms encapsulated layer 03, as shown in Figure 9.
S03：In order to reduce the package dimension of CIS devices, wafer 01 is thinned.Packaged wafer 01 is overturn,
Make encapsulated layer 03 down, wafer 01 upward, as shown in Figure 10；Reduction processing is carried out after upset, is obtained after being thinned such as Figure 11 institutes
The wafer 01 shown；Will be thinned after wafer 01 overturn again, make encapsulated layer 03 upward, wafer 01 down, as shown in figure 12.
S04：Encapsulated layer 03 is thinned to and exposes conductive material 022.In the present embodiment, in order to reduce the envelope of CIS devices
Size is filled, encapsulated layer 03 can be thinned to and maintained an equal level with the notch of the first groove 011, as shown in figure 13, in encapsulation process, the
For one groove 011 with being filled with encapsulated layer 03 in the gap of CIS chips 02, these encapsulated layers 03 can ensure CIS chips 02 and crystalline substance
Fastness between circle 01；Certainly, in other embodiments, encapsulated layer 03 can be thinned to and maintained an equal level with CIS chips 02, such as schemed
Shown in 14；The optional position between the groove 011 of CIS chips 02 and first is can also be, is rationally set as needed.
S05：Line layer 04 is prepared at the back side of CIS chips 02, line layer 04 is connected with conductive material 022, in line layer 04
Surface prepares insulating barrier 05, and salient point 06 is prepared at the windowing 051 on insulating barrier 05, and salient point 06 is connected with line layer 04, such as schemes
Shown in 15.
S06：Wafer 01 is cut, forms single CIS device.
The method for packing of CIS devices provided by the invention, including CIS chips 02 are inverted on wafer 01, at least CIS cores
The lenticule 023 of piece 02 is embedded in wafer 01, and CIS chips 02 have through hole, and conductive material 022, conduction material are filled with through hole
The positive pad 021 of CIS chips 02 is connected to the back side of CIS chips 02 by material 022；It is packaged on wafer 01, CIS chips
02 outside forms encapsulated layer 03；Encapsulated layer 03 is thinned to the conductive material 022 exposed in through hole；In the back side system of CIS chips 02
Reserve line layer 04, line layer 04 are connected with conductive material 022, insulating barrier 05 are prepared on the surface of line layer 04, on insulating barrier 05
Windowing 051 at prepare salient point 06, salient point 06 is connected with line layer 04.The method for packing of this CIS devices is by CIS flip-chips
It is positioned in wafer, is combined CIS chips with wafer by encapsulating material, with package dimension is small, light transmittance is high, technique
The advantages of simple to operate and production cost is high.
In addition, also providing a kind of CIS devices in the present embodiment, it is prepared using the above method, by above method system
For the semiconductor devices gone out, reliability is high, and package dimension is small, and overall performance is good, and preparation process is simple, and production efficiency is high.
Embodiment 2
Originally apply example and a kind of CIS devices are provided, as shown in figure 16, including wafer layer 01, wafer layer 01 is interior to have the first groove
011 and second groove 012, the width of the second groove 012 be less than the bottom of the first groove 011, in the present embodiment, CIS chips
02 front has pad 021, and the number of pad 021 is two, has through hole on pad 021, conductive material is filled with through hole
022, i.e., there is conductive material 022, pad 021 is connected to the back side of CIS chips 02, CIS by conductive material 022 on pad 021
The front of chip 02 is provided with lenticule 023, and certainly, in other embodiments, the number of pad 021 can be one, can also
It is even more for three, rationally set as needed.The outer peripheral width of CIS chips 02 is less than the first groove 011
Width, more than the width of the second groove 012, the upside-down mounting of CIS chips 02 above the second groove 012 and CIS chips 02 it is micro-
Mirror 023 is embedded in the second groove 012, and the back side of CIS chips 02 and the notch of the first groove 011 maintain an equal level, and the outside of CIS chips 02 has
Encapsulated layer 03, the back side of CIS chips 02 have line layer 04, and line layer 04 is connected with conductive material 022, and the surface of line layer 04 has
Insulating barrier 05, windowing 051 is provided with insulating barrier 05, is provided with salient point 06 at windowing 051, salient point 06 is connected with line layer 04.
The package dimensions of this CIS devices is small, light transmittance is high, it is simple to prepare and production cost is low.
Alternatively, the inside cavity filling light transmissive material 07 that the second groove 012 is formed, as shown in figure 17, light transmissive material 07
CIS chips 02 can be made more firm with wafer layer 01, and the bottom of the first groove 011 and light transmissive material 07 can also be given
CIS chips 02 provide dual support.
Obviously, above-described embodiment is only intended to clearly illustrate example, and is not the restriction to embodiment.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of change or
Change.There is no necessity and possibility to exhaust all the enbodiments.And the obvious change thus extended out or
Among changing still in the protection domain of the invention.
Claims (10)
1. a kind of method for packing of CIS devices, it is characterised in that comprise the following steps：
By CIS flip-chips on wafer, the lenticule of at least described CIS chips is embedded in the wafer, the CIS chips tool
There is through hole, conductive material is filled with the through hole, the pad of the CIS chip front sides is connected to described by the conductive material
The back side of CIS chips；
It is packaged on the wafer, encapsulated layer is formed on the outside of the CIS chips；
The encapsulated layer is thinned to the conductive material exposed in the through hole；
Line layer is prepared in the CIS chip backs, the line layer is connected with the conductive material, in the circuit layer surface
Insulating barrier is prepared, salient point is prepared at the windowing on the insulating barrier, the salient point is connected with the line layer.
2. the method for packing of CIS devices according to claim 1, it is characterised in that described that the CIS flip-chips exist
On wafer, the lenticule of at least described CIS chips is embedded in the step in the wafer, including：
The first groove is prepared on wafer, prepares the second groove in the first bottom portion of groove, the width of second groove is less than institute
The bottom of the first groove is stated, the outer peripheral width of the CIS chips is less than the width of first groove, more than described second
The width of groove；
The CIS chips are positioned over to the bottom of first groove, the CIS chips lenticule is located at second groove
It is interior.
3. the method for packing of CIS devices according to claim 2, it is characterised in that described to be positioned over the CIS chips
Before the bottom of first groove, the inside cavity filling light transmissive material that second groove is formed is additionally included in.
4. the method for packing of CIS devices according to claim 3, it is characterised in that the packed height of the light transmissive material
More than the depth of second groove.
5. according to the method for packing of any described CIS devices of claim 1-4, it is characterised in that described on the wafer
It is packaged, after the step of encapsulated layer is formed on the outside of the CIS chips, in addition to：
The wafer is thinned.
6. the method for packing of CIS devices according to claim 5, it is characterised in that described in the CIS chip back systems
Reserve line layer, the line layer are connected with the conductive material, insulating barrier are prepared in the circuit layer surface, in the insulating barrier
On windowing at prepare salient point, after the step of salient point is connected with the line layer, in addition to：
The wafer is cut, forms single CIS device.
7. a kind of usage right requires CIS devices prepared by 1-6 either method.
8. a kind of CIS devices, it is characterised in that including wafer layer, there is the first groove and the second groove, institute in the wafer layer
The width for stating the second groove is less than the bottom of first groove, and the outer peripheral width of CIS chips is less than first groove
Width, more than the width of second groove, the CIS flip-chips are above second groove and the CIS chips
Lenticule be embedded in second groove, have encapsulated layer on the outside of the CIS chips, have on the CIS chips at least one
Through hole, the inside of the through hole are filled with conductive material, and the conductive material connects the pad of the CIS chips, the CIS cores
The piece back side has line layer, and the line layer is connected with the conductive material, and the circuit layer surface has insulating barrier, described exhausted
Windowing is provided with edge layer, salient point is provided with the windowing, the salient point is connected with the line layer.
9. CIS devices according to claim 8, it is characterised in that the inside cavity filling that second groove is formed is saturating
Luminescent material.
10. CIS devices according to claim 8 or claim 9, it is characterised in that the back side of the CIS chips and described first recessed
The notch of groove maintains an equal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710720105.8A CN107481946B (en) | 2017-08-21 | 2017-08-21 | A kind of packaging method and structure of CIS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710720105.8A CN107481946B (en) | 2017-08-21 | 2017-08-21 | A kind of packaging method and structure of CIS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107481946A true CN107481946A (en) | 2017-12-15 |
| CN107481946B CN107481946B (en) | 2019-09-10 |
Family
ID=60601924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710720105.8A Active CN107481946B (en) | 2017-08-21 | 2017-08-21 | A kind of packaging method and structure of CIS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107481946B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111627947A (en) * | 2020-05-29 | 2020-09-04 | 北京工业大学 | Fan-out type packaging method for CIS chip |
| CN111710615A (en) * | 2020-06-29 | 2020-09-25 | 华天科技（昆山）电子有限公司 | CIS chip packaging structure and packaging method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060006486A1 (en) * | 2004-06-10 | 2006-01-12 | Byoung-Rim Seo | Image sensor package and method of manufacturing the same |
| CN102956653A (en) * | 2011-08-12 | 2013-03-06 | 索尼公司 | Image pickup apparatus and camera module |
| CN103378115A (en) * | 2012-04-18 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Methods and apparatus for glass removal in CMOS image sensors |
| CN104681516A (en) * | 2013-11-27 | 2015-06-03 | 精材科技股份有限公司 | Chip Package And Method For Forming The Same |
| US20160351608A1 (en) * | 2015-05-28 | 2016-12-01 | Xintec Inc. | Chip package and method of manufacturing the same |
-
2017
- 2017-08-21 CN CN201710720105.8A patent/CN107481946B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060006486A1 (en) * | 2004-06-10 | 2006-01-12 | Byoung-Rim Seo | Image sensor package and method of manufacturing the same |
| CN102956653A (en) * | 2011-08-12 | 2013-03-06 | 索尼公司 | Image pickup apparatus and camera module |
| CN103378115A (en) * | 2012-04-18 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Methods and apparatus for glass removal in CMOS image sensors |
| CN104681516A (en) * | 2013-11-27 | 2015-06-03 | 精材科技股份有限公司 | Chip Package And Method For Forming The Same |
| US20160351608A1 (en) * | 2015-05-28 | 2016-12-01 | Xintec Inc. | Chip package and method of manufacturing the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111627947A (en) * | 2020-05-29 | 2020-09-04 | 北京工业大学 | Fan-out type packaging method for CIS chip |
| CN111627947B (en) * | 2020-05-29 | 2023-09-01 | 北京工业大学 | CIS chip fan-out type packaging method |
| CN111710615A (en) * | 2020-06-29 | 2020-09-25 | 华天科技（昆山）电子有限公司 | CIS chip packaging structure and packaging method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107481946B (en) | 2019-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102241388B (en) | MEMS (micro electro mechanical system) wafer-level three-dimensional mixing integration packaging structure and method | |
| CN102856336B (en) | Wafer encapsulation body and forming method thereof | |
| CN105702696B (en) | The encapsulating structure and preparation method thereof of image sensing chip | |
| TWI248202B (en) | Optical device and method for fabricating the same | |
| CN103367382B (en) | A kind of wafer-level packaging method of image sensor chip | |
| CN104078479B (en) | The wafer-level packaging method of imageing sensor and image sensor package structure | |
| WO2021146860A1 (en) | Stacked chip, manufacturing method, image sensor, and electronic device | |
| CN103000648B (en) | Large chip sized package and manufacture method thereof | |
| US20110227226A1 (en) | Multi-chip stack structure having through silicon via | |
| EP1041628A2 (en) | An image sensor ball grid array package and the fabrication thereof | |
| CN101419952A (en) | Wafer stage chip encapsulation method and encapsulation construction | |
| CN104979447B (en) | Flip LED encapsulating structure and production method | |
| TW200536130A (en) | Multiple chip package module having inverted package stacked over die | |
| CN107958881A (en) | A kind of CIS device encapsulation structures and method for packing | |
| JP2009088459A (en) | Wafer-level image sensor module and its manufacturing method, and camera module | |
| TW201232752A (en) | Light-mixing multichip package structure | |
| CN109492622A (en) | For shielding the recognizer component and electronic equipment of lower optical finger print | |
| CN103178023B (en) | Electric hybrid board, the method for packing of semiconductor device and encapsulating structure | |
| CN107481946A (en) | A kind of method for packing and structure of CIS devices | |
| CN108010906A (en) | A kind of package structure of semiconductor device and method for packing | |
| US20210028217A1 (en) | Semiconductor package including an image sensor chip and a method of fabricating the same | |
| TWI407540B (en) | Multi-chip stacked structure having through silicon via and fabrication method thereof | |
| CN105070732A (en) | High-pixel image sensor packaging structure and manufacturing method thereof | |
| CN209086962U (en) | For shielding the recognizer component and electronic equipment of lower optical finger print | |
| CN104409464A (en) | High-reliability image sensor packaging structure with stress protection structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |