CN107481946B - A kind of packaging method and structure of CIS device - Google Patents

A kind of packaging method and structure of CIS device Download PDF

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Publication number
CN107481946B
CN107481946B CN201710720105.8A CN201710720105A CN107481946B CN 107481946 B CN107481946 B CN 107481946B CN 201710720105 A CN201710720105 A CN 201710720105A CN 107481946 B CN107481946 B CN 107481946B
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cis
chip
groove
wafer
layer
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CN107481946A (en
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王训堂
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions

Abstract

The present invention provides the packaging methods and structure of a kind of CIS device, wherein, method include: by CIS flip-chip on wafer, at least in the lenticule insertion wafer of CIS chip, CIS chip has through-hole, conductive material is filled in through-hole, the pad of CIS chip front side is connected to the back side of CIS chip by conductive material;It is packaged on wafer, forms encapsulated layer on the outside of CIS chip;Encapsulated layer is thinned to the conductive material exposed in through-hole;Line layer is prepared in CIS chip back, line layer is connect with conductive material, is prepared insulating layer in route layer surface, salient point is prepared at windowing on the insulating layer, salient point is connect with line layer.CIS chip is placed in wafer by the packaging method of this CIS device, is combined CIS chip with wafer by encapsulating material, has the advantages that package dimension is small, light transmittance is high, technological operation is simple low with production cost.

Description

A kind of packaging method and structure of CIS device
Technical field
The present invention relates to field of semiconductor package, and in particular to a kind of packaging method and structure of CIS device.
Background technique
Microelectronic imaging element is widely used in digital camera (camera), the unlimited device with image store ability Or in other purposes.Microelectronic imaging element includes imaging sensor, and imaging sensor is that optical imagery is converted to telecommunications Number semiconductor devices, generally can be divided into charge-coupled device (Charge Coupled Device, CCD) and complementary metal oxygen Compound semiconductor image sensor (Complementary-Metal-Oxide-Semiconductor Image Sensor, CIS).Cmos image sensor (CIS) utilizes control circuit and signal processing circuit and use around MOS transistor The handoff technique of MOS transistor sequentially detects output, wherein the quantity of MOS transistor is equal to the quantity of pixel, that is, utilizes Light is by watch crystal cover board and light transmission glue, the photosensitive area being irradiated on chip, completes the conversion of optical signal to electric signal, thus The principle of imaging.Cmos image sensor (CIS) can overcome charge-coupled device (CCD) manufacturing process complexity and energy consumption is higher Defect, can be integrated on the same chip by pixel unit array and peripheral circuit using CMOS fabrication technology so that CIS core Piece has the advantages that small in size, light-weight, low-power consumption, programming are convenient, easily controllable and inexpensive.
Traditional CIS device encapsulation includes wafer-level packaging method and chip-scale packaging method, wherein according to packaging technology It is different be divided into again chip size packages (Chip Scale Package, CSP), chip on board encapsulation (Chip On Board, COB), Flip-Chip Using (Flip Chip, FC).Currently, the CIS chip encapsulation technology of mainstream includes COB and CSP.Wafer Grade chip-scale package (Wafer Level Chip Scale Packaging, WLCSP), i.e. wafer stage chip packaged type, Different from traditional chip package mode (first cut and seal survey again, at least increase the volume of former chip 20% after encapsulation), this kind envelope Dress is that packaging and testing is first carried out on full wafer wafer, is then just cut into chip particle one by one, therefore the body after encapsulation Product is equal to the full size of chip bare crystalline, can reduce package dimension, improve integration density and performance.
In wafer scale (Wafer Level) encapsulation process of CSP, traditional CIS device is using first to chip progress Then circuit production coats light transmission glue on chip photosensitive area surface, the mode of glass cover-plate is added to complete the production of CIS device.By In the production that first carry out circuit, consider that later period chip will be bonded with glass cover-plate, the thickness of chip can not be just made It is thin.And due to apply light transmission glue in chip surface, a circle copper wire is also done on chip, so that photosensitive area is formed cavity, increases Chip thickness and technological operation difficulty after encapsulation.
Summary of the invention
Therefore, the technical problem to be solved in the present invention is that overcoming that CIS device package dimension in the prior art is big, light transmission Rate is low, the defect of at least one complex operation and high production cost.
For this purpose, the present invention provides a kind of packaging method of CIS device, include the following steps: CIS flip-chip in wafer On, the lenticule of at least described CIS chip is embedded in the wafer, and the CIS chip has through-hole, is filled in the through-hole The pad of the CIS chip front side is connected to the back side of the CIS chip by conductive material, the conductive material;In the crystalline substance It is packaged on circle, forms encapsulated layer on the outside of the CIS chip;The encapsulated layer is thinned to the conduction exposed in the through-hole Material;Line layer is prepared in the CIS chip back, the line layer is connect with the conductive material, in the line layer table Wheat flour prepares salient point for insulating layer at the windowing on the insulating layer, and the salient point is connect with the line layer.
Optionally, it is described by the CIS flip-chip on wafer, described in the insertion of the lenticule of at least described CIS chip In step in wafer, comprising: the first groove is prepared on wafer, the first bottom portion of groove prepare the second groove, described second The width of groove is less than the bottom of first groove, and the outer peripheral width of the CIS chip is less than first groove Width, greater than the width of second groove;The CIS chip is placed in the bottom of first groove, the CIS chip Lenticule is located in second groove.
It optionally, further include described second before the bottom that the CIS chip is placed in first groove The inside cavity that groove is formed fills translucent material.
Optionally, the packed height of the translucent material is greater than the depth of second groove.
Optionally, described to be packaged on the wafer, after the step of forming encapsulated layer on the outside of the CIS chip, Further include: the wafer is carried out thinned.
Optionally, described to prepare line layer in the CIS chip back, the line layer is connect with the conductive material, Insulating layer is prepared in the route layer surface, salient point, the salient point and the route are prepared at the windowing on the insulating layer After the step of layer connection, further includes: cut the wafer, form single CIS device.
The present invention also provides a kind of CIS devices prepared using the above method.
It is recessed with the first groove and second in the wafer layer the present invention also provides a kind of CIS device, including wafer layer Slot, the width of second groove are less than the bottom of first groove, and the outer peripheral width of CIS chip is less than described first The width of groove, greater than the width of second groove, the CIS flip-chip is above second groove and the CIS The lenticule of chip is embedded in second groove, has encapsulated layer on the outside of the CIS chip, has at least on the CIS chip The inside of one through-hole, the through-hole is filled with conductive material, and the conductive material is connected to the pad of the CIS chip, described CIS chip back has line layer, and the line layer is connect with the conductive material, and the route layer surface has insulating layer, It is provided with windowing on the insulating layer, salient point is provided at the windowing, the salient point is connect with the line layer.
Optionally, the inside cavity that second groove is formed fills translucent material.
Optionally, the notch of the back side of the CIS chip and first groove maintains an equal level.
Technical solution of the present invention has the advantages that
1. the packaging method of CIS device provided by the invention, including by CIS flip-chip on wafer, at least described CIS The lenticule of chip is embedded in the wafer, and the CIS chip has through-hole, and conductive material is filled in the through-hole, described The pad of the CIS chip front side is connected to the back side of the CIS chip by conductive material;It is packaged on the wafer, Encapsulated layer is formed on the outside of the CIS chip;The encapsulated layer is thinned to the conductive material exposed in the through-hole;Described CIS chip back prepares line layer, and the line layer is connect with the conductive material, prepares and insulate in the route layer surface Layer, prepares salient point, the salient point is connect with the line layer at the windowing on the insulating layer.The encapsulation of this CIS device CIS chip is placed in wafer by method, is combined CIS chip with wafer by encapsulating material, small with package dimension, Light transmittance height, the simple advantage low with production cost of technological operation.
2. CIS device provided by the invention, including wafer layer, the wafer layer is interior to have the first groove and the second groove, The width of second groove is less than the bottom of first groove, and it is recessed that the outer peripheral width of CIS chip is less than described first The width of slot, greater than the width of second groove, the CIS flip-chip is above second groove and the CIS core The lenticule of piece is embedded in second groove, has encapsulated layer on the outside of the CIS chip, has at least one on the CIS chip The inside of a through-hole, the through-hole is filled with conductive material, and the conductive material is connected to the pad of the CIS chip, the CIS Chip back has line layer, and the line layer is connect with the conductive material, and the route layer surface has insulating layer, described It is provided with windowing on insulating layer, salient point is provided at the windowing, the salient point is connect with the line layer.This CIS device Package dimension it is small, light transmittance is high, it is simple to prepare and production cost is low.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow chart of a specific example of the packaging method of CIS device in the embodiment of the present invention 1;
Fig. 2 is the flow chart of another specific example of the packaging method of CIS device in the embodiment of the present invention 1;
Fig. 3-Figure 15 is the specific steps schematic diagram of the packaging method of CIS device in the embodiment of the present invention 1;
Figure 16 is the structure chart of a specific example of CIS device in the embodiment of the present invention 2;
Figure 17 is the structure chart of another specific example of CIS device in the embodiment of the present invention 2.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical", The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to Convenient for description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation, It is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.In addition, term " first ", " second ", " third " is used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected;It can To be mechanical connection, it is also possible to be electrically connected;It can be directly connected, can also indirectly connected through an intermediary, it can be with It is the connection inside two elements, can be wireless connection, be also possible to wired connection.For those of ordinary skill in the art For, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.
As long as in addition, the non-structure each other of technical characteristic involved in invention described below different embodiments It can be combined with each other at conflict.
Embodiment 1
The present embodiment provides a kind of packaging method of CIS device, flow chart is as shown in Figure 1.One as the present embodiment Preferred embodiment, flow chart is as shown in Fig. 2, include the following steps:
S011: carrier of the wafer 01 as CIS chip 02 can carry several CIS chips 02, as shown in figure 3, according to The characteristic of CIS chip, in the present embodiment, wafer 01 are glass wafer, and certainly, in other embodiments, wafer 01 can also be with For the wafer being made of other transparent materials.In the present embodiment, 02 front of CIS chip has pad 021, of pad 021 Number is two, has through-hole on pad 021, is filled with conductive material 022 in through-hole, i.e., has conductive material on pad 021 022, pad 021 is connected to the back side of CIS chip 02 by conductive material 022, and 02 front of CIS chip is provided with lenticule 023, such as Shown in Fig. 4, certainly, in other embodiments, the number of pad 021 can be one, or three even more, roots According to needs rationally setting.In the present embodiment, as shown in figure 5, preparing several first grooves 011 on wafer 01, One groove, 011 bottom prepares the second groove 012, bottom of the width less than the first groove 011 of the second groove 012, CIS chip 02 Outer peripheral width less than the width of the first groove 011, greater than the width of the second groove 012, the depth of the first groove 011 is small In the thickness of CIS chip 02, in other embodiments, shape, depth and the big rootlet of the first groove 011 and the second groove 012 It is determined according to CIS chip 02, as long as can guarantee that CIS chip 02 is put into the first groove 011,023 energy of lenticule on CIS chip 02 It is enough put into the second groove 012, as needed rationally setting;It certainly, in other embodiments, can also be in wafer Several grooves 013 are prepared on 01, as shown in fig. 6, the width of groove 013 is less than the outer edge of CIS chip 02, the shape of groove 013 Shape, depth and size are determined according to CIS chip 02, as long as can guarantee that the lenticule 023 on CIS chip 02 can be put into groove In 013, rationally setting as needed.
The inside cavity that S012: the second groove 012 is formed fills translucent material 07, in the present embodiment, translucent material 07 Packed height be greater than the second groove 012 depth, as shown in fig. 7, CIS chip 02 can be fixed in this way, first is recessed The bottom of slot 011 and translucent material 07 can provide dual support to CIS chip 02.Certainly, in other embodiments, light transmission material The packed height of material 07 can be equal to the depth of the second groove 012, can save translucent material 07 in this way, but for controlling precision It is more demanding;Translucent material 07 can also be filled inside the groove 013 of preparation, the packed height of translucent material 07 is not less than recessed The depth of slot 013, as needed rationally setting.
S013: CIS chip 02 is inverted on wafer 01, and CIS chip 02 is placed in the bottom of the first groove 011, CIS core Lenticule 023 on piece 02 is located in the second groove 012, as shown in Figure 8.In the present embodiment, inside due to the second groove 012 Filled with translucent material 07, therefore, after CIS chip 02 posts on wafer 01, at appropriate temperatures, in the upper of CIS chip 02 Side provides appropriate pressure, and to enable CIS chip 02 and wafer 01 preferably to combine, the translucent material 07 of spilling is directly stayed in In the gap of first groove 011 and CIS chip 02, as shown in Figure 8.
S02: being packaged on wafer 01, encapsulated layer 03 is formed on the outside of CIS chip 02, as shown in Figure 9.
S03: the package dimension in order to reduce CIS device carries out wafer 01 thinned.Packaged wafer 01 is overturn, Make encapsulated layer 03 downward, wafer 01 upward, as shown in Figure 10;Reduction processing is carried out after overturning, is obtained after being thinned such as Figure 11 institute The wafer 01 shown;Will be thinned after wafer 01 overturn again, make encapsulated layer 03 upward, wafer 01 downward, as shown in figure 12.
S04: encapsulated layer 03 is thinned to and exposes conductive material 022.In the present embodiment, in order to reduce the envelope of CIS device Size is filled, encapsulated layer 03 can be thinned to and be maintained an equal level with the notch of the first groove 011, as shown in figure 13, in encapsulation process, the It is filled with encapsulated layer 03 in one groove 011 and the gap of CIS chip 02, these encapsulated layers 03 can guarantee CIS chip 02 and crystalline substance Fastness between circle 01;Certainly, in other embodiments, encapsulated layer 03 can be thinned to and is maintained an equal level with CIS chip 02, such as schemed Shown in 14;It can also be any position between CIS chip 02 and the first groove 011, as needed rationally setting.
S05: line layer 04 is prepared at 02 back side of CIS chip, line layer 04 is connect with conductive material 022, in line layer 04 Surface prepares insulating layer 05, and salient point 06 is prepared at the windowing 051 on insulating layer 05, and salient point 06 is connect with line layer 04, such as schemes Shown in 15.
S06: wafer 01 is cut, and forms single CIS device.
The packaging method of CIS device provided by the invention, including CIS chip 02 is inverted on wafer 01, at least CIS core The lenticule 023 of piece 02 is embedded in wafer 01, and CIS chip 02 has through-hole, is filled with conductive material 022, conduction material in through-hole The positive pad 021 of CIS chip 02 is connected to the back side of CIS chip 02 by material 022;It is packaged on wafer 01, CIS chip 02 outside forms encapsulated layer 03;Encapsulated layer 03 is thinned to the conductive material 022 exposed in through-hole;In 02 back side system of CIS chip Reserve line layer 04, line layer 04 are connect with conductive material 022, insulating layer 05 are prepared on 04 surface of line layer, on insulating layer 05 Windowing 051 at prepare salient point 06, salient point 06 is connect with line layer 04.The packaging method of this CIS device is by CIS flip-chip It is placed in wafer, is combined CIS chip with wafer by encapsulating material, with package dimension is small, light transmittance is high, technique The advantages of easy to operate and high production cost.
In addition, also providing a kind of CIS device in the present embodiment, it is prepared using the above method, by above method system Standby semiconductor devices out, high reliablity, package dimension is small, and overall performance is good, and preparation process is simple, high production efficiency.
Embodiment 2
Originally it applies example and a kind of CIS device is provided, as shown in figure 16, including wafer layer 01, wafer layer 01 is interior to have the first groove 011 and second groove 012, the width of the second groove 012 less than the first groove 011 bottom, in the present embodiment, CIS chip 02 front has pad 021, and the number of pad 021 is two, has through-hole on pad 021, is filled with conductive material in through-hole 022, i.e., there is conductive material 022, pad 021 is connected to the back side of CIS chip 02, CIS by conductive material 022 on pad 021 02 front of chip is provided with lenticule 023, and certainly, in other embodiments, the number of pad 021 can be one, can also be with It is even more for three, rationally setting as needed.The outer peripheral width of CIS chip 02 is less than the first groove 011 Width, greater than the width of the second groove 012,02 upside-down mounting of CIS chip above the second groove 012 and CIS chip 02 it is micro- Mirror 023 is embedded in the second groove 012, and the notch of the back side of CIS chip 02 and the first groove 011 maintains an equal level, and is had on the outside of CIS chip 02 Encapsulated layer 03,02 back side of CIS chip have line layer 04, and line layer 04 is connect with conductive material 022, and 04 surface of line layer has Insulating layer 05 is provided with windowing 051 on insulating layer 05, is provided with salient point 06 at windowing 051, salient point 06 is connect with line layer 04. The package dimension of this CIS device is small, light transmittance is high, it is simple to prepare and production cost is low.
Optionally, the inside cavity that the second groove 012 is formed fills translucent material 07, as shown in figure 17, translucent material 07 CIS chip 02 and wafer layer 01 can be made stronger, and the bottom of the first groove 011 and translucent material 07 can also give CIS chip 02 provides dual support.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or It changes still within the protection scope of the invention.

Claims (9)

1. a kind of packaging method of CIS device, which comprises the steps of:
By CIS flip-chip on wafer, the lenticule of at least described CIS chip is embedded in the wafer, the CIS chip tool There is through-hole, conductive material is filled in the through-hole, the pad of the CIS chip front side is connected to described by the conductive material The back side of CIS chip;
It is packaged on the wafer, forms encapsulated layer on the outside of the CIS chip;
The encapsulated layer is thinned to the conductive material exposed in the through-hole;
Line layer is prepared in the CIS chip back, the line layer is connect with the conductive material, in the route layer surface Insulating layer is prepared, salient point is prepared at the windowing on the insulating layer, the salient point is connect with the line layer;
It is described by the CIS flip-chip on wafer, the lenticule of at least described CIS chip is embedded in the step in the wafer In, comprising: the first groove is prepared on wafer, prepares the second groove in the first bottom portion of groove, the width of second groove is small In the bottom of first groove, the outer peripheral width of the CIS chip is less than the width of first groove, is greater than described The width of second groove;The CIS chip is placed in the bottom of first groove, the CIS chip lenticule is located at institute It states in the second groove;
Alternatively, it is described by the CIS flip-chip on wafer, the lenticule of at least described CIS chip is embedded in the wafer The step of in, comprising: prepared on wafer groove (013), the width of groove (013) is less than the outer edge of CIS chip, CIS core The lenticule of on piece is located in groove (013).
2. the packaging method of CIS device according to claim 1, which is characterized in that described to be placed in the CIS chip It further include that the inside cavity formed in second groove fills translucent material before the bottom of first groove.
3. the packaging method of CIS device according to claim 2, which is characterized in that the packed height of the translucent material Greater than the depth of second groove.
4. the packaging method of CIS device according to claim 1 to 3, which is characterized in that described on the wafer After the step of being packaged, forming encapsulated layer on the outside of the CIS chip, further includes:
The wafer is carried out thinned.
5. the packaging method of CIS device according to claim 4, which is characterized in that described in the CIS chip back system Reserve line layer, the line layer are connect with the conductive material, insulating layer are prepared in the route layer surface, in the insulating layer On windowing at prepare salient point, after the step of salient point is connect with the line layer, further includes:
The wafer is cut, single CIS device is formed.
6. a kind of CIS device prepared using claim 1-5 either method.
7. a kind of CIS device, which is characterized in that including wafer layer, there is the first groove and the second groove, institute in the wafer layer The width for stating the second groove is less than the bottom of first groove, and the outer peripheral width of CIS chip is less than first groove Width, greater than the width of second groove, the CIS flip-chip is above second groove and the CIS chip Lenticule be embedded in second groove, have encapsulated layer on the outside of the CIS chip, there is at least one on the CIS chip The inside of through-hole, the through-hole is filled with conductive material, and the conductive material is connected to the pad of the CIS chip, the CIS core The piece back side has line layer, and the line layer is connect with the conductive material, and the route layer surface has insulating layer, described exhausted It is provided with windowing in edge layer, salient point is provided at the windowing, the salient point is connect with the line layer.
8. CIS device according to claim 7, which is characterized in that the inside cavity filling that second groove is formed is saturating Luminescent material.
9. CIS device according to claim 7 or 8, which is characterized in that the back side of the CIS chip and described first recessed The notch of slot maintains an equal level.
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CN111627947B (en) * 2020-05-29 2023-09-01 北京工业大学 CIS chip fan-out type packaging method
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