CN107464845A - A kind of FET MOS device - Google Patents
A kind of FET MOS device Download PDFInfo
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- CN107464845A CN107464845A CN201610391408.5A CN201610391408A CN107464845A CN 107464845 A CN107464845 A CN 107464845A CN 201610391408 A CN201610391408 A CN 201610391408A CN 107464845 A CN107464845 A CN 107464845A
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 105
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 105
- 239000001301 oxygen Substances 0.000 claims abstract description 105
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 238000000034 method Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a kind of FET MOS device, including：P type substrate, the first p-well region being arranged in P type substrate and polysilicon layer, wherein polysilicon layer are formed as the symmetrical structure of the first center line in the first direction；Relative to the first center line, polysilicon layer includes Part I, Part II and the Part III between Part I and Part II positioned at the first center line both sides, wherein Part I is covered in first oxygen layer, and Part II is covered in second oxygen layer；The first grid oxide layer is formed between Part III and P type substrate；The MOS device also includes：It is respectively arranged at polysilicon layer both sides and on the first center line is symmetrical, the first N well regions and the 2nd N well regions in P type substrate, wherein first oxygen layer is located on the first N well regions, second oxygen layer is located on the 2nd N well regions；The present invention is solved after grid accesses high voltage, and field oxygen parasitic components can be also switched on, the problem of influenceing expectation function.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of FET MOS device.
Background technology
For FET (MOS) power management chip, it usually needs possessing can high voltage bearing high pressure
Device and relatively low low-voltage device is opened, high tension apparatus is used for power input, and low-voltage device is used for arithmetic logic.
And high tension apparatus be not only to drain can it is high pressure resistant, grid is also required to high pressure resistant；Grid is pressure-resistant generally to be passed through
Gate oxide thickness is lifted to realize, but during practical application, after grid accesses high voltage, tradition
The field oxygen parasitic components of device can be also switched on, and cause device current to become big suddenly, and then influence expected work(
Energy.
The content of the invention
The invention provides a kind of FET MOS device, its purpose is to solve MOS device
After grid access high voltage, field oxygen parasitic components are switched on, the problem of influenceing expectation function.
In order to achieve the above object, the embodiment provides a kind of FET MOS device, bag
Include：
P type substrate, the first p-well region being arranged in P type substrate and polysilicon layer, wherein polysilicon layer shape
As the symmetrical structure of the first center line in the first direction；
Relative to the first center line, polysilicon layer includes the Part I positioned at the first center line both sides, second
Part and the Part III between Part I and Part II, wherein Part I are covered in first
In the oxygen layer of field, Part II is covered in second oxygen layer；First is formed between Part III and P type substrate
Grid oxide layer；
The MOS device also includes：
Be respectively arranged at polysilicon layer both sides and on the first center line it is symmetrical, in P type substrate
First N well regions and the 2nd N well regions, wherein first oxygen layer is located on the first N well regions, second oxygen layer
On the 2nd N well regions；
The first N-type heavily doped region symmetrical on the first center line, the second N-type heavily doped region,
First N-type heavily doped region is located in the first N well regions and is connected with first oxygen layer, and the second N-type is heavily doped
Miscellaneous region is located in the 2nd N well regions and is connected with second oxygen layer.
Preferably, polysilicon layer is also formed as the second center line phase along the second direction vertical with first direction
Symmetrical structure；
Relative to the second center line, polysilicon layer includes：
Positioned at the Part IV of the second center line both sides, Part V and positioned at Part IV and Part V
Between Part VI, Part IV is covered in the 3rd oxygen layer, and Part V is covered in the 4th oxygen layer
On；The second grid oxide layer is formed between Part VI and P type substrate；
The MOS device also includes：
Be respectively arranged at polysilicon layer both sides and on the second center line it is symmetrical, in P type substrate
3rd N well regions, the 4th N well regions, the 3rd oxygen layer are located on the 3rd N well regions, and the 4th oxygen layer is located at
On 4th N well regions；
The threeth N-type heavily doped region symmetrical on the second center line, the 4th N-type heavily doped region,
3rd N-type heavily doped region is located in the 3rd N well regions and is connected with the 3rd oxygen layer, and the 4th N-type is heavily doped
Miscellaneous region is located in the 4th N well regions and is connected with the 3rd oxygen layer.
Preferably, the MOS device also includes：
The 5th oxygen layer being connected with the first N-type heavily doped region, the center line and the first N of the 5th oxygen layer
The first end overlapping margins of well region, the first end of the first N well regions is one end away from the first center line；
The 6th oxygen layer being connected with the second N-type heavily doped region, the center line and the 2nd N of the 6th oxygen layer
The first end overlapping margins of well region, the first end of the 2nd N well regions is one end away from the first center line.
Preferably, the distance on the border at first second end of the oxygen layer away from the first N well regions is the first present count
Value, the second end of the first N well regions is close to one end of the first center line；
The distance on the border at second second end of the oxygen layer away from the 2nd N well regions is the first default value, the 2nd N
Second end of well region is close to one end of the first center line.
Preferably, the MOS device also includes：
It is arranged at first p-type heavily doped region of the 5th oxygen layer away from the first center line side；
And it is arranged at second p-type heavily doped region of the 6th oxygen layer away from the first center line side；
And first p-type heavily doped region and the second p-type heavily doped region be respectively relative to the first center line pair
Claim distribution.
Preferably, first oxygen layer, the thickness of second oxygen layer are 6000 angstroms.
Preferably, the thickness of polysilicon layer is 2000~3000 angstroms.
Preferably, the thickness of the first grid oxide layer is 800~1000 angstroms.
Preferably, the span of the first default value is between 0.6 micron~1 micron.
Preferably, the width on the direction vertical with first direction of Part I, the edge of Part II is
Two default values, first oxygen layer, the width of second oxygen layer are the 3rd default value；Wherein,
The ratio of second default value and the 3rd default value is 3：5.
The such scheme of the present invention comprises at least following beneficial effect：
The MOS device that embodiments of the invention provide, the structure that polysilicon layer overlaps with field oxygen layer only exist
On N well regions, and it is not present on p-well region, it is thus eliminated that the generation of parasitic fields tube device, and channel region
The p-well region in domain is existed only under the first grid oxide layer, and is not present under an oxygen, avoids parasitic fields pipe device
The phenomenon that part is opened occurs, and then lifts stability when MOS device works, and solves when grid accesses
After high voltage, the field oxygen parasitic components of traditional devices can be also switched on, and cause device current to become big suddenly,
And then the problem of influenceing expectation function.
Brief description of the drawings
Fig. 1 represents the structural representation of MOS device first direction provided in an embodiment of the present invention；
The structural representation and first direction of one of Fig. 2 expressions MOS device provided in an embodiment of the present invention,
Second direction schematic diagram；
Fig. 3 represents two structural representation of MOS device provided in an embodiment of the present invention；
Fig. 4 represents one of process chart of MOS device provided in an embodiment of the present invention；
Fig. 5 represents the two of the process chart of MOS device provided in an embodiment of the present invention；
Fig. 6 represents the three of the process chart of MOS device provided in an embodiment of the present invention；
Fig. 7 represents the four of the process chart of MOS device provided in an embodiment of the present invention.
Description of reference numerals：
1st, P type substrate；2nd, polysilicon layer；21st, Part I, 22, Part II, 23, the 3rd
Point；3rd, the first center line；4th, first oxygen layer；5th, second oxygen layer；6th, the first grid oxide layer；7、
First N well regions；8th, the 2nd N well regions；9th, the first N-type heavily doped region；10th, the second N-type is heavily doped
Miscellaneous region；11st, the 5th oxygen layer；12nd, the 6th oxygen layer；13rd, the first p-type heavily doped region；14、
Second p-type heavily doped region；15th, the first p-well region.
Embodiment
To make the technical problem to be solved in the present invention, technical scheme and advantage clearer, below in conjunction with attached
Figure and specific embodiment are described in detail.
The present invention is directed to the problem of existing, there is provided a kind of FET MOS device.
Referring to Fig. 1 and Fig. 2, the embodiment provides a kind of FET MOS device, including：
P type substrate 1, the first p-well region 15 being arranged in P type substrate 1 and polysilicon layer 2, wherein,
The first center line 3 that polysilicon layer 2 is formed as (X-direction in Fig. 2) in the first direction is symmetrical
Structure；Wherein, the thickness of polysilicon layer 2 be 2000~3000 angstroms, by P type substrate 1 photoetching,
Implanted dopant, high temperature, which push away trap, makes magazine be diffuseed to form in P type substrate 1.
Relative to the first center line 3, polysilicon layer 2 includes the Part I positioned at the both sides of the first center line 3
21st, Part II 22 and the Part III 23 between Part I 21 and Part II 22, its
In, grid of the polysilicon layer 2 as MOS device；Part I 21 is covered in first oxygen layer 4,
Part II 22 is covered in second oxygen layer 5, in order in first oxygen layer 4, second
Field plate is formed respectively in oxygen layer 5；The first grid oxide layer 6 is formed between Part III 23 and P type substrate 1；
First grid oxide layer 6 is formed by gate oxidation, and thickness is 800~1000 angstroms；First oxygen layer 4, second
The thickness of oxygen layer 5 is 6000 angstroms.
Width on the direction vertical with first direction of Part I 21, the edge of Part II 22 is (in Fig. 2
C) it is the second default value, the width (D in Fig. 2) of first oxygen layer, 4, second oxygen layer 5 is
For the 3rd default value；Wherein,
The ratio of second default value and the 3rd default value is 3：5, i.e. Part I 21 is covered in first
The ratio between width of width and first oxygen layer 4 in the oxygen layer 4 of field is 3：5, i.e. Part II 22 is covered in
The ratio between width of width and first oxygen layer 4 in second oxygen layer 5 is 3：5.
The MOS device also includes：
Be respectively arranged at the both sides of polysilicon layer 2 and on the first center line it is 3 symmetrical, positioned at P type substrate
The first N well regions 7 and the 2nd N well regions 8 on 1, wherein first oxygen layer 4 is located at the first N well regions 7
On, second oxygen layer 5 is located on the 2nd N well regions 8；
Wherein, the structure that polysilicon layer 2 overlaps with field oxygen layer (first oxygen layer, 4, second oxygen layer 5)
Only exist on the first N well regions 7 and the 2nd N well regions 8, and be not present on the first p-well region 15, because
This eliminates the generation (polysilicon+field oxygen+p-well, forming parasitic fields tube device) of parasitic fields tube device, enters
And lift stability when MOS device works.
Wherein, the distance on the border at first second end of the oxygen layer 4 away from the first N well regions 7 is first default
Numerical value, the second end of the first N well regions 7 is close to one end of the first center line 3；
The distance on the border at second second end of the oxygen layer 5 away from the 2nd N well regions 8 is the first default value (figure
B in 2), the second end of the 2nd N well regions 8 is close to one end of the first center line 3；First default value
Span between 0.6 micron~1 micron.
The first N-type heavily doped region (source as MOS device symmetrical on the first center line 3
Pole), the second N-type heavily doped region 10 (drain electrode as MOS device), the first N-type heavily doped region
Domain 9 is connected in the first N well regions 7 and with first oxygen layer 4, the second N-type heavily doped region 10
It is connected in the 2nd N well regions 8 and with second oxygen layer 5, wherein, channel region (source electrode and drain electrode
Between) p-well region exist only under the first grid oxide layer 6, and be not present under an oxygen, avoid parasitic fields
The phenomenon that tube device is opened occurs.
Preferably, the MOS device also includes：
The 5th oxygen layer 11 being connected with the first N-type heavily doped region 9, the center line of the 5th oxygen layer 11
With the first end overlapping margins of the first N well regions 7, the first end of the first N well regions 7 is away from the first center
One end of line 3；
The 6th oxygen layer 12 being connected with the second N-type heavily doped region 10, the center of the 6th oxygen layer 12
The first end overlapping margins of line and the 2nd N well regions 8, the first ends of the 2nd N well regions 8 are away from first
E is equal with F numerical value in one end of heart line 3, i.e. Fig. 2.
Preferably, the MOS device also includes：
It is arranged at first p-type heavily doped region 13 of the 5th oxygen layer 11 away from the side of the first center line 3；
And it is arranged at second p-type heavily doped region of the 6th oxygen layer 12 away from the side of the first center line 3
14；
And first p-type heavily doped region 13 and the second p-type heavily doped region 14 be respectively relative in first
Heart line 3 is symmetrical.
Referring to the structural representation of one of Fig. 2, embodiments of the invention MOS device provided, polysilicon
Layer 2 is also formed as along the symmetrical structure of the second center line of the second direction vertical with first direction, Fig. 2
Middle X-direction is first direction, and Y-direction is second direction, wherein, NW represents N well regions, and PW is represented
P-well region, Poly represent polysilicon layer, and N+ represents N-type heavily doped region, and P+ represents p-type heavily doped region
Domain；
Referring to Y-direction schematic diagram in Fig. 2, relative to the second center line, polysilicon layer 2 includes：
Positioned at the Part IV of the second center line both sides, Part V and positioned at Part IV and Part V
Between Part VI, Part IV is covered in the 3rd oxygen layer, and Part V is covered in the 4th oxygen layer
On；The second grid oxide layer is formed between Part VI and P type substrate 1；
MOS device also includes：
Be respectively arranged at the both sides of polysilicon layer 2 and on the second center line it is symmetrical, positioned at P type substrate 1
On the 3rd N well regions, the 4th N well regions, the 3rd oxygen layer be located on the 3rd N well regions, the 4th oxygen layer
On the 4th N well regions；
The threeth N-type heavily doped region symmetrical on the second center line, the 4th N-type heavily doped region,
3rd N-type heavily doped region is located in the 3rd N well regions and is connected with the 3rd oxygen layer, and the 4th N-type is heavily doped
Miscellaneous region is located in the 4th N well regions and is connected with the 3rd oxygen layer.
Wherein, polysilicon layer 2 is only deposited with the structure that field oxygen layer (the 3rd oxygen layer, the 4th oxygen layer) overlaps
On the 3rd N well regions and the 4th N well regions, and it is not present on p-well region, it is thus eliminated that parasitic fields
The generation (polysilicon+field oxygen+p-well, forming parasitic fields tube device) of tube device, and then lift MOS device
Stability during work.
It is understood that X is identical with Fig. 1 to schematic diagram in Fig. 2, embodiments of the invention are herein not
Repeat again.
Referring to two structural representation of Fig. 3, embodiments of the invention MOS device provided；Relative to
N-type heavily doped region, the structure of p-type heavily doped region are fillet in Fig. 2, Fig. 3, first direction,
The cross-section structure in two directions is identical with Fig. 2, and embodiments of the invention will not be repeated here.
The technological process to the MOS device of the embodiment of the present invention is illustrated below below：
(1) referring to Fig. 4, trap is pushed away to P type substrate 1 (P sub in figure) photoetching, injection, high temperature successively
Process first in the first NW of upper formation (N traps) and the first PW (p-well), the purpose of high temperature pushes away trap be make it is miscellaneous
Matter spreads in P type substrate 1.
(2) referring to Fig. 5, the field oxygen for isolation is formed by way of selective oxidation (LOCOS)
(FOX), thickness is 6000 angstroms.
(3) referring to Fig. 6, grid are carried out to the P type substrate 1 between first oxygen layer, 4, second oxygen layer 5
Oxidation, the first grid oxide layer 6 is formed, and carry out polysilicon deposit, form polysilicon layer 2, wherein, polycrystalline
Silicon layer 2 is covered on the first grid oxide layer 6 and on second oxygen layer 5.
(4) referring to Fig. 7, N+ photoetching, injection and P+ photoetching, injection are carried out；P+ in PW is
Substrate contact, the N+ in NW are source electrode, and NW is the resistance to nip of high pressure, and the N+ in NW is drain contact,
Poly is grid, and the purpose that poly is taken on FOX improves pressure-resistant to form field plate.
It should be noted that the technological process on the right side of the first center line 3 is only illustrated in Fig. 4-7, left side
Technological process is identical with right side, and embodiments of the invention will not be repeated here.
Described above is the preferred embodiment of the present invention, it is noted that for the common skill of the art
For art personnel, on the premise of principle of the present invention is not departed from, some improvements and modifications can also be made,
These improvements and modifications also should be regarded as protection scope of the present invention.
Claims (10)
- A kind of 1. FET MOS device, it is characterised in that including：P type substrate, the first p-well region being arranged in the P type substrate and polysilicon layer, wherein described more Crystal silicon layer is formed as the symmetrical structure of the first center line in the first direction；Relative to first center line, the polysilicon layer includes the positioned at the first center line both sides A part, Part II and the Part III between the Part I and the Part II, its Described in Part I be covered in first oxygen layer, the Part II is covered in second oxygen layer；Institute State and the first grid oxide layer is formed between Part III and the P type substrate；The MOS device also includes：Be respectively arranged at the polysilicon layer both sides and on first center line it is symmetrical, positioned at described The first N well regions and the 2nd N well regions in P type substrate, wherein first oxygen layer is located at the first N traps Qu Shang, second oxygen layer are located on the 2nd N well regions；The first N-type heavily doped region symmetrical on first center line, the second N-type heavy doping Region, the first N-type heavily doped region be located in the first N well regions and with first oxygen layer Connection, the second N-type heavily doped region be located at the 2nd N well regions it is interior and with second oxygen layer Connection.
- 2. MOS device according to claim 1, it is characterised in that the polysilicon layer also shape As the symmetrical structure of the second center line of the edge second direction vertical with the first direction；Relative to second center line, the polysilicon layer includes：Positioned at the Part IV of the second center line both sides, Part V and positioned at the Part IV and Part VI between the Part V, the Part IV are covered in the 3rd oxygen layer, and the described 5th Part is covered in the 4th oxygen layer；The second grid oxide layer is formed between the Part VI and the P type substrate；The MOS device also includes：Be respectively arranged at the polysilicon layer both sides and on second center line it is symmetrical, positioned at P The 3rd N well regions, the 4th N well regions on type substrate, the 3rd oxygen layer are located on the 3rd N well regions, 4th oxygen layer is located on the 4th N well regions；The threeth N-type heavily doped region symmetrical on second center line, the 4th N-type heavy doping Region, the 3rd N-type heavily doped region be located in the 3rd N well regions and with the 3rd oxygen layer Connection, the 4th N-type heavily doped region be located at the 4th N well regions it is interior and with the 3rd oxygen layer Connection.
- 3. MOS device according to claim 1, it is characterised in that the MOS device is also wrapped Include：The 5th oxygen layer being connected with the first N-type heavily doped region, the center of the 5th oxygen layer The first end overlapping margins of line and the first N well regions, the first end of the first N well regions is away from institute State one end of the first center line；The 6th oxygen layer being connected with the second N-type heavily doped region, the center of the 6th oxygen layer The first end overlapping margins of line and the 2nd N well regions, the first end of the 2nd N well regions is away from institute State one end of the first center line.
- 4. MOS device according to claim 1, it is characterised in that first oxygen layer away from The distance on the border at the second end of the first N well regions is the first default value, the first N well regions Second end is close to one end of first center line；The distance on the border at second end of second oxygen layer away from the 2nd N well regions is described first pre- If numerical value, the second end of the 2nd N well regions is close to one end of first center line.
- 5. MOS device according to claim 3, it is characterised in that the MOS device is also wrapped Include：It is arranged at the first p-type heavily doped region of the 5th oxygen layer away from the first center line side；And it is arranged at the second p-type heavy doping of the 6th oxygen layer away from the first center line side Region；And the first p-type heavily doped region and the second p-type heavily doped region be respectively relative to it is described First center line is symmetrical.
- 6. MOS device according to claim 1, it is characterised in that first oxygen layer, The thickness of second oxygen layer is 6000 angstroms.
- 7. MOS device according to claim 1, it is characterised in that the thickness of the polysilicon layer Spend for 2000~3000 angstroms.
- 8. MOS device according to claim 1, it is characterised in that first grid oxide layer Thickness is 800~1000 angstroms.
- 9. MOS device according to claim 4, it is characterised in that first default value Span between 0.6 micron~1 micron.
- 10. MOS device according to claim 1, it is characterised in that the Part I, Width on the direction vertical with the first direction of the edge of two parts is the second default value, and described first Field oxygen layer, the width of second oxygen layer are the 3rd default value；Wherein,The ratio of second default value and the 3rd default value is 3：5.
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| CN201610391408.5A CN107464845A (en) | 2016-06-06 | 2016-06-06 | A kind of FET MOS device |
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| CN201610391408.5A CN107464845A (en) | 2016-06-06 | 2016-06-06 | A kind of FET MOS device |
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| CN103280462A (en) * | 2013-05-27 | 2013-09-04 | 东南大学 | High-robustness P type symmetric laterally double-diffused field effect transistor |
| CN103617996A (en) * | 2013-12-09 | 2014-03-05 | 江南大学 | ESD protective device with high-holding-current annular VDMOS structure |
| CN203659860U (en) * | 2013-12-13 | 2014-06-18 | 江南大学 | Doubly anti-latch-up type high-voltage ESD protection device of annular LDMOS-SCR structure |
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2016
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| US20070108602A1 (en) * | 2005-11-16 | 2007-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | MOS device with a high voltage isolation structure |
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| CN103617996A (en) * | 2013-12-09 | 2014-03-05 | 江南大学 | ESD protective device with high-holding-current annular VDMOS structure |
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Application publication date: 20171212 |