CN107463521B - Solid state disk control device and method - Google Patents
Solid state disk control device and method Download PDFInfo
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- CN107463521B CN107463521B CN201610395495.1A CN201610395495A CN107463521B CN 107463521 B CN107463521 B CN 107463521B CN 201610395495 A CN201610395495 A CN 201610395495A CN 107463521 B CN107463521 B CN 107463521B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
Abstract
The invention discloses a solid state disk control device and a control method, wherein the control device comprises: a multi-interface compatible physical layer circuit for generating a physical layer output signal according to the serial/deserialized receive signal; the input/output circuit is used for generating at least one terminal output signal according to the signal change of at least one terminal; and the processing circuit is used for enabling the operation mode of the solid state disk control device to be suitable for one of multiple interface types according to the physical layer output signal and/or the at least one terminal output signal.
Description
Technical Field
The present invention relates to an interface detection technology, and more particularly, to a solid state disk control device and method capable of detecting an interface type.
Background
The conventional solid state disk interface is a Serial Advanced Technology Attachment (SATA) interface. However, since the transmission speed of the SATA interface gradually fails to meet the requirement of high-speed transmission, some solid state disks instead use a Peripheral Component Interconnect Express (PCI-Express) interface.
To increase compatibility, some solid state disks can support SATA interfaces and PCI-Express interfaces, such solid state disks set a voltage level of a specific pin, so that a host can assign Configuration (Configuration) of a port connected to the solid state disk by detecting the voltage level of the pin, however, after the host completes Configuration of the port, if the operating mode of the solid state disk is changed from a first mode (e.g., SATA mode) to a second mode (e.g., PCI-Express mode) or another solid state disk is replaced with the solid state disk to support only the second mode, the host does not change Configuration accordingly, so that the solid state disk or the another solid state disk cannot be normally connected to the host. In another case, the solid state disk operates in a predetermined mode (e.g., the first or second mode) by setting the level of the pin, but a host connected to the solid state disk does not have a function of detecting the pin, and the host configures a port connected to the solid state disk to be incompatible with the predetermined mode, so that the solid state disk cannot be normally connected to the host.
Some of the prior art is described in the following documents:
(1)”PCI Express M.2Specification”,Revision 0.7,Version 1.0,November27,2012,PP.150(pin 69PEDET)；
(2)“Serial ATA Revision 3.3”,Gold Revision,February 2,2016,PP.214(pinposition 69[Config_1])&PP.215(Table 27)。
disclosure of Invention
In view of the problems of the prior art, an object of the present invention is to provide a solid state disk control apparatus and method, which can perform interface detection from the apparatus side, thereby improving the prior art.
The invention discloses a solid state disk control device, one embodiment of which comprises a multi-interface compatible physical layer circuit, an input/output circuit and a processing circuit. The multi-interface compatible physical layer circuit is used for generating a physical layer output signal according to the serial/deserializing receiving signal. The input-output circuit is used for generating at least one terminal output signal according to the signal change of at least one terminal. The processing circuit is used for enabling the operation mode of the solid state disk control device to be suitable for one of multiple interface types according to at least one of the physical layer output signal and the at least one terminal output signal.
The present invention further discloses a solid state disk control method executed by a solid state disk control device, wherein an embodiment of the control method makes the solid state disk control device compatible with a plurality of interface types, and comprises the following steps: generating a physical layer output signal according to the received signal; generating at least one terminal output signal according to the signal change of at least one terminal; and enabling the operation mode of the solid state disk control device to be suitable for one of the plurality of interface types according to at least one of the physical layer output signal and the at least one terminal output signal.
The features, operation and function of the present invention will be described in detail with reference to the drawings.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a solid state drive control apparatus of the present invention;
FIG. 2 is a schematic diagram of the present invention for detecting SerDes received signals that conform to the PCI-Express specification;
FIG. 3 is a diagram of detecting a SerDes received signal that conforms to the SATA specification in accordance with the present invention;
FIG. 4 is a schematic diagram of another embodiment of a solid state drive control apparatus of the present invention;
FIG. 5 is a waveform diagram of a terminal output signal conforming to the PCI-Express specification; and
fig. 6 is a flowchart of an embodiment of a solid state disk control method of the present invention.
Detailed Description
The following description is made with reference to the common usage in the art, and if the present specification explains or defines a part of the terms, the explanation of the part of the terms is based on the explanation or definition in the present specification.
The present disclosure includes solid state drive control devices and methods, some of which individually may be known components, and the details of which are omitted from the following description without affecting the requirements of the disclosure and the feasibility of implementation. In addition, the method of the present invention may be implemented in software and/or firmware, and may be implemented by the apparatus of the present invention or an equivalent apparatus.
Please refer to fig. 1, which is a schematic diagram of a Solid State Drive (SSD) Controller according to an embodiment of the invention. The solid state disk control apparatus 100 of fig. 1 is compatible with a plurality of interface types, and therefore includes a Physical Layer (Physical Layer) and a Protocol Layer (Protocol Layer) of the plurality of interface types, the Protocol Layer being a Layer above the Physical Layer, such as a Data Link Layer (Data Link Layer), a Data processing Layer (Data transaction Layer), and the like, and the plurality of interface types are, for example only, a peripheral component Interconnect Express (PCI-Express) interface, a Serial Advanced Technology Attachment (SATA) interface, and the like, and are not intended to limit the scope of the present invention.
As shown in fig. 1, the solid state disk control apparatus 100 includes: a Multi-Interface Compatible Physical Layer (MIC-PHY) circuit 110; an Input/Output (I/O) circuit 120; a Processing Circuit (Processing Circuit) 130; and a Media Access Control (MAC) circuit 140.
Referring to fig. 1, the multi-interface-compatible phy circuit 110 includes a phy layer of the aforementioned multiple interface types for generating a phy output signal according to a received signal, in this embodiment, the received signal is a seradizer/Deserializer (SerDes) received signal, since SerDes is a conventional technique in the art, a single-ended bus signal with a large bit width can be compressed into one or more differential signals, and the frequency of the one or more differential signals is higher than that of the single-ended bus signal, the SerDes received signal has a specific meaning for those skilled in the art, and is not an arbitrary signal, however, the present invention is not limited to SerDes received signals.
Referring to fig. 1, the input/output circuit 120 is used for generating at least one terminal output signal according to a signal variation of at least one terminal (or at least one pin), in this embodiment, the number of the at least one terminal is equal to the signal of the at least one terminal output signal, that is, different terminal output signals are transmitted through different terminals; in addition, the at least one terminal output signal does not pass through the phy layer circuit 110 in this embodiment, in other words, the solid state disk control apparatus 100 receives the at least one terminal output signal and the SerDes receiving signal through different pins respectively.
Referring to fig. 1, the processing circuit 130 is, for example, a microprocessor (or an equivalent circuit thereof) for adapting the operation mode of the solid state disk control apparatus 100 to one of the plurality of interface types according to at least one of the physical layer output signal and the at least one terminal output signal (i.e. according to the physical layer output signal and/or the at least one terminal output signal). Details of the operation of the processing circuit 130 are described below.
Referring to fig. 1, a mac circuit 140, coupled to the phy circuit 110 and the processing circuit 130, is required for the solid state drive control apparatus 100, but is not directly related to the implementation of the present invention.
As mentioned above, in one embodiment, the processing circuit 130 may determine the operation mode of the solid state disk control apparatus 100 according to the physical layer output signal. For example, if a host assigns a port connected to the solid state disk control device 100 as a port of the SATA or PCI-Express interface, the solid state disk control device 100 can determine the mode of operation by detecting the characteristics of the signal from the host to distinguish the state of the port because the characteristics of the transmission signal of the SATA interface in the connection setup phase are different from the characteristics of the transmission signal of the PCI-Express interface in the connection setup phase. Specifically, if the host transmits a SerDes signal conforming to the PCI-Express specification during the connection setup phase, the SerDes signal is an In-Band (In-Band) signal with a frequency conforming to the specification, such as a Training Sequence (Training Sequence) with a frequency of 2.5GHz, as shown In fig. 2. Therefore, the phy layer circuit 110 will generate the phy layer output signal according to the in-band signal, so that the processing circuit 130 can determine that the phy layer output signal meets the PCI-Express specification by at least one of the means of comparing the signal frequency, detecting the level variation, detecting the level average value, and the like; if the host transmits a SerDes signal conforming to the SATA specification during the connection establishment phase, the SerDes signal is an Out-of-Band (OOB) signal having a frequency lower than the specification definition, such as a COMRESET, COMINIT or COMWAKE signal having a low frequency, as shown in FIG. 3. Therefore, the phy layer circuit 110 includes a low frequency signal detection circuit (LFD)410, as shown in fig. 4, for generating the phy layer output signal according to the out-of-band signal, so that the processing circuit 130 can determine that the phy layer output signal conforms to the SATA specification. Note that the frequency of the in-band signal is generally higher than 1GHz (e.g., several GHz), and the frequency of the out-of-band signal is generally lower than 1GHz (e.g., several hundreds of KHz to several MHz). It should be noted that the solid state disk control apparatus 100 also sends a signal to the host, but this operation is not related to the technical features of the present embodiment, and therefore the details are omitted here.
In another embodiment, the processing circuit 130 may determine the operation mode of the solid state disk control apparatus 100 according to the at least one terminal output signal. For example, if a host designates a port connected to the solid state disk control device 100 as a port of an SATA or PCI-Express interface, since the SATA interface does not need to transmit the at least one terminal output signal and the PCI-Express interface needs to transmit the signal, the SATA interface does not have a change in the at least one terminal output signal and the PCI-Express interface has a specific change in the at least one terminal output signal, so that the solid state disk control device 100 can receive and detect the signal from the host through the at least one terminal to distinguish the state of the port, and further determine the mode of operation. In detail, when the at least one terminal output signal conforms to the PCI-Express specification, the at least one terminal output signal is for example at least one frequency Band edge (Side Band) signal, which includes at least one of a reset signal (PERST #), a WAKE-up signal (WAKE #), a clock request signal (CLKRREQ #) and a reference clock signal (REFCLK), wherein the symbol "#" represents a low enable (i.e. a low level of a signal corresponds to an enable state), and after the solid state disk control apparatus 100 is connected to a host, the waveforms of the reset signal, the wake-up signal, the clock request signal and the reference clock signal are shown in fig. 5, and accordingly, the processing circuit 130 can determine that the port is assigned as the port of the PCI-Express interface according to the at least one terminal output signal by at least one of signal frequency comparison, level variation detection, level average value detection and the like; if the port is assigned as the SATA port, the waveform of the at least one terminal output signal does not change, and the processing circuit 130 can determine that the at least one terminal output signal does not conform to the PCI-Express specification, thereby determining that the solid state disk control apparatus 100 should operate in the SATA mode.
Referring to fig. 5, in one embodiment, the processing circuit 130 detects whether the level of the reset signal is pulled high (pulled high), and then detects whether the level of the reset signal is pulled low and asserted (asserted), so as to determine that the at least one terminal output signal meets the PCI-Express specification if the detection result is yes, or determine that the at least one terminal output signal does not meet the PCI-Express specification if the detection result is no. In another embodiment, the processing circuit 130 detects whether the level of the clock request signal is pulled up and then detects whether the level of the clock request signal is pulled down and asserted by the solid state disk control device, so as to determine that the at least one terminal output signal meets the PCI-Express specification if the detection result is yes or determine that the at least one terminal output signal does not meet the PCI-Express specification if the detection result is no. In another embodiment, the processing circuit 130 detects a level change of the clock request signal and detects the presence or absence of the reference clock signal, so as to determine that the at least one terminal output signal conforms to the PCI-Express specification when the level change and the presence of the clock are detected, in this embodiment, the solid state disk control device 100 includes a clock generating circuit (not shown) for generating an operation clock according to the reference clock signal (e.g., a 100MHz clock signal) from a host for the solid state disk control device 100 to operate in the PCI-Express mode, and it is noted that the SATA specification employs an embedded clock signal without the above-mentioned independent reference clock signal. In another embodiment, the processing circuit 130 detects whether the level of at least one of the reset signal, the wake-up signal and the clock request signal is pulled high, so as to determine that the at least one terminal output signal meets the PCI-Express specification if the detection result is yes, or determine that the at least one terminal output signal does not meet the PCI-Express specification if the detection result is no.
In addition to the solid state disk control device 100, the present disclosure further includes a solid state disk control method executed by the solid state disk control device 100 of the present disclosure or an equivalent device thereof. One embodiment of the control method is shown in fig. 6, which enables a solid state disk control device to be compatible with a plurality of interface types, and comprises the following steps:
step S610: generating a physical layer output signal according to the received signal. This step may be performed by the multi-interface compatible physical layer circuit 110 of fig. 1 or its equivalent.
Step S620: generating at least one terminal output signal according to the signal change of at least one terminal. This step may be performed by the input-output circuit 120 of fig. 1 or its equivalent.
Step S630: and enabling the operation mode of the solid state disk control device to be suitable for one of the plurality of interface types according to at least one of the physical layer output signal and the at least one terminal output signal.
Since those skilled in the art can deduce details and variations of the embodiments of the method based on the disclosure of the apparatus disclosed in the present application, and more particularly, technical features of the embodiments of the apparatus can be reasonably applied to the embodiments of the method, repeated and redundant descriptions are omitted herein without affecting the disclosure and the feasibility of the embodiments of the method. It should be noted that although the embodiments of the present disclosure mostly use the SATA interface and the PCI-Express interface as examples, those skilled in the art can derive the solid state disk control apparatus and method supporting more interfaces or other interfaces according to the disclosure and specifications of other interfaces, and all such modifications are within the scope of the present disclosure.
In summary, the apparatus and method of the present invention can perform interface detection from the apparatus side, which can avoid the problems of the prior art, and have the characteristics of low implementation cost and high applicability.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
[ notation ] to show
100 solid state disk control device (SSD Controller)
110 multi-interface compatible physical layer circuit (MIC-PHY)
120 input/output circuit (I/O)
130 Processing Circuit (Processing Circuit)
140 media access control circuit (MAC)
Host
SSD Controller solid state disk control device
Training Sequence
COMRESET, COMWAKE SATA signal
410 Low frequency signal detecting circuit (LFD)
PERST # RESET signal
WAKE # WAKE SIGNAL
CLKRREQ # clock request signal
REFCLK reference clock signal
S610 to S630
Claims (12)
1. A solid state disk control device compatible with multiple interface types comprises:
the multi-interface compatible physical layer circuit is used for receiving a serial/deserializing receiving signal from a host and generating a physical layer output signal according to the serial/deserializing receiving signal;
the input/output circuit is used for generating at least one terminal output signal according to the signal change of at least one terminal; and
a processing circuit for making the operation mode of the solid state disk control device suitable for one of the plurality of interface types according to the physical layer output signal and the at least one terminal output signal,
wherein the at least one terminal output signal complies with a peripheral component interconnect express specification;
wherein the at least one terminal output signal comprises at least one of: a reset signal (PERST #), a WAKE-up signal (WAKE #), and a clock request signal (CLKRREQ #);
wherein the processing circuit detects whether the level of the reset signal is pulled up and then detects whether the level of the reset signal is pulled down by the host terminal to be established, so as to judge whether the output signal of the at least one terminal meets the interconnection specification of the fast peripheral component according to the detection result; or
The processing circuit detects whether the level of the clock pulse request signal is pulled up or not and then detects whether the level of the clock pulse request signal is pulled down or not by the solid state disk control device to be established, so that whether the output signal of the at least one terminal meets the interconnection specification of the peripheral component express (PCI) is judged according to the detection result.
2. The solid state disk control device of claim 1, wherein the plurality of interface types includes peripheral component interconnect Express (PCI-Express) and Serial Advanced Technology Attachment (SATA).
3. The solid state disk control device of claim 1, wherein the deserialized receive signal comprises one of an in-band signal and an out-of-band signal.
4. The solid state drive control apparatus of claim 3, wherein the in-band signal complies with a peripheral component interconnect express specification and the out-of-band signal complies with a serial advanced technology attachment specification.
5. The solid state drive control device in claim 4, wherein the frequency of the in-band signal is higher than 1GHz, and the frequency of the out-of-band signal is lower than 1 GHz.
6. A solid state disk control device compatible with multiple interface types comprises:
the multi-interface compatible physical layer circuit is used for receiving a serial/deserializing receiving signal from a host and generating a physical layer output signal according to the serial/deserializing receiving signal;
the input/output circuit is used for generating at least one terminal output signal according to the signal change of at least one terminal; and
the processing circuit is used for outputting a signal according to the at least one terminal so that the operation mode of the solid state disk control device is suitable for one of the plurality of interface types;
wherein the at least one terminal output signal complies with a peripheral component interconnect express specification;
wherein the at least one terminal output signal comprises at least one of: a reset signal (PERST #), a WAKE-up signal (WAKE #), and a clock request signal (CLKRREQ #);
wherein the processing circuit detects whether the level of the reset signal is pulled up and then detects whether the level of the reset signal is pulled down by the host terminal to be established, so as to judge whether the output signal of the at least one terminal meets the interconnection specification of the fast peripheral component according to the detection result; or
Wherein, whether the level of the clock pulse request signal is pulled up or not is detected, and then whether the level of the clock pulse request signal is pulled down or not is detected and is determined, thereby judging whether the output signal of the at least one terminal meets the interconnection specification of the fast peripheral component or not according to the detection result.
7. The solid state disk control apparatus of claim 6, wherein the plurality of interface types comprises peripheral component interconnect Express (PCI-Express) and Serial Advanced Technology Attachment (SATA).
8. The solid state disk control device of claim 6, wherein the deserialized receive signal comprises one of an in-band signal and an out-of-band signal.
9. The solid state drive control apparatus of claim 8, wherein the in-band signal complies with a peripheral component interconnect express specification and the out-of-band signal complies with a serial advanced technology attachment specification.
10. The solid state drive control device in claim 9, wherein the frequency of the in-band signal is higher than 1GHz and the frequency of the out-of-band signal is lower than 1 GHz.
11. A solid state disk control method is executed by a solid state disk control device, the control method makes the solid state disk control device compatible with a plurality of interface types, comprising the following steps:
receiving a serial/deserializing receiving signal from a host, and generating a physical layer output signal according to the serial/deserializing receiving signal;
generating at least one terminal output signal according to the signal change of at least one terminal; and
the operation mode of the solid state disk control device is suitable for one of the plurality of interface types according to the physical layer output signal and the at least one terminal output signal,
wherein the at least one terminal output signal complies with a peripheral component interconnect express specification;
wherein the at least one terminal output signal comprises at least one of: a reset signal (PERST #), a WAKE-up signal (WAKE #), and a clock request signal (CLKRREQ #);
wherein whether the level of the reset signal is pulled up or not is detected, and whether the level of the reset signal is pulled down or not is detected, so that the determination is made whether the output signal of the at least one terminal meets the interconnection specification of the peripheral component express (PCI) according to the detection result; or
Wherein, whether the level of the clock pulse request signal is pulled up or not is detected, and then whether the level of the clock pulse request signal is pulled down or not is detected and is determined, thereby judging whether the output signal of the at least one terminal meets the interconnection specification of the fast peripheral component or not according to the detection result.
12. A solid state disk control method is executed by a solid state disk control device, the control method makes the solid state disk control device compatible with a plurality of interface types, comprising the following steps:
receiving a serial/deserializing receiving signal from a host, and generating a physical layer output signal according to the serial/deserializing receiving signal;
generating at least one terminal output signal according to the signal change of at least one terminal; and
outputting a signal according to the at least one terminal so that the operation mode of the solid state disk control device is suitable for one of the plurality of interface types;
wherein the at least one terminal output signal complies with a peripheral component interconnect express specification;
wherein the at least one terminal output signal comprises at least one of: a reset signal (PERST #), a WAKE-up signal (WAKE #), and a clock request signal (CLKRREQ #);
wherein whether the level of the reset signal is pulled up or not is detected, and whether the level of the reset signal is pulled down or not is detected, so that the determination is made whether the output signal of the at least one terminal meets the interconnection specification of the peripheral component express (PCI) according to the detection result; or
Wherein, whether the level of the clock pulse request signal is pulled up or not is detected, and then whether the level of the clock pulse request signal is pulled down or not is detected and is determined, thereby judging whether the output signal of the at least one terminal meets the interconnection specification of the fast peripheral component or not according to the detection result.
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| CN107463521A (en) | 2017-12-12 |
| CN111930655A (en) | 2020-11-13 |
| CN111930655B (en) | 2022-01-21 |
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Effective date of registration: 20190429 Address after: No. 11 Standardized Workshop of Hefei Intelligent Industrial Park at the Junction of Wenzhong Road and Qianjiang Road, Xinzhan District, Hefei City, Anhui Province Applicant after: Hefei Peirui Microelectronics Co., Ltd. Address before: Hsinchu City, Taiwan, China Applicant before: Ruiyu Semiconductor Co., Ltd. |
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