CN107454008B - Gigabit-ten-gigabit Ethernet intercommunication system and method - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/70—Admission control; Resource allocation
- H04L47/78—Architectures of resource allocation
- H04L47/783—Distributed allocation of resources, e.g. bandwidth brokers
- H04L47/785—Distributed allocation of resources, e.g. bandwidth brokers among multiple network domains, e.g. multilateral agreements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
- H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
- H04L47/2441—Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
Abstract
The invention discloses a gigabit Ethernet intercommunication system and a gigabit Ethernet intercommunication method, which comprise a gigabit Ethernet transceiving interface module, a gigabit Ethernet transceiving interface module and a logic module, wherein the logic module is configured between the gigabit Ethernet transceiving interface module and the gigabit Ethernet transceiving interface module, the logic module is used for logically converging gigabit Ethernet flow from the gigabit Ethernet transceiving interface module to the gigabit Ethernet transceiving interface module and outputting the gigabit Ethernet flow, and the logic module can also be used for evenly dividing the gigabit flow from the gigabit Ethernet transceiving interface module to the gigabit Ethernet transceiving interface module and outputting the gigabit Ethernet flow. Compared with the prior art, the gigabit Ethernet intercommunication system and the gigabit Ethernet intercommunication method solve the problems that under the gigabit Ethernet flow environment, the gigabit Ethernet intercommunication system cannot be adapted to the gigabit interface on the selected network hardware equipment, and the flow cannot be accessed to the network equipment.
Description
Technical Field
The invention relates to the technical field of digital communication, in particular to a gigabit Ethernet intercommunication system and a gigabit Ethernet intercommunication method.
Background
With the maturity of optical transmission technology, various network traffic control and analysis devices are in a wide range, and the interface types supported by network devices during research, development and production are fixed, but the problem that the device interfaces are not adapted to the network traffic during field application is encountered.
Disclosure of Invention
The technical task of the invention is to provide a kilomega and kilomega Ethernet intercommunication system and a kilomega and kilomega Ethernet intercommunication method aiming at the defects.
A gigabit-ten-gigabit Ethernet intercommunication system comprises a gigabit-Ethernet transceiving interface module, a gigabit-Ethernet transceiving interface module and a logic module, wherein the logic module is configured between the gigabit-Ethernet transceiving interface module and the gigabit-Ethernet transceiving interface module, the logic module is used for logically converging gigabit Ethernet flow from the gigabit-Ethernet transceiving interface module to the gigabit-Ethernet transceiving interface module and outputting the gigabit-Ethernet flow, and the logic module can also be used for evenly dividing the gigabit flow from the gigabit-Ethernet transceiving interface module into the gigabit-Ethernet transceiving interface module and outputting the gigabit-Ethernet flow.
The logic module carries out behavioral level description through Verilog language, compiles to form a netlist file, comprehensively maps and downloads the netlist file into an FPGA chip, and realizes logic control through the form of the FPGA chip.
The logic module comprises a logic part of gigabit-over-tera, the logic part of gigabit-over-tera comprises a receiving module, a merging module and an XGMII module, wherein the receiving module is responsible for receiving and analyzing the flow transmitted by the gigabit Ethernet transceiving interface module to obtain an effective message; the merging module is used for merging all the received flow data into one path and outputting the path to the XGMII module; the XGMII module is used for packaging and converting the received combined data and is in butt joint output with the tera Ethernet transceiving interface module.
The merging module comprises two groups, wherein one group is used for merging all the received gigabit Ethernet transceiving interface modules into two paths of data, and correspondingly, the merging module comprises two groups; and the other group combines the two paths of data into one path of data and outputs the one path of data to the XGMII module.
The logic module comprises a logic part of ten-gigabit, and the logic part of ten-gigabit comprises an Ethernet message analysis logic module, a load balancing logic module and a homologous homoclinic logic module, wherein the Ethernet message analysis logic module is used for analyzing flow data from the ten-gigabit Ethernet transceiving interface module; the load balancing logic module is used for uniformly distributing the analyzed message information to the gigabit Ethernet transceiving interface module; and the homologous homoclinic logic module is used for sending the data traffic of the same source equally divided by the load balancing logic module to the same receiving device.
A gigabit-ten-gigabit Ethernet intercommunication method is based on the system and is realized by the following steps:
firstly, downloading a logic module into an FPGA chip;
then, the gigabit Ethernet transceiving interface module and the gigabit Ethernet transceiving interface module are respectively connected with a logic module of the FPGA chip, and the gigabit Ethernet transceiving interface module are both connected with corresponding receiving equipment;
when the gigabit Ethernet transceiving interface module sends gigabit Ethernet flow, the logic module finishes receiving, then all the gigabit Ethernet flow is converged to the gigabit Ethernet transceiving interface module and then output to receiving equipment connected with the gigabit Ethernet transceiving interface module;
when the tera Ethernet transceiving interface module sends tera flow, the logic module completes receiving, then the tera flow is evenly distributed into the gigabit Ethernet transceiving interface module and then output to receiving equipment connected with the gigabit Ethernet transceiving interface module.
The process that the gigabit Ethernet transceiving interface module sends the traffic to the gigabit Ethernet transceiving interface module is as follows:
firstly, all or a plurality of kilomega Ethernet transceiving interface modules are simultaneously accessed to flow and output to a logic module by adopting a strategy of original output, a receiving module in the logic module receives and analyzes an effective message from the flow transmitted by the kilomega Ethernet transceiving interface modules, the integrity of the message is detected according to the message with CRC fields, and simultaneously, the message is packaged into data [68:0] of 69bits per period;
the merging module is used for merging all the received flow data into one path and outputting the path to the XGMII module;
the XGMII module is used for packaging and converting the received combined data and is in butt joint output with the tera Ethernet transceiving interface module.
The gigabit Ethernet transceiving interface module is provided with 12 gigabit Ethernet transceiving interface modules, the gigabit Ethernet transceiving interface module is provided with 1 gigabit Ethernet transceiving interface module, correspondingly, the merging module comprises two groups, one group comprises two modules which can merge six received flow data from the gigabit Ethernet transceiving interface module into one flow data, and the other group is a module which merges two paths of data into one path of data.
The specific process of sending the flow data to the gigabit Ethernet transceiving interface module by the gigabit Ethernet transceiving interface module is as follows:
firstly, an Ethernet message analysis logic module analyzes flow data from a gigabit Ethernet transceiving interface module, performs hash calculation according to an IP address of a received Ethernet message to obtain a corresponding hash value, then searches a corresponding strategy output interface table to obtain an output interface number, and then forwards the output interface number to a corresponding output interface; in the process, the analyzed message information is uniformly distributed into the gigabit Ethernet transceiving interface module through the load balancing logic module, and the homologous homoclinic logic module is used for sending the data traffic of the same source equally distributed by the load balancing logic module to the same receiving device.
The specific process of analyzing the data flow by the Ethernet message analysis logic module is as follows:
when the Ethernet message analysis logic module analyzes the message, the message is analyzed into 72bits data [71:0 ];
then, separating data bits from effective bits of data [71:0] of the data, repackaging the data into 134bits single-cycle processing data, and discarding the ultra-long packet with the data length exceeding 1518 bytes and the ultra-short packet with the data length smaller than 64 bytes;
and then analyzing the encapsulated data, identifying the Ethernet message, and discarding the identified non-Ethernet message, wherein the identified Ethernet message is the Ethernet message required to be subjected to Hash calculation.
Compared with the prior art, the gigabit Ethernet intercommunication system and the method thereof have the following beneficial effects:
the invention relates to a kilomega and kilomega Ethernet intercommunication system and a method, which mainly solve the problems that under the kilomega or kilomega Ethernet flow environment, the system can not be adapted to a kilomega and kilomega interface on selected network hardware equipment, and the flow can not be accessed to the network equipment; support kilomega port output automatic load balancing, ensure output flow not to overload and lose packets; the method supports the same source and the same destination, reasonably distributes the output interface according to the IP address of the message, ensures the integrity of the session, and has strong practicability, wide application range and easy popularization.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of the gigabit-to-gigabit ethernet interworking implementation of the present invention.
Fig. 2 is a schematic diagram of the gigabit ethernet interworking implementation of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific embodiments in order to make the technical field better understand the scheme of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 and fig. 2, the present invention provides a gigabit ethernet interworking system, which includes a gigabit ethernet transceiving interface module, and a logic module, wherein the logic module is configured between the gigabit ethernet transceiving interface module and the gigabit ethernet transceiving interface module, the logic module is configured to logically converge gigabit ethernet traffic from the gigabit ethernet transceiving interface module to the gigabit ethernet transceiving interface module and output the gigabit ethernet traffic, and the logic module is further configured to equally divide the gigabit traffic from the gigabit ethernet transceiving interface module into the gigabit ethernet transceiving interface module and output the gigabit ethernet traffic.
The logic module carries out behavioral level description through Verilog language, compiles to form a netlist file, comprehensively maps and downloads the netlist file into an FPGA chip, and realizes logic control through the form of the FPGA chip.
The logic module comprises a logic part of gigabit-over-tera, the logic part of gigabit-over-tera comprises a receiving module, a merging module and an XGMII module, wherein the receiving module is responsible for receiving and analyzing the flow transmitted by the gigabit Ethernet transceiving interface module to obtain an effective message; the merging module is used for merging all the received flow data into one path and outputting the path to the XGMII module; the XGMII module is used for packaging and converting the received combined data and is in butt joint output with the tera Ethernet transceiving interface module.
The merging module comprises two groups, wherein one group is used for merging all the received gigabit Ethernet transceiving interface modules into two paths of data, and correspondingly, the merging module comprises two groups; and the other group combines the two paths of data into one path of data and outputs the one path of data to the XGMII module.
The logic module comprises a logic part of ten-gigabit, and the logic part of ten-gigabit comprises an Ethernet message analysis logic module, a load balancing logic module and a homologous homoclinic logic module, wherein the Ethernet message analysis logic module is used for analyzing flow data from the ten-gigabit Ethernet transceiving interface module; the load balancing logic module is used for uniformly distributing the analyzed message information to the gigabit Ethernet transceiving interface module; and the homologous homoclinic logic module is used for sending the data traffic of the same source equally divided by the load balancing logic module to the same receiving device.
The gigabit Ethernet interface is suitable for the IEEE 802.3-2005 standard, and the 10G Ethernet interface is suitable for the IEEE 802.3ae standard.
The gigabit port output supports load balancing and supports homologous and homoclinic to ensure the integrity of the session.
The FPGA chip may be implemented in EP2AGX125EF29I3 model Altera.
The load balancing logic module is mainly used for ensuring that the flow is more uniformly distributed to each output interface under the condition that the gigabit interface does not carry load and lose packet (here, firstly, the analysis server connected with each output interface can play the best performance, so that the full load work and the light load work are avoided, and secondly, the conversation flow is ensured not to be lost and the information is not lost). The homological and homological module mainly refers to ensuring that the traffic of the same session can be distributed to the same output interface, so that the back-end server receives the complete session (the external meaning is that if the traffic of the same session is output to two servers from two different interfaces, any one server cannot obtain the complete session, and thus cannot analyze the 'original meaning' of the session).
A gigabit-ten-gigabit Ethernet intercommunication method is based on the system and is realized by the following steps:
firstly, downloading a logic module into an FPGA chip;
then, the gigabit Ethernet transceiving interface module and the gigabit Ethernet transceiving interface module are respectively connected with a logic module of the FPGA chip, and the gigabit Ethernet transceiving interface module are both connected with corresponding receiving equipment;
when the gigabit Ethernet transceiving interface module sends gigabit Ethernet flow, the logic module finishes receiving, then all the gigabit Ethernet flow is converged to the gigabit Ethernet transceiving interface module and then output to receiving equipment connected with the gigabit Ethernet transceiving interface module;
when the tera Ethernet transceiving interface module sends tera flow, the logic module completes receiving, then the tera flow is evenly distributed into the gigabit Ethernet transceiving interface module and then output to receiving equipment connected with the gigabit Ethernet transceiving interface module.
The process that the gigabit Ethernet transceiving interface module sends the traffic to the gigabit Ethernet transceiving interface module is as follows:
firstly, all or a plurality of kilomega Ethernet transceiving interface modules are simultaneously accessed to flow and output to a logic module by adopting a strategy of original output, a receiving module in the logic module receives and analyzes an effective message from the flow transmitted by the kilomega Ethernet transceiving interface modules, the integrity of the message is detected according to the message with CRC fields, and simultaneously, the message is packaged into data [68:0] of 69bits per period;
the merging module is used for merging all the received flow data into one path and outputting the path to the XGMII module;
the XGMII module is used for packaging and converting the received combined data and is in butt joint output with the tera Ethernet transceiving interface module.
The gigabit Ethernet transceiving interface module is provided with 12 gigabit Ethernet transceiving interface modules, the gigabit Ethernet transceiving interface module is provided with 1 gigabit Ethernet transceiving interface module, correspondingly, the merging module comprises two groups, one group comprises two modules which can merge six received flow data from the gigabit Ethernet transceiving interface module into one flow data, and the other group is a module which merges two paths of data into one path of data.
The specific process of sending the flow data to the gigabit Ethernet transceiving interface module by the gigabit Ethernet transceiving interface module is as follows:
firstly, an Ethernet message analysis logic module analyzes flow data from a gigabit Ethernet transceiving interface module, performs hash calculation according to an IP address of a received Ethernet message to obtain a corresponding hash value, then searches a corresponding strategy output interface table to obtain an output interface number, and then forwards the output interface number to a corresponding output interface; in the process, the analyzed message information is uniformly distributed into the gigabit Ethernet transceiving interface module through the load balancing logic module, and the homologous homoclinic logic module is used for sending the data traffic of the same source equally distributed by the load balancing logic module to the same receiving device.
The specific process of analyzing the data flow by the Ethernet message analysis logic module is as follows:
when the Ethernet message analysis logic module analyzes the message, the message is analyzed into 72bits data [71:0 ];
then, separating data bits from effective bits of data [71:0] of the data, repackaging the data into 134bits single-cycle processing data, and discarding the ultra-long packet with the data length exceeding 1518 bytes and the ultra-short packet with the data length smaller than 64 bytes;
and then analyzing the encapsulated data, identifying the Ethernet message, and discarding the identified non-Ethernet message, wherein the identified Ethernet message is the Ethernet message required to be subjected to Hash calculation.
A specific example is given below to describe the method of the present invention in detail, where SFP is used as the gigabit ethernet transceiver interface module and XAUI is used as the gigabit ethernet transceiver interface module.
When the SFP is used for access, all or a plurality of 12 gigabit Ethernet interfaces can be simultaneously accessed to flow, all flow processing logics adopt a strategy of original output, when the SFP is used for output, the flow is accessed by an SFP + module, and the load of the gigabit interfaces is considered to be very easy to reach, so that the processing logics firstly carry out hash calculation according to the IP address of the received Ethernet message to obtain a corresponding hash value, then look up a corresponding strategy output interface table to obtain an output interface number, and then forward the output interface number to the corresponding output interface, thereby ensuring that the output interface can not lose the packet due to flow overload, ensuring that the message of the same session can be output from the same output interface, and ensuring the integrity of the session. The design is realized by adopting Verilog language to describe and comprehensively mapping to FPGA after meeting the design requirements. The overall design data flow is as shown in fig. 1 and fig. 2, and the implementation is as follows:
giga to ten thousand million:
1) the SFP Ethernet interface adopts a GMII _ MAC _1000 module provided by QuartusII to support the IEEE 802.3-2005 standard, a receiving module firstly resolves the received differential signal into a digital processable effective message, detects the message integrity according to the CRC field of the message, and simultaneously encapsulates the message into data of 69bits per period [68:0 ].
2) Adopting 2 merging modules to merge the 12 paths of data streams in the step 1) into 2 paths.
3) And 2 paths of data flows output by the 2) are further subjected to two-in-one to obtain a final path of output.
4) And sending the data stream output in the step 3) to an xgmii module for packaging conversion.
5) Interfacing the data stream output in 4) with the XAUI module provided by quaarthsi.
Ten thousand megabits per giga:
the SFP + interface is used as input, the flow enters the internal logic of the FPGA through the XAUI module, and the message is analyzed into 72bits data [71:0 ].
Data [71:0] data is subjected to data bit and valid bit separation and repackaged into 134bits single cycle processing data. For very long packets with data length exceeding 1518 bytes and very short packets with data length less than 64 bytes, processing logic selects the discard process.
And analyzing the output data, and acquiring multi-element information by using the Ethernet message. And discarding the identified non-Ethernet message.
And inputting the multi-element information into a hash module for calculation to obtain a hash value.
And taking the output hash value as the address of the lookup output interface table, and looking up the output interface value.
And outputting the message to a corresponding interface according to the query result.
The output interface tables in the trillion gigabit logical process have been written sequentially in output port order (0123456789AB012345 … cycles until the tables are filled). According to the design, CRC16 is used for hash operation, and an input source IP is used as hash input after being expanded to 128 bits. The hash value of the message source IP is used as the address of the lookup output interface table to ensure that messages of the same session are output from the same interface, and the flow of different sessions can be output through different interfaces to ensure that a certain gigabit interface can not lose packet due to overload.
The present invention can be easily implemented by those skilled in the art from the above detailed description. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the basis of the disclosed embodiments, a person skilled in the art can combine different technical features at will, thereby implementing different technical solutions.
In addition to the technical features described in the specification, the technology is known to those skilled in the art.
Claims (4)
1. A gigabit Ethernet intercommunication system is characterized by comprising a gigabit Ethernet transceiving interface module, a gigabit Ethernet transceiving interface module and a logic module, wherein the logic module is configured between the gigabit Ethernet transceiving interface module and the gigabit Ethernet transceiving interface module, the logic module is used for logically converging gigabit Ethernet flow from the gigabit Ethernet transceiving interface module to the gigabit Ethernet transceiving interface module and outputting the gigabit Ethernet flow, and the logic module can also be used for evenly dividing the gigabit flow from the gigabit Ethernet transceiving interface module to the gigabit Ethernet transceiving interface module and outputting the gigabit Ethernet flow;
the logic module comprises a logic part of gigabit-over-tera, the logic part of gigabit-over-tera comprises a receiving module, a merging module and an XGMII module, wherein the receiving module is responsible for receiving and analyzing the flow transmitted by the gigabit Ethernet transceiving interface module to obtain an effective message; the merging module is used for merging all the received flow data into one path and outputting the path to the XGMII module; the XGMII module is used for carrying out packaging conversion on the received combined data and is in butt joint output with the tera Ethernet transceiving interface module;
the merging module comprises two groups, wherein one group is used for merging all the received data from the gigabit Ethernet transceiving interface module into two paths of data, and correspondingly, the merging module which is combined into two paths of data comprises two merging modules; the other group combines the two paths of data into one path of data and outputs the data to the XGMII module;
the logic module comprises a logic part of ten-gigabit, and the logic part of ten-gigabit comprises an Ethernet message analysis logic module, a load balancing logic module and a homologous homoclinic logic module, wherein the Ethernet message analysis logic module is used for analyzing flow data from the ten-gigabit Ethernet transceiving interface module; the load balancing logic module is used for uniformly distributing the analyzed message information to the gigabit Ethernet transceiving interface module; and the homologous homoclinic logic module is used for sending the data traffic of the same source equally divided by the load balancing logic module to the same receiving device.
2. The gigabit ethernet intercommunication system according to claim 1, wherein said logic module performs behavioral level description via Verilog language, compiles to form a netlist file, synthetically maps and downloads it to an FPGA chip, and implements logic control via the form of the FPGA chip.
3. A gigabit ethernet interworking method, characterized in that based on the gigabit ethernet interworking system of claim 1 or 2, the implementation process is:
firstly, downloading a logic module into an FPGA chip;
then, the gigabit Ethernet transceiving interface module and the gigabit Ethernet transceiving interface module are respectively connected with a logic module of the FPGA chip, and the gigabit Ethernet transceiving interface module are both connected with corresponding receiving equipment;
when the gigabit Ethernet transceiving interface module sends gigabit Ethernet flow, the logic module finishes receiving, then all the gigabit Ethernet flow is converged to the gigabit Ethernet transceiving interface module and then output to receiving equipment connected with the gigabit Ethernet transceiving interface module;
when the tera Ethernet transceiving interface module sends tera flow, the logic module finishes receiving, then the tera flow is evenly distributed into the gigabit Ethernet transceiving interface module and then output to receiving equipment connected with the gigabit Ethernet transceiving interface module;
the process that the gigabit Ethernet transceiving interface module sends the traffic to the gigabit Ethernet transceiving interface module is as follows:
firstly, all or a plurality of kilomega Ethernet transceiving interface modules are simultaneously accessed to flow and output to a logic module by adopting a strategy of original output, a receiving module in the logic module receives and analyzes an effective message from the flow transmitted by the kilomega Ethernet transceiving interface modules, the integrity of the message is detected according to the message with CRC fields, and meanwhile, the message is encapsulated into data of 69bits per period;
the merging module is used for merging all the received flow data into one path and outputting the path to the XGMII module;
the XGMII module is used for carrying out packaging conversion on the received combined data and is in butt joint output with the tera Ethernet transceiving interface module;
the specific process of sending the flow data to the gigabit Ethernet transceiving interface module by the gigabit Ethernet transceiving interface module is as follows:
firstly, an Ethernet message analysis logic module analyzes flow data from a gigabit Ethernet transceiving interface module, performs hash calculation according to an IP address of a received Ethernet message to obtain a corresponding hash value, then searches a corresponding strategy output interface table to obtain an output interface number, and then forwards the output interface number to a corresponding output interface; in the process, the analyzed message information is uniformly distributed into the gigabit Ethernet transceiving interface module through the load balancing logic module, and the homologous homoclinic logic module is used for sending the data traffic of the same source equally distributed by the load balancing logic module to the same receiving device;
the specific process of analyzing the data flow by the Ethernet message analysis logic module is as follows:
when the Ethernet message analysis logic module analyzes the message, the message is analyzed into 72bits data;
then, separating data bits from effective bits of 72bits data, repackaging the data into 134bits single-cycle processing data, and discarding the ultra-long packets with the data length exceeding 1518 bytes and the ultra-short packets with the data length smaller than 64 bytes;
and then analyzing the encapsulated data, identifying the Ethernet message, and discarding the identified non-Ethernet message, wherein the identified Ethernet message is the Ethernet message required to be subjected to Hash calculation.
4. The gigabit ethernet interworking method according to claim 3, wherein 12 gigabit ethernet transceiving interface modules are configured, and 1 gigabit ethernet transceiving interface module is configured, and correspondingly, the combining module includes two groups, one group includes two modules that can combine six received traffic data from the gigabit ethernet transceiving interface module into one traffic data, and the other group is a module that combines two data into one data.
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| CN108073546A (en) * | 2017-12-27 | 2018-05-25 | 西安奇维科技有限公司 | One kind realizes network data reception and reading and control method thereof based on FPGA |
| CN108540350A (en) * | 2018-04-20 | 2018-09-14 | 济南浪潮高新科技投资发展有限公司 | A kind of network flow preprocess method based on FPGA |
| CN109286686B (en) * | 2018-11-23 | 2021-05-14 | 盛科网络（苏州）有限公司 | Load balancing method based on polling mechanism |
| CN109194591A (en) * | 2018-12-03 | 2019-01-11 | 济南浪潮高新科技投资发展有限公司 | A kind of 100G and 10G ether intercommunicating system and method |
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