CN108073546A - One kind realizes network data reception and reading and control method thereof based on FPGA - Google Patents
One kind realizes network data reception and reading and control method thereof based on FPGA Download PDFInfo
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- CN108073546A CN108073546A CN201711447076.9A CN201711447076A CN108073546A CN 108073546 A CN108073546 A CN 108073546A CN 201711447076 A CN201711447076 A CN 201711447076A CN 108073546 A CN108073546 A CN 108073546A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The present invention relates to network data reception technique fields, and in particular to one kind realizes network reception control method based on FPGA.One kind realizes network data reception control method based on FPGA, includes the following steps：Step 1：Determine whether network frame head；Step 2：It writes data into BRAM_IP buffering areas, while the data received is counted by data reception module；Step 3：BRAM_IP buffering area initial addresses are jumped into next byte；Step 4：Carry out CRC check；Step 5：Receiving network data length is written to FIFO_IP buffering areas, the receive process of one packet network data of instruction are completed.When reading information, first judged according to the data length of deposit FIFO_IP buffering areas, rather than directly read data message in BRAM_IP buffering areas, and the data message in BRAM_IP buffering areas does not have sufficient space to be operated when storing next bag maximum network data without network data reception, avoids network data packet loss problem.
Description
Technical field
The present invention relates to network data reception technique fields, and in particular to one kind realizes that network receives controlling party based on FPGA
Method.
Background technology
Current more and more applications are realized by FPGA to communicate with network, can complete higher transmission speed, but
It is that FPGA can usually run into loss network packet situation in reception network data, network is caused to carry out TCP or UDP message
During transmission, there is unstable situation or when transmitting TCP data, transmission speed is unsatisfactory for actual requirement, in actual test mistake
Find there is a situation where length bag due to network in journey, FPGA there is a situation where to lose data packet, cause in receiving network data bag
Network stabilization transmission speed reduces.
The content of the invention
It is contemplated that it in view of the above-mentioned problems, proposes a kind of based on FPGA solutions data in receiving network data length bag
The problem of loss.
Technical program of the present invention lies in：
One kind realizes network data reception control method based on FPGA, includes the following steps：
Step 1：During receiving network data, network frame head is determined whether by data reception module；It is to perform step 2 normally
Reception data manipulation is carried out, mistake then performs step 6；
Step 2：After network frame head correct judgment, then the data received are written to BRAM_IP buffering areas by data reception module
In, while the data received are counted by data reception module；And determine whether abnormal data, if normal data
Step 3 is then performed, if abnormal data, then performs step 6；
Step 3：BRAM_IP buffering area initial addresses are jumped into next byte；
Step 4：Carry out CRC check：CRC calculating is done to the valid data of reception, is carried out after the completion of calculating with the CRC of reception data
Compare, it is more identical, confirm that present networks bag data is correct, perform step 5, otherwise abandon the network data, perform step 6：
Step 5：The network packet receives normally, generates end-of-data mark, receiving network data length is written to FIFO_
IP buffering areas, the receive process of one packet network data of instruction are completed；
Step 6：Terminate data packet to receive, write length useful signal if having generated, generate end-of-data mark, generate simultaneously
Initial address during this write-in BRAM_IP buffering area is jumped to last time and writes end position, so that next by packet error mark
Receiving network data can re-write the BRAM_IP buffering areas；
Step 7：Data are continuously received by step 1- steps 6, until BRAM_IP buffer storage spaces are less than a bag maximum web
Network data stop network data and receive operation.
The abnormal data is network long packets or the ultrashort bag of network, and the network long packets byte number is more than
1518Byte, the ultrashort packet byte number of network are less than 48 Byte.
One kind realizes network data reading and control method thereof based on FPGA, and controlling party is received using network data as described above
After method, during digital independent include the following steps：
Step 1：Whether it is to have according in the condition adjudgement BRAM_IP buffering areas of FIFO_IP buffering areas when reading data message
The network state of effect, if dummy status, then clearly the corresponding data of the dummy status are abnormal data, stop digital independent；
Step 2：If FIFO_IP buffering areas are not sky, read according to the data length recorded in the FIFO_IP buffering areas
The data of the length in BRAM_IP buffering areas, complete the read operation of network packet.
The technical effects of the invention are that：
The present invention is in data receiver, by data information memory to BRAM_IP buffering areas, when data are normal information, by number
It is believed that the data length of breath is stored to FIFO_IP buffering areas, when receiving abnormal data, FIFO_IP buffering areas are dummy status；
Therefore, when reading information, first judged rather than directly read according to the data length of deposit FIFO_IP buffering areas
Data message in BRAM_IP buffering areas, and the data message in BRAM_IP buffering areas does not have sufficient space to store next bag
It receives and operates without network data during maximum network data, avoid network data packet loss problem.
Description of the drawings
Fig. 1 is inventive network data receiver process chart.
Fig. 2 receives valid data process chart for the present invention.
Fig. 3 receives dealing of abnormal data flow chart for the present invention.
Specific embodiment
One kind realizes network data reception control method based on FPGA, when receiving valid data, as shown in Fig. 2, including
Following steps：
Step 1：During receiving network data, network frame head is determined whether by data reception module；It is to perform step 2 normally
Carry out reception data manipulation；
Step 2：As shown in Fig. 2, after network frame head correct judgment, then the data received are written to by data reception module
In BRAM_IP buffering areas, write address is located at current data initial position when starting to receive data, it is assumed that write-in data are 8 words
The byte is stored in BRAM_IP buffering areas, while the data received is counted by data reception module by section；
Step 3：As shown in Fig. 2, BRAM_IP buffering area initial addresses are jumped into next byte；
Step 4：Carry out CRC check：CRC calculating is done to the valid data of reception, is carried out after the completion of calculating with the CRC of reception data
Compare, it is more identical, confirm that present networks bag data is correct；
Step 5：The network packet receives normally, generates end-of-data mark, receiving network data length is written to FIFO_
IP buffering areas, the receive process of one packet network data of instruction are completed, meanwhile, FIFO_IP buffering area initial addresses jump to next
Byte；
Step 6：Data are continuously received by step 1- steps 5, until BRAM_IP buffer storage spaces are less than a bag maximum web
Network data stop network data and receive operation.
When receiving wrong data, as shown in figure 3, the data received are written to BRAM_IP in data reception module
When in buffering area, data reception module counts the data received and is judged as abnormal data, then generates end of data
Mark, while generates packet error mark, and initial address during this write-in BRAM_IP buffering area jumped to last time writes end
Position, so that next receiving network data can re-write the BRAM_IP buffering areas；FIFO_IP buffering areas write start bit
It puts constant.
Wherein, the abnormal data is network long packets or the ultrashort bag of network, and the network long packets byte number is big
In 1518Byte, the ultrashort packet byte number of network is less than 48 Byte.
One kind realizes network data reading and control method thereof based on FPGA, include the following steps during digital independent：
Step 1：Whether it is to have according in the condition adjudgement BRAM_IP buffering areas of FIFO_IP buffering areas when reading data message
The network state of effect, if dummy status, then clearly the corresponding data of the dummy status are abnormal data, stop digital independent；
Step 2：If FIFO_IP buffering areas are not sky, read according to the data length recorded in the FIFO_IP buffering areas
The data of the length in BRAM_IP buffering areas, complete the read operation of network packet.
Claims (3)
1. one kind realizes network data reception control method based on FPGA, it is characterised in that：Include the following steps：
Step 1：During receiving network data, network frame head is determined whether by data reception module；It is to perform step 2 normally
Reception data manipulation is carried out, mistake then performs step 6；
Step 2：After network frame head correct judgment, then the data received are written to BRAM_IP buffering areas by data reception module
In, while the data received are counted by data reception module；And determine whether abnormal data, if normal data
Step 3 is then performed, if abnormal data, then performs step 6；
Step 3：BRAM_IP buffering area initial addresses are jumped into next byte；
Step 4：Carry out CRC check：CRC calculating is done to the valid data of reception, is carried out after the completion of calculating with the CRC of reception data
Compare, it is more identical, confirm that present networks bag data is correct, perform step 5, otherwise abandon the network data, perform step 6：
Step 5：The network packet receives normally, generates end-of-data mark, receiving network data length is written to FIFO_
IP buffering areas, the receive process of one packet network data of instruction are completed；
Step 6：Terminate data packet to receive, write length useful signal if having generated, generate end-of-data mark, generate simultaneously
Initial address during this write-in BRAM_IP buffering area is jumped to last time and writes end position, so that next by packet error mark
Receiving network data can re-write the BRAM_IP buffering areas；
Step 7：Data are continuously received by step 1- steps 6, until BRAM_IP buffer storage spaces are less than a bag maximum web
Network data stop network data and receive operation.
2. according to claim 1 realize network data reception control method based on FPGA, it is characterised in that：Described is different
Regular data is network long packets or the ultrashort bag of network, and the network long packets byte number is more than 1518Byte, the ultrashort bag of network
Byte number is less than 48 Byte.
3. one kind realizes network data reading and control method thereof based on FPGA, connect using the network data described in as above claim 2
After receiving control method, during digital independent include the following steps：
Step 1：Whether it is to have according in the condition adjudgement BRAM_IP buffering areas of FIFO_IP buffering areas when reading data message
The network state of effect, if dummy status, then clearly the corresponding data of the dummy status are abnormal data, stop digital independent；
Step 2：If FIFO_IP buffering areas are not sky, read according to the data length recorded in the FIFO_IP buffering areas
The data of the length in BRAM_IP buffering areas, complete the read operation of network packet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711447076.9A CN108073546A (en) | 2017-12-27 | 2017-12-27 | One kind realizes network data reception and reading and control method thereof based on FPGA |
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| CN201711447076.9A CN108073546A (en) | 2017-12-27 | 2017-12-27 | One kind realizes network data reception and reading and control method thereof based on FPGA |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110928486A (en) * | 2018-09-19 | 2020-03-27 | 爱思开海力士有限公司 | Memory system and operating method thereof |
| CN112073256A (en) * | 2020-06-01 | 2020-12-11 | 新华三信息安全技术有限公司 | Packet loss processing method, device, equipment and machine-readable storage medium |
| CN113204515A (en) * | 2021-06-02 | 2021-08-03 | 郑州信大捷安信息技术股份有限公司 | Flow control system and method in PCIE application layer data receiving process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110928486A (en) * | 2018-09-19 | 2020-03-27 | 爱思开海力士有限公司 | Memory system and operating method thereof |
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| CN113204515A (en) * | 2021-06-02 | 2021-08-03 | 郑州信大捷安信息技术股份有限公司 | Flow control system and method in PCIE application layer data receiving process |
| CN113204515B (en) * | 2021-06-02 | 2022-02-22 | 郑州信大捷安信息技术股份有限公司 | Flow control system and method in PCIE application layer data receiving process |
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Application publication date: 20180525 |