CN107452349A - A kind of drive circuit and liquid crystal display device - Google Patents
A kind of drive circuit and liquid crystal display device Download PDFInfo
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- CN107452349A CN107452349A CN201710698828.2A CN201710698828A CN107452349A CN 107452349 A CN107452349 A CN 107452349A CN 201710698828 A CN201710698828 A CN 201710698828A CN 107452349 A CN107452349 A CN 107452349A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of drive circuit and liquid crystal display device, its drive circuit is provided with time schedule controller, gate driving circuit and source electrode drive circuit；When opening power saving display pattern, the gate drive signal of each drive element of the grid output in same sub- gate driving circuit is identical, and m/mono- of the number of the source drive signal switching of source electrode drive circuit output when being color mode, so change the output signal of gate driving circuit and source electrode drive circuit, so as to be effectively saved power consumption, switching of the display picture from color mode to white-black pattern can be also realized.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of drive circuit and liquid crystal display device.
Background technology
Liquid crystal display device (Liquid Crystal Display, LCD) have image quality is good, small volume, in light weight, low drive
The advantages of dynamic voltage, low-power consumption, relatively low radiationless and manufacturing cost, occupied an leading position at present in flat display field.With
The progress of lcd technology, people are to the display quality of liquid crystal display, appearance design, high-res, low-power consumption
The higher requirement Deng feature extraction.
Fig. 1 is the part equivalent circuit structure schematic diagram of existing liquid crystal display device.Liquid crystal display device includes display
Panel and drive circuit.Display panel includes multiple pixel cells, and each pixel cell includes red sub-pixel R, green
Sub-pixel G and blueness sub-pixel B.The basic functional principle of liquid crystal display panel and drive circuit is：Gate driving circuit leads to
Cross with pulling up transistor of being electrically connected with of scan line to scan line send out gate drive signal Gn (only shown in Fig. 1 G1, G2,
G3), sequentially to open the thin film transistor (TFT) (TFT) of every a line, and data is sent out to data wire by source electrode drive circuit and believed
Number Dn (D1, D2, D3 are only shown in Fig. 1), so as to which the pixel cell of a full line to be charged to each required voltage simultaneously, with
Show different GTGs.Pulled up transistor first by the gate driving circuit of the first row by it by the film crystal of the first row
Pipe is opened, and then the sub-pixel of the first row is charged by source electrode drive circuit.When the pixel cell of the first row is charged, grid
Pole drive circuit just closes the row thin film transistor (TFT), and then the gate driving circuit of the second row is pulled up transistor the by it
The thin film transistor (TFT) of two rows is opened, then carries out discharge and recharge to the sub-pixel of the second row by source electrode drive circuit.So sequentially go down,
When the pixel cell of last column of having substituted the bad for the good, just started to charge up again from the first row.
When carrying out display picture, each pixel is scanned line by line, every a line gate driving circuit and each row source electrode
Drive circuit output signal frequency matches.However, no matter this display device is it is shown which kind of image mode, used in it shows
Power consumption is constant all the time, it is impossible to meets the requirement of low-power consumption of the people to liquid crystal display.
The content of the invention
In view of this, present invention aims at a kind of drive circuit and liquid crystal display device is provided, to solve to liquid crystal
Show the requirement of the low-power consumption of device.
Specifically, drive circuit provided by the invention, to drive display panel, including time schedule controller, raster data model
Circuit and source electrode drive circuit；The time schedule controller, for exporting grid clock signal to the gate driving circuit, and it is defeated
Go out source electrode clock signal to source electrode drive circuit；The gate driving circuit includes more sub- raster data model electricity being arranged in order
Road, every sub- gate driving circuit include m drive element of the grid, and every grade of drive element of the grid is used for according to the grid
Clock signal exports this grade of gate drive signal to corresponding sub-pixel；The source electrode drive circuit is used for according to the sequential control
The source electrode clock signal generation source drive signal of device input processed；Wherein, during power saving display pattern, same sub- gate driving circuit
In each drive element of the grid output gate drive signal it is identical, and source electrode drive circuit output source drive signal cut
The number changed is m/mono- of color mode.
In one embodiment of the invention, every sub- gate driving circuit includes m drive element of the grid, wherein, m etc.
In 3 or 4.
In one embodiment of the invention, in power saving display pattern, the grid of the sub- gate driving circuit output
The frequency of drive signal is identical with frequency during color mode, and the frequency of the source drive signal of the source electrode drive circuit output is
M/mono- of frequency during color mode.
In one embodiment of the invention, sub-pixel corresponding to the sub- gate driving circuit includes red sub- picture
The sub-pixel of element, the sub-pixel of green and blueness.
In one embodiment of the invention, sub-pixel corresponding to the sub- gate driving circuit includes red sub- picture
Element, the sub-pixel of green, the sub-pixel of blueness and white sub-pixel.
In one embodiment of the invention, all sub-pixels of each pixel cell are located at same a line, and each
The arrangement mode of the sub-pixel of pixel cell is identical.
In one embodiment of the invention, the instruction of the time schedule controller reception pattern switching, and according to the mould
Grid clock signal corresponding to the instruction output of formula switching, the instruction are inputted by user by input equipment.
In one embodiment of the invention, during power saving display pattern, the time schedule controller is exported to same sub- grid
The grid clock signal of each drive element of the grid in drive circuit is identical.
In one embodiment of the invention, the drive element of the grid includes：First switching element, including the first path
End, alternate path end and the first control terminal, first control terminal receive the first pulse signal, and first path terminal receives ginseng
Examine high voltage；Second switch element, including third path end, fourth passage end and the second control terminal, the second control termination
The second pulse signal is received, the fourth passage end receives and refers to high voltage；3rd switch element, including fifth passage end, the 6th
Path terminal and the 3rd control terminal, the fifth passage end connect first grid clock signal, and the 6th path terminal exports this level
Gate drive signal, the alternate path end of the 3rd control terminal and the first switching element and the second switch element
Third path end is connected；4th switch element, including the 7th path terminal, the 8th path terminal and the 4th control terminal, the described 7th is logical
Terminal connects the 6th path terminal of the 3rd switch element, and the 8th path terminal receives low reference voltage, the 4th control
End processed connects the 4th grid clock signal；Wherein, in addition to preceding three-level drive element of the grid, first pulse signal is upward phase
The upper three-level grid clock signal of the drive element of the grid output of poor three-level；In addition to rear three-level drive element of the grid, described second
The lower three-level grid clock signal that pulse signal exports for the drive element of the grid of difference three-level downwards.
The present invention also provides a kind of liquid crystal display device, and the liquid crystal display device includes above-mentioned drive circuit and display
Panel.
The drive circuit and liquid crystal display device of the present invention is when opening power saving display pattern, same sub- gate driving circuit
In each drive element of the grid output gate drive signal it is identical, and source electrode drive circuit output source drive signal cut
M/mono- when the number changed is color mode, the output signal of gate driving circuit and source electrode drive circuit is so changed,
So as to be effectively saved power consumption, switching of the display picture from color mode to white-black pattern can be also realized.
Brief description of the drawings
Fig. 1 is the part equivalent circuit structure schematic diagram of existing liquid crystal display device.
Fig. 2 is the structural representation of the drive circuit of first embodiment of the invention.
Fig. 3 is the circuit diagram of the drive element of the grid of first embodiment of the invention.
Fig. 4 is the structural representation of the gate driving circuit of first embodiment of the invention.
Fig. 5 is the sequential for the grid clock signal that the time schedule controller of first embodiment of the invention exports in color mode
Schematic diagram.
Fig. 6 is the grid clock signal that the time schedule controller of first embodiment of the invention exports in power saving display pattern
Time diagram.
Fig. 7 is that the gate drive signal that the drive circuit of first embodiment of the invention exports in color mode drives with source electrode
The time diagram of dynamic signal.
Fig. 8 is the gate drive signal and source that the drive circuit of first embodiment of the invention exports in power saving display pattern
The time diagram of pole drive signal.
Fig. 9 is the structural representation of the drive circuit of second embodiment of the invention.
Figure 10 is the circuit diagram of the drive element of the grid of second embodiment of the invention.
Figure 11 be the grid clock signal that is exported in color mode of time schedule controller of second embodiment of the invention when
Sequence schematic diagram.
Figure 12 is the grid clock signal that the time schedule controller of second embodiment of the invention exports in power saving display pattern
Time diagram.
Embodiment
With reference to embodiment and compare accompanying drawing the present invention is described in further details.
First embodiment
As shown in Fig. 2 the structural representation of the drive circuit for first embodiment of the invention.As shown in Fig. 2 the present invention carries
The drive circuit of confession, to drive display panel 101.Drive circuit includes time schedule controller 110, the and of gate driving circuit 120
Source electrode drive circuit 130.
Wherein, time schedule controller 110 is used to export grid clock signal to gate driving circuit 120, and when exporting source electrode
Sequential signal is to source electrode drive circuit 130.
Gate driving circuit 120 includes more sub- gate driving circuits being arranged in order, every sub- gate driving circuit bag
M drive element of the grid is included, specifically, m can be equal to 3 or 4, and m is equal to 3 in the present embodiment one, and every grade of drive element of the grid is used for
This grade of gate drive signal Gn (n be equal to 1,2,3 ... N) is exported to corresponding sub-pixel according to grid clock signal, wherein, N
For the integer more than or equal to m.
Source electrode drive circuit 130 is used for the source electrode clock signal generation source drive letter inputted according to time schedule controller 110
Number Sn (S1, S2, S3 are only shown in Fig. 2).
In color mode, drive circuit progressively scans each pixel, and every grade of drive element of the grid exports this grade of grid and driven
The dynamic signal Gn and source drive signal Sn exported per data line line frequency matches, and source electrode drive circuit 130 is each only
The sub-pixel of certain a line is charged.
In power saving display pattern, the raster data model of every grade of drive element of the grid output in same sub- gate driving circuit
Signal is identical, the gate drive signal exported such as every grade of drive element of the grid in the first sub- gate driving circuit G1X in Fig. 2
G1, G2, G3 are identical.Moreover, when the number for the source drive signal Sn switchings that source electrode drive circuit 130 exports is color mode
M/mono-.Now, gate driving circuit 120 is not to be scanned each sub-pixel line by line, but m rows are scanned simultaneously, institute
So that the source drive signal Sn that source electrode drive circuit 130 exports charges to this m row sub-pixel every time, therefore source drive is believed
M/mono- when the number of number Sn switching is color mode, such source drive signal Sn refreshing frequency reduces, so as to drop
The low power consumption of system.
In the present embodiment, in power saving display pattern, the frequency for the gate drive signal Gn that gate driving circuit 120 exports
Rate is identical with frequency during color mode, and the frequency for the source drive signal Sn that source electrode drive circuit 130 exports is color mode
When frequency 1/3rd, so as to reach power saving effect.In addition, each drive element of the grid of same sub- gate driving circuit
The gate drive signal of high level is all exported to corresponding pixel cell so that the sub-pixel on three horizontal scanning lines passes through source simultaneously
Pole drive signal Sn is charged, and controls source electrode drive circuit 130 to export corresponding source drive signal Sn, so as to reach
Switching from color mode to white-black pattern.
Preferably, sub-pixel corresponding to this example gate driving circuit be red sub-pixel R, the sub-pixel G of green and
The sub-pixel B of blueness.The light color that this three sub-pixel is sent is the three primary colors of light, can be presented after light mixing different
Color.During so as to, power saving display pattern, source electrode drive circuit 130 exports specific source drive signal Sn, and drive circuit can be with
Driving display panel 101 realizes the switching of color mode and white-black pattern.
More preferably, all sub-pixels of each pixel cell are located at same a line, and the row of the sub-pixel of each pixel cell
Row mode is identical, in specific the present embodiment, the red sub-pixel R of pixel cell, the sub-pixel G of green and blueness sub-pixel
B is located at same a line, and the arrangement mode of the sub-pixel of each pixel cell is identical, as shown in Fig. 2 the sub- picture of each pixel cell
Plain red sub-pixel R, the sub-pixel G of green and the sub-pixel B of blueness are arranged in order.
More preferably, the instruction of the reception pattern of time schedule controller 110 switching, and according to corresponding to the instruction of pattern switching output
Grid clock signal.Instruction can be, but not limited to be inputted by input equipment by user.
In the present embodiment, during power saving display pattern, time schedule controller 110 is supplied in same sub- gate driving circuit
The grid clock signal of each drive element of the grid is identical, and being supplied in this sub- gate driving circuit when being color mode
First drive element of the grid grid clock signal.Such as first every grade of raster data model in sub- gate driving circuit G1X
The gate drive signal G1 of unit output, G2, G3 is identical, and offer when gate drive signal G1, G2, G3 are color modes
Grid clock signal to first drive element of the grid in this first sub- gate driving circuit G1X.
Fig. 3 is the circuit diagram of the drive element of the grid of first embodiment of the invention.Every grade of drive element of the grid includes
First switching element T1, second switch element T2, the 3rd switch element T3 and the 4th switch element T4.
It is by taking the first order drive element of the grid of first embodiment of the invention as an example in Fig. 3.First switching element T1 includes
First path terminal, alternate path end and the first control terminal, the first control terminal receive the first pulse signal, and the first path terminal receives ginseng
Examine high voltage VDD.Second switch element T2 includes third path end, fourth passage end and the second control terminal, the second control termination
The second pulse signal is received, fourth passage end receives low reference voltage VSS.3rd switch element T3 includes fifth passage end, the 6th
Path terminal and the 3rd control terminal, fifth passage end connection first grid clock signal CLK1, the 6th path terminal export this level
Gate drive signal Gn, the 3rd control terminal and first switching element T1 alternate path end and second switch element T2 threeway
Terminal is connected.4th switch element T4, including the 7th path terminal, the 8th path terminal and the 4th control terminal, the connection of the 7th path terminal
3rd switch element T3 the 6th path terminal, the 8th path terminal receive low reference voltage VGL, and the 4th control terminal connects the 4th grid
Clock signal CLK4.Wherein, in addition to preceding three-level drive element of the grid, the first pulse signal is the upward raster data model for differing three-level
The upper three-level grid clock signal Gn-3 of unit output；In addition to rear three-level drive element of the grid, the second pulse signal is downward phase
The lower three-level grid clock signal Gn+3 of the drive element of the grid output of poor three-level.Wherein, due to preceding three-level drive element of the grid
Without the drive element of the grid for differing three-level upwards, rear three-level drive element of the grid is without the raster data model list for differing three-level downwards
Member, so the first pulse signal that preceding three-level drive element of the grid receives, the second pulse that rear three-level drive element of the grid receives
Signal is intended to be provided by external signal circuit.
In first embodiment of the invention, every grade of drive element of the grid also includes stablizing unit, in raster data model
When signal Gn is in low-voltage, gate drive signal Gn is set to maintain low reference voltage VGL.
Fig. 4 is the structural representation of the gate driving circuit of first embodiment of the invention.Fig. 4 only depicts the grid of the first six grade
The circuit connection of pole driver element, the circuit that gate driving circuit is illustrated with this connect.As seen from Figure 4, per one-level grid
Pole driver element includes five inputs, and an output end.Wherein, five inputs difference of i-stage drive element of the grid
Receive low with reference to high voltage VDD, grid clock signal CLKi, grid clock signal CLK (i+3), low reference voltage VSS and reference
Voltage VGL, output end are used to export this grade of gate drive signal Gn.Such as Fig. 4, first order drive element of the grid is used to receive first
Grid clock signal CLK1 and the 4th grid clock signal CLK4, and export first order gate drive signal G1.Second level grid
Driver element exports second level gate drive signal G2, receives second grid clock signal CLK2 and the 5th grid clock signal
CLK5.And using 9 grid clock signals as a repetitive cycling, i.e. the 7th grade of drive element of the grid can be released and receive the 7th grid
Pole clock signal CLK7 and first grid clock signal CLK1, and connection of every one-level drive element of the grid can be analogized with this.
Also, in addition to preceding three-level drive element of the grid, the first pulse signal that drive element of the grid receives is difference upwards
The upper three-level grid clock signal Gn-3 of the drive element of the grid output of three-level, in Fig. 4, fourth stage drive element of the grid receives
Upper three-level grid clock signal G1, level V drive element of the grid receive upper three-level grid clock signal G2；Except rear three-level grid
Outside driver element, the second pulse signal is the lower three-level grid clock signal Gn of the drive element of the grid output of difference three-level downwards
+ 3, in Fig. 4, first order drive element of the grid receives upper three-level grid clock signal G4, and second level drive element of the grid receives
Upper three-level grid clock signal G5 etc..Wherein, because preceding three-level drive element of the grid is without the raster data model for differing three-level upwards
Unit, rear three-level drive element of the grid is without the drive element of the grid for differing three-level downwards, so preceding three-level drive element of the grid
The first pulse signal received, the second pulse signal that rear three-level drive element of the grid receives are intended to be carried by external signal circuit
For, in Fig. 4, first grid driver element receives external signal STV1, and second grid driver element receives external signal STV2,
3rd drive element of the grid receives external signal STV3.
Fig. 5 is the sequential for the grid clock signal that the time schedule controller of first embodiment of the invention exports in color mode
Schematic diagram.As shown in figure 5, in color mode first grid clock signal to the 9th grid clock signal CLK1~CLK9 successively
Switching to high level from low level, first grid clock signal to the 9th grid clock signal CLK1~CLK9 cycle phase are same, and
First grid clock signal to the 9th grid clock signal CLK1~CLK9 interval times for switching to high level by low level are nine
/ a cycle.
Fig. 6 is the grid clock signal that the time schedule controller of first embodiment of the invention exports in power saving display pattern
Time diagram.Wherein, first grid clock signal CLK1, second grid clock signal CLK2, the 3rd grid clock signal
CLK3 signal is identical, the 4th grid clock signal CLK4, the 5th grid clock signal CLK5, the 6th grid clock signal CLK6
Signal it is identical, the 7th grid clock signal CLK7, the 8th grid clock signal CLK8, the 9th grid clock signal CLK9 letter
It is number identical.First grid clock signal CLK1, the 4th grid clock signal CLK4, the 7th grid clock signal CLK7 are successively from low
Level switchs to high level, and it is three/a cycle to switch to interval time of high level by low level, high electricity in each cycle
It is flat to hold time as three/a cycle.
Wherein, in power saving display pattern, the course of work per one-level drive element of the grid can be divided into pre-charging stage, on
Drawing stage, drop-down stage, 4 stages of stabilization sub stage：
Pre-charging stage is the first stage：The grid for the upward difference three-level that first switching element T1 the first control terminal receives
The gate drive signal Gn-3 of the upward difference three-level of pole driver element output is high level, first switching element T1 conductings, is saved
Voltage at point Q is driven high by the first switching element T1 of conducting, the first switching element that the voltage at node Q passes through conducting
T1 is referenced high voltage VDD precharge, the 3rd switch element T3 conductings；
The pull-up stage is second stage：When first grid clock signal CLK1 is changed into high level from low level, due to
Pre-charging stage node Q has been precharged, therefore, the 3rd switch element T3 conductings so that this grade of gate drive signal Gn leads to
The 3rd switch element T3 for crossing conducting is drawn high by first grid clock signal CLK1；
The drop-down stage is the phase III：First grid clock signal CLK1 is changed into low level from high level, due to pulling up
Voltage is high level at stage node Q, and the 3rd switch element T3 is turned on, and this grade of gate drive signal Gn opens by the 3rd of conducting
Element T3 is closed to be pulled low, meanwhile, when the 4th signal CLK4 is changed into high level from low level, this grade of gate drive signal Gn
Low reference voltage VGL is pulled low to by the 4th switch element T4 of conducting；
Further, since the gate drive signal Gn+3 of difference three-level is changed into high level, second switch member from low level downwards
Part T2 is turned on, therefore node Q is pulled low by the second switch element T2 of conducting, and the 3rd Katyuan part T3 is closed；
Stabilization sub stage is fourth stage：Because the voltage at the drop-down stage, node Q is pulled low, therefore, the 3rd switch member
Part T3 is closed, and avoids influences of the first grid clock signal CLK1 to this grade of gate drive signal Gn.
More than, only it is presently preferred embodiments of the present invention, in battery saving mode, does not limit same sub- raster data model electricity
The grid clock signal of the reception of each drive element of the grid in road must be identical, if the grid in same sub- gate driving circuit
The physical circuit of pole driver element is different, and the grid clock signal of the reception of each drive element of the grid may also be different, as long as
Meet the category of the identical as technical solution of the present invention of gate drive signal of same sub- gate driving circuit output.
The corresponding relation figure of gate drive signal and source drive signal when Fig. 7 is color mode of the present invention.Can from Fig. 7
To find out, the gate drive signal Gn (such as G1, G2, G3 etc.) at different levels of above-described embodiment switch to high level from low level successively,
And the interval times at different levels for switching to high level by low level are T, source corresponding to the data wire that source electrode drive circuit exports in addition
Pole drive signal Sn switches once every T time.
The corresponding relation figure of gate drive signal and source drive signal when Fig. 8 is power saving display pattern of the present invention.Can
To find out, the gate drive signal of above-described embodiment, the grid of the drive element of the grid output of same sub- gate driving circuit drives
Dynamic signal is identical, as first gate driving signal G1, second grid drive signal G2, the 3rd gate drive signal G3 are equal, the
Four gate drive signal G4, the 5th gate drive signal G5, the 6th gate drive signal G6 are equal, the like.And press grid
It is that same sub- gate driving circuit is one group belonging to driver element, the gate drive signal of drive element of the grid output presses group successively
Switch to high level from low level, and the interval time that each group switchs to high level by low level is 3T, source electrode drive circuit is defeated in addition
Source drive signal Sn corresponding to the data wire gone out every 3T time-switchings once.I.e. compared with color mode, source drive
The frequency of the source drive signal of circuit output is changed into original 1/3rd, so as to reach the purpose for reducing system power dissipation.
Also include a kind of liquid crystal display device in present embodiment, liquid crystal display device includes above-mentioned drive circuit
And display panel.
Second embodiment
As shown in figure 9, the structural representation of the drive circuit for second embodiment of the invention.As shown in figure 9, the present invention carries
The drive circuit of confession, to drive display panel 101.Drive circuit includes time schedule controller 110, the and of gate driving circuit 120
Source electrode drive circuit 130.
Wherein, time schedule controller 110 is used to export grid clock signal to gate driving circuit 120, and when exporting source electrode
Sequential signal is to source electrode drive circuit 130.
Gate driving circuit 120 includes more sub- gate driving circuits being arranged in order, every sub- gate driving circuit bag
4 (m is equal to 4) individual drive element of the grid are included, every grade of drive element of the grid is used to export this grade of grid drive according to grid clock signal
Dynamic signal Gn (n is equal to 1,2,3 ... N) to corresponding sub-pixel, wherein, N is the integer more than or equal to m.Source drive electricity
The source electrode clock signal generation source drive signal Sn that road 130 is used to be inputted according to time schedule controller 110 (is only shown in Fig. 9
S1、S2、S3)。
In color mode, drive circuit progressively scans each pixel, and every grade of drive element of the grid exports this grade of grid and driven
The dynamic signal Gn and source drive signal Sn exported per data line line frequency matches, and source electrode drive circuit 130 is each only
The sub-pixel of certain a line can be charged.
In the present embodiment, in power saving display pattern, every grade of drive element of the grid in same sub- gate driving circuit
The gate drive signal of output is identical, in Fig. 9, every grade of drive element of the grid output in the first sub- gate driving circuit G1X
Gate drive signal G1, G2, G3, G4 it is identical.Moreover, the source drive signal Sn switchings that source electrode drive circuit 130 exports
A quarter when number is color mode.Now, gate driving circuit 120 is not to be scanned each sub-pixel line by line, and
It is four rows while is scanned, so, the source drive signal Sn that source electrode drive circuit 130 exports is every time to this four rows sub-pixel
Charged.The frequency for the gate drive signal Gn that gate driving circuit 120 exports is identical with frequency during color mode, source electrode
The a quarter of frequency, such source drive when the frequency for the source drive signal Sn that drive circuit 130 exports is color mode
Signal Sn refreshing frequency reduces, and so as to reduce the power consumption of system, has reached power saving effect.In addition, same sub- grid drives
Each drive element of the grid of dynamic circuit exports the gate drive signal of high level to corresponding sub-pixel so that four rows scan
Sub-pixel on line is charged by source drive signal Sn simultaneously, and controls source electrode drive circuit 130 to export corresponding source
Pole drive signal Sn, so as to reach the switching from color mode to white-black pattern.
Preferably, the sub-pixel of the pixel in present embodiment is the sub-pixel R, green sub-pixel G, indigo plant of red
The sub-pixel B of the color and sub-pixel W of white.The light color that first three sub-pixel is sent is the three primary colors of light, and light mixing can
So that different colors is presented, and the sub-pixel of white plays the role of to adjust brightness.So that during power saving display pattern, source drive
The specific source electrode drive signal of circuit output, circuit can realize the switching of color mode and white-black pattern.
More preferably, all sub-pixels of each pixel cell are located at same a line, and the row of the sub-pixel of each pixel cell
Row mode is identical, in specific the present embodiment, the red sub-pixel R of pixel cell, the sub-pixel G of green, the sub-pixel B of blueness
It is located at same a line with the sub-pixel W of white, and the arrangement mode of the sub-pixel of each pixel cell is identical, as shown in figure 9, each
The red sub-pixel R of the sub-pixel of pixel cell, the sub-pixel G of green, the sub-pixel B of blueness and white sub-pixel W according to
Secondary arrangement.
More preferably, the instruction of the reception pattern of time schedule controller 110 switching, and according to corresponding to the instruction of pattern switching output
Grid clock signal.Instruction can be, but not limited to be inputted by input equipment by user.
In the present embodiment, during power saving display pattern, time schedule controller 110 is supplied in same sub- gate driving circuit
The grid clock signal of each drive element of the grid is identical, and being supplied in this sub- gate driving circuit when being color mode
First drive element of the grid grid clock signal.Such as in Fig. 9, every grade of grid in the first sub- gate driving circuit G1X
The gate drive signal G1 of pole driver element output, G2, G3, G4 is identical, and gate drive signal G1, G2, G3, G4 are colored
The grid clock signal of first drive element of the grid being supplied in this first sub- gate driving circuit G1X during pattern.
Figure 10 is the circuit diagram of the drive element of the grid of second embodiment of the invention.Be in Figure 10 with the present invention the
Exemplified by the first order drive element of the grid of two embodiments.Every grade of drive element of the grid includes first switching element T1, second switch
Element T2, the 3rd switch element T3 and the 4th switch element T4.
Wherein, first switching element T1 includes the first path terminal, alternate path end and the first control terminal, the first control termination
The first pulse signal is received, the first path terminal receives and refers to high voltage VDD.Second switch element T2 includes third path end, the 4th
Path terminal and the second control terminal, the second control terminal receive the second pulse signal, and fourth passage end receives low reference voltage VSS.The
Three switch element T3 include fifth passage end, the 6th path terminal and the 3rd control terminal, fifth passage end connection first grid sequential
Signal CLK1, the 6th path terminal export this grade of gate drive signal Gn, and the of the 3rd control terminal and first switching element T1
Two path terminals and second switch element T2 third path end are connected.4th switch element T4, including it is the 7th path terminal, the 8th logical
Terminal and the 4th control terminal, the 7th path terminal connect the 3rd switch element T3 the 6th path terminal, and the 8th path terminal receives reference
Low-voltage VGL, the 4th control terminal connect the 4th grid clock signal CLK4.Wherein, in addition to preceding level Four drive element of the grid, first
The upper level Four grid clock signal Gn-4 that pulse signal exports for the drive element of the grid of difference level Four upwards；Except rear level Four grid
Outside driver element, the second pulse signal is the lower level Four grid clock signal Gn of the drive element of the grid output of difference level Four downwards
+4.Wherein, because preceding level Four drive element of the grid is without the drive element of the grid for differing level Four upwards, rear level Four raster data model list
Member is without the drive element of the grid for differing level Four downwards, the first pulse signal of the former level Four drive element of the grid reception of institute, after
The second pulse signal that level Four drive element of the grid receives is intended to be provided by external signal circuit.
In second embodiment of the invention, every grade of drive element of the grid also includes stablizing unit, in raster data model
When signal Gn is in low-voltage, gate drive signal Gn is set to maintain low reference voltage VGL.
Figure 11 be the grid clock signal that is exported in color mode of time schedule controller of second embodiment of the invention when
Sequence schematic diagram.As shown in figure 11, in color mode first grid clock signal to the 12nd grid clock signal CLK1~
CLK12 switchs to high level from low level successively, and first grid clock signal is to the 12nd grid clock signal CLK1~CLK12's
Cycle phase is same, and first grid clock signal switchs to high level to the 12nd grid clock signal CLK1~CLK12 by low level
Interval time be ten half cycles.
Figure 12 is the grid clock signal that the time schedule controller of second embodiment of the invention exports in power saving display pattern
Time diagram.Wherein, first grid clock signal CLK1, second grid clock signal CLK2, the 3rd grid clock signal
CLK3, the 4th grid clock signal CLK4 signal are identical, the 5th grid clock signal CLK5, the 6th grid clock signal
CLK6, the 7th grid clock signal CLK7, the 8th grid clock signal CLK8 signal are identical, the 9th grid clock signal
CLK9, the tenth grid clock signal CLK10, the 11st grid clock signal CLK11, the 12nd grid clock signal CLK12
Signal is identical.First grid clock signal CLK1, the 5th grid clock signal CLK5, the 9th grid clock signal CLK9 successively from
Low level switchs to high level, and it is three/a cycle to switch to interval time of high level by low level, high in each cycle
Level is held time as three/a cycle.
Wherein, in power saving display pattern, the course of work per one-level drive element of the grid can be divided into pre-charging stage, on
Drawing stage, drop-down stage, 4 stages of stabilization sub stage：
Pre-charging stage is the first stage：The grid for the upward difference level Four that first switching element T1 the first control terminal receives
The gate drive signal Gn-4 of the upward difference level Four of pole driver element output is high level, first switching element T1 conductings, is saved
Voltage at point Q is driven high by the first switching element T1 of conducting, the first switching element that the voltage at node Q passes through conducting
T1 is referenced high voltage VDD precharge, the 3rd switch element T3 conductings；
The pull-up stage is second stage：When first grid clock signal CLK1 is changed into high level from low level, due to
Pre-charging stage node Q has been precharged, therefore, the 3rd switch element T3 conductings so that this grade of gate drive signal Gn leads to
The 3rd switch element T3 for crossing conducting is drawn high by first grid clock signal CLK1；
The drop-down stage is the phase III：First grid clock signal CLK1 is changed into low level from high level, due to pulling up
Voltage is high level at stage node Q, and the 3rd switch element T3 is turned on, and this grade of gate drive signal Gn opens by the 3rd of conducting
Element T3 is closed to be pulled low, meanwhile, when the 4th signal CLK4 is changed into high level from low level, this grade of gate drive signal Gn
Low reference voltage VGL is pulled low to by the 4th switch element T4 of conducting；
Further, since the gate drive signal Gn+4 of difference level Four is changed into high level, second switch member from low level downwards
Part T2 is turned on, therefore node Q is pulled low by the second switch element T2 of conducting, and the 3rd Katyuan part T3 is closed；
Stabilization sub stage is fourth stage：Because the voltage at the drop-down stage, node Q is pulled low, therefore, the 3rd switch member
Part T3 is closed, and avoids influences of the first grid clock signal CLK1 to this grade of gate drive signal Gn.
More than, only it is presently preferred embodiments of the present invention, in battery saving mode, does not limit same sub- raster data model electricity
The grid clock signal of the reception of each drive element of the grid in road must be identical, if the grid in same sub- gate driving circuit
The physical circuit of pole driver element is different, and the grid clock signal of the reception of each drive element of the grid may also be different, as long as
Meet the category of the identical as technical solution of the present invention of gate drive signal of same sub- gate driving circuit output.
Also include a kind of liquid crystal display device in present embodiment, liquid crystal display device includes above-mentioned drive circuit
And display panel.
The drive circuit and liquid crystal display device of the present invention, provided with time schedule controller, gate driving circuit and source drive
Circuit；When opening power saving display pattern, the raster data model of each drive element of the grid output in same sub- gate driving circuit
Signal is identical, and m/mono- of the number of the source drive signal switching of source electrode drive circuit output when being color mode, so
The output signal of gate driving circuit and source electrode drive circuit is changed, so as to be effectively saved power consumption, can also realize display
Switching of the picture from color mode to white-black pattern.
More than, only it is presently preferred embodiments of the present invention, any formal limitation not is made to the present invention, although this
Invention is disclosed above with preferred embodiment, but is not limited to invent, any person skilled in the art, not
Depart from the range of inventive technique scheme, when the technology contents using the disclosure above make a little change or are modified to equivalent variations
Equivalent embodiment, as long as being without departing from inventive technique scheme content, the technical spirit according to invention is made to above example
Any simple modification, equivalent change and modification, in the range of still falling within technical solution of the present invention.
Claims (10)
1. a kind of drive circuit, to drive display panel, it is characterised in that the drive circuit includes time schedule controller, grid
Pole drive circuit and source electrode drive circuit；
The time schedule controller, for exporting grid clock signal to the gate driving circuit, and export source electrode clock signal
To the source electrode drive circuit；
The gate driving circuit includes more sub- gate driving circuits being arranged in order, and every sub- gate driving circuit includes m
Individual drive element of the grid, every grade of drive element of the grid are used to export this grade of gate drive signal extremely according to the grid clock signal
Corresponding sub-pixel；
The source electrode clock signal that the source electrode drive circuit is used to be inputted according to the time schedule controller generates source drive
Signal；
Wherein, during power saving display pattern, the raster data model of each drive element of the grid output in same sub- gate driving circuit
Signal is identical, and m/mono- of the number of the source drive signal switching of source electrode drive circuit output when being color mode.
2. drive circuit as claimed in claim 1, it is characterised in that every sub- gate driving circuit includes m raster data model
Unit, wherein, m is equal to 3 or 4.
3. drive circuit as claimed in claim 1, it is characterised in that in power saving display pattern, the sub- raster data model electricity
The frequency of the gate drive signal of road output is identical with frequency during color mode, the source drive of the source electrode drive circuit output
M/mono- of frequency when the frequency of signal is color mode.
4. drive circuit as claimed in claim 1, it is characterised in that sub-pixel corresponding to the sub- gate driving circuit includes
Red sub-pixel, the sub-pixel of green and blue sub-pixel.
5. drive circuit as claimed in claim 1, it is characterised in that sub-pixel corresponding to the sub- gate driving circuit includes
Red sub-pixel, the sub-pixel of green, the sub-pixel of blueness and white sub-pixel.
6. drive circuit as claimed in claim 1, it is characterised in that all sub-pixels of each pixel cell are positioned at same
OK, and the sub-pixel of each pixel cell arrangement mode it is identical.
7. drive circuit as claimed in claim 1, it is characterised in that the instruction of the time schedule controller reception pattern switching,
And the grid clock signal according to corresponding to the instruction of pattern switching output, the instruction are defeated by input equipment by user
Enter.
8. drive circuit as claimed in claim 7, it is characterised in that in power saving display pattern, the time schedule controller is defeated
The grid clock signal gone out to each drive element of the grid in same sub- gate driving circuit is identical.
9. drive circuit as claimed in claim 1, it is characterised in that the drive element of the grid includes：
First switching element, including the first path terminal, alternate path end and the first control terminal, first control terminal receive first
Pulse signal, first path terminal receive and refer to high voltage；
Second switch element, including third path end, fourth passage end and the second control terminal, second control terminal receive second
Pulse signal, the fourth passage end receive low reference voltage；
3rd switch element, including fifth passage end, the 6th path terminal and the 3rd control terminal, the fifth passage end connection first
Grid clock signal, the 6th path terminal export this grade of gate drive signal, the 3rd control terminal and the first switch
The alternate path end of element and the third path end of the second switch element are connected；
4th switch element, including the 7th path terminal, the 8th path terminal and the 4th control terminal, described in the 7th path terminal connection
6th path terminal of the 3rd switch element, the 8th path terminal receive low reference voltage, the 4th control terminal connection the 4th
Grid clock signal；
Wherein, in addition to preceding three-level drive element of the grid, first pulse signal is the upward drive element of the grid for differing three-level
The upper three-level gate drive signal of output；In addition to rear three-level drive element of the grid, second pulse signal is difference three downwards
The lower three-level gate drive signal of the drive element of the grid output of level.
10. a kind of liquid crystal display device, it is characterised in that the liquid crystal display device is included such as any one of claim 1-9
Described drive circuit and display panel.
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| CN112447145A (en) * | 2019-08-29 | 2021-03-05 | 北京小米移动软件有限公司 | Display panel, display mode switching method and device and electronic equipment |
| CN113903315A (en) * | 2019-01-31 | 2022-01-07 | 联咏科技股份有限公司 | Driving device of display panel and operation method thereof |
| US20220415232A1 (en) * | 2020-06-30 | 2022-12-29 | Hefei Boe Display Technology Co., Ltd. | Driving method and driving circuit of display panel, and display apparatus |
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