CN107436752B - Abnormal site recovery method and device and computer readable storage medium - Google Patents
Abnormal site recovery method and device and computer readable storage medium Download PDFInfo
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- CN107436752B CN107436752B CN201710594077.XA CN201710594077A CN107436752B CN 107436752 B CN107436752 B CN 107436752B CN 201710594077 A CN201710594077 A CN 201710594077A CN 107436752 B CN107436752 B CN 107436752B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0715—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a system implementing multitasking
Abstract
The application provides an abnormal site recovery method, an abnormal site recovery device and a computer readable storage medium, wherein the method comprises the following steps: and acquiring an execution exception return instruction, wherein the exception return instruction comprises an operation code, the operation code is used for instructing the processor to execute the last instruction of the exception handling function, executing the exception return instruction to modify the value of the program counter and pop the information pressed into the target register file of the exception stack from the exception stack, and returning to continue executing the interrupted normal handling function. According to the technical scheme, software codes are not needed to recover abnormal fields, the occupied space and power consumption of the software codes are reduced, and the execution efficiency of the processor is improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for recovering an abnormal site, and a computer-readable storage medium.
Background
In the existing computer system, a processor is used as a system control center, and a plurality of hardware devices in the system need to be managed. For example, when a processor normally executes a program in a system, a phenomenon interrupted by an external event, a system call, or an instruction abnormal execution may occur. At this time, the processor protects the program execution site and transfers to processing the abnormal event, and recovers the abnormal execution site after the abnormal event execution is finished, and continues to execute the interrupted processing program.
At present, the protection and recovery of the abnormal site can be realized by running a set software program. Specifically, before the abnormal event starts to be executed, a set stack pushing program is run to push a register file to be protected into an abnormal stack to store relevant information of the interrupted program, and correspondingly, after the abnormal event is executed, the set stack popping program is used to pop the register file pushed into the abnormal stack out of the abnormal stack to recover the relevant information of the interrupted program stored before the abnormal event is executed, so that the processor is ensured to continue to execute the interrupted processing program.
However, the stack pushing program and the stack popping program set in the above method for protecting and recovering the abnormal field use a lot of processor instructions (for example, in the MIPS architecture, if 30 register files need to be protected and recovered, 60 processor instructions are needed at this time), which not only occupies a large storage space, but also causes low execution efficiency and large power consumption due to excessive execution instructions.
In summary, when the existing abnormal field protection and recovery method uses software codes to perform field protection, the software codes occupy a large storage space, which results in low execution efficiency and large power consumption of the processor.
Disclosure of Invention
The application provides an abnormal site recovery method, an abnormal site recovery device and a computer readable storage medium, which are used for solving the problems of low execution efficiency and high power consumption of a processor in the conventional abnormal site recovery method.
The application provides a method for recovering an abnormal site in a first aspect, which comprises the following steps:
obtaining an exception return instruction, wherein the exception return instruction comprises an operation code, and the operation code is used for instructing a processor to execute a last instruction of an exception handling function;
executing the exception return instruction to modify a program counter value and pop information pushed to a target register file of an exception stack off the exception stack and returning to continue executing the interrupted normal processing function.
In an embodiment of the present application, the obtaining an exception return instruction includes:
fetching an instruction in a memory storing the exception handling function;
analyzing the instruction to obtain an operation code in the instruction;
and when the operation code in the instruction is consistent with the preset operation code of the abnormal return instruction, determining that the instruction is the abnormal return instruction.
In another embodiment of the present application, before the obtaining the exception return instruction, the method further includes:
when an abnormal request is obtained, interrupting the normal processing function which is being executed;
and pushing the information in the target register file corresponding to the normal processing function into the exception stack, and forwarding to execute the exception processing function corresponding to the exception request.
In the above embodiments of the present application, a stack maintenance module is disposed in the processor;
the pushing the information in the target register file corresponding to the normal processing function to the exception stack includes:
pushing the information in the target register file corresponding to the normal processing function into the abnormal stack through the stack maintenance module;
said executing said exception return instruction to modify a program counter value and pop information pushed to a target register file of an exception stack off said exception stack and return to continue executing the interrupted normal processing function, comprising:
executing the exception return instruction to modify the value of a program counter and sequentially popping and writing the information pressed into the exception stack into a register of a corresponding number in the target register file through the stack maintenance module;
and returning to continue executing the interrupted normal processing function when all the information pushed into the abnormal stack is popped up.
In the above embodiment of the present application, the stack maintenance module is provided with a register protection domain and an exception stack pointer;
the register protection field is used for indicating the number of the target register files, and the exception stack pointer is used for indicating the position of the target register files.
In yet another embodiment of the present application, the target register file comprises: a general register file and a system control register file;
the general register file is a combination of general registers used for saving data operations in the processor, and the system control register file is a combination of system control registers used for saving processor states in the processor.
A second aspect of the present application provides an abnormal site recovery apparatus, including:
the instruction acquisition module is used for acquiring an exception return instruction, wherein the exception return instruction comprises an operation code, and the operation code is used for indicating the processor to execute the last instruction of an exception handling function;
and the instruction execution module is used for executing the exception return instruction so as to modify the value of a program counter, popping the information pressed into a target register file of the exception stack from the exception stack, and returning to continue executing the interrupted normal processing function.
In an embodiment of the application, the instruction obtaining module is configured to obtain an exception return instruction, and specifically:
the instruction obtaining module is specifically configured to obtain an instruction in a memory storing the exception handling function, analyze the instruction, obtain an operation code in the instruction, and determine that the instruction is the exception return instruction when the operation code in the instruction is consistent with a preset operation code of the exception return instruction.
In another embodiment of the present application, the apparatus further includes: a processing module;
the processing module is configured to, before the instruction obtaining module obtains the exception return instruction, break the normal processing function being executed when obtaining the exception request, push information in the target register file corresponding to the normal processing function to the exception stack, and forward to execute the exception processing function corresponding to the exception request.
In the above embodiments of the present application, a stack maintenance module is disposed in the processor;
the processing module is configured to push information in the target register file corresponding to the normal processing function to the exception stack, specifically:
the processing module is specifically configured to push information in the target register file corresponding to the normal processing function to the exception stack through the stack maintenance module;
the instruction execution module is configured to execute the exception return instruction to modify a program counter value and pop information pushed into a target register file of an exception stack from the exception stack, and return to continue executing the interrupted normal processing function, and specifically:
the instruction execution module is specifically configured to execute the exception return instruction to modify a program counter value, sequentially pop up and write information pushed into the exception stack into a register of a corresponding number in the target register file through the stack maintenance module, and return to continue executing the interrupted normal processing function when all information pushed into the exception stack is popped up.
In the above embodiment of the present application, the stack maintenance module is provided with a register protection domain and an exception stack pointer;
the register protection field is used for indicating the number of the target register files, and the exception stack pointer is used for indicating the position of the target register files.
In yet another embodiment of the present application, the target register file comprises: a general register file and a system control register file;
the general register file is a combination of general registers used for saving data operations in the processor, and the system control register file is a combination of system control registers used for saving processor states in the processor.
A third aspect of the application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the method as described in the first aspect above.
According to the method, the device and the computer-readable storage medium for recovering the exception site provided by the embodiment of the application, the processor acquires the exception return instruction, the exception return instruction comprises the operation code, and the operation code is used for indicating the processor to execute the last instruction of the exception handling function and executing the exception return instruction so as to modify the value of a program counter, pop the information of a target register file pressed into an exception stack from the exception stack and return to continue to execute the interrupted normal handling function. According to the technical scheme, software codes are not needed to recover abnormal fields, the occupied space and power consumption of the software codes are reduced, and the execution efficiency of the processor is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic flowchart of a first embodiment of an abnormal site recovery method according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating instruction execution of a processor in the abnormal field recovery method according to an embodiment of the present disclosure;
fig. 3 is a schematic flow chart of a second embodiment of an abnormal site recovery method according to an embodiment of the present application;
fig. 4 is a schematic flow chart of a third embodiment of an abnormal site recovery method according to an embodiment of the present application;
FIG. 5 is an architectural diagram illustrating normal execution path and exception stack maintenance for a processor according to an embodiment of the present application;
FIG. 6A is a first block diagram illustrating an architecture of an exception maintenance register in the stack maintenance module in the embodiment shown in FIG. 5;
FIG. 6B is a block diagram illustrating a second architecture of an exception maintenance register in the stack maintenance module in the embodiment shown in FIG. 5;
fig. 7 is a schematic structural diagram of a first embodiment of an abnormal field recovery device according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a second embodiment of an abnormal site recovery apparatus according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, when a program is executed normally, a processor is often interrupted by external events, system calls, program instruction exceptions, or the like. Interruptions originating from system calls and program instruction exceptions are referred to as normal exceptions, and interruptions originating from external events are referred to as interrupts. Once an exception is generated, the processor must most of the time respond, breaking the normal program flow, and jumping to the specified entry address to fetch and execute the exception handler. After the execution of the exception handler is completed, the normal program flow needs to be skipped back to continue the execution.
The key to the exception handling mechanism in the processor is that the normal program flow can be interrupted and restored after the exception event handling is finished and executed correctly, which also needs to be protected in the exception field. The exception field protection means that before entering an exception event and executing a first instruction of an exception handler, necessary internal information such as certain register files of the processor is saved, and when the exception handler is executed and returns to a normal program flow, the information of the certain register files of the processor which is saved before is restored.
Therefore, when an exception event occurs and enters the exception handler, if the exception field is not completely saved, the processor cannot execute the exception handler, and correspondingly, when the exception handler returns, if the exception field is not completely restored, the processor cannot execute the normal program.
At present, two methods are mainly adopted in the prior art to realize the protection and recovery of an abnormal field, namely, the field protection is executed by software and a plurality of sets of register files are arranged in a processor core.
The software execution field protection means that before executing the exception handling program, the register file to be protected is pushed into the exception stack by the set software program, and at the end of the exception handling program, the register file pushed into the exception stack is popped out of the exception stack by the set software program. However, this approach has more problems: too many processor instructions are used for pressing and popping the software, too much code storage space is occupied, too many processor instructions cause low execution efficiency, dozens of beats of processor cycles are needed for completing the operation, the exception processing time of the processor core is greatly increased, and the power consumption is high.
The method for setting a plurality of sets of register files in a processor core means that another set of register file is used each time when an exception handling program is entered, at the moment, an exception field does not need to be protected, and the method has extremely high efficiency for single exception handling. For example, when there are 30 general registers in the MIPS architecture, 2 sets of 30 general registers may be set, and a first set of general register file is used when normal program flow is executed, and another set of general register file is used when an exception request is received to enter an exception handler. However, this method also has the corresponding problems: for example, this approach does not work with embedded exceptions (such as interrupts) and thus does not reduce the average exception handling time, and setting multiple register files will use too much hardware resources, resulting in higher processor core area, power consumption, and cost.
It should be noted that the above-mentioned inline exception refers to that when the processor core is executing an exception handler, another exception request is received, and so on, the inline exception hierarchy can be theoretically infinitely deep. Obviously, embedded exceptions also need to be protected in the field each time, and after the use of a plurality of sets of register files is completed, software is needed to be protected in the field, and at the moment, the problem that the software executes the field protection is also generated.
Since the execution time of the exception field protection is a part of the entire exception handling time of the processor, the exception field protection mechanism in the processor greatly affects the time T for the processor to averagely handle an exception eventintAlso, the exception handling bandwidth (1/T) of the processor is affectedint) And exception handling bandwidth reflects the exception handling capability of the processor.
However, many application scenarios place high demands on exception handling bandwidth. For example, in a real-time operating system, a processor is required to respond and process quickly when receiving an exception request from an external device, so as to control a production process or respond quickly to a processing system at a prescribed time. Since timeliness and reliability are the main characteristics of the real-time operating system, the lower exception handling bandwidth can greatly reduce timeliness and reliability of the real-time operating system.
In addition, in the embedded microcontroller, because the controllability of the processor is more emphasized, the processor core can receive a plurality of different types of exception events and is required to be capable of performing quick response and processing, so that the requirement on exception processing bandwidth is high, and the exception processing bandwidth is reduced due to overlong exception processing time.
The application provides an abnormal site recovery method, an abnormal site recovery device and a computer readable storage medium, aiming at the problems of low execution efficiency and high power consumption of a processor in the abnormal site protection and recovery method in the prior art. In addition, the method can well support embedded exception, reduce average exception handling time and improve exception handling bandwidth of the processor core. The technical solution of the present application will be described in detail below with reference to specific examples.
It should be noted that the following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
Fig. 1 is a schematic flow chart of a first embodiment of an abnormal site recovery method provided in the embodiment of the present application. Fig. 2 is a schematic diagram illustrating instruction execution of a processor in the abnormal field recovery method according to the embodiment of the present application. The embodiment of the present application will be described with reference to fig. 1 and fig. 2, mainly using a processor as an execution subject. As shown in fig. 1, the abnormal site recovery method provided in the embodiment of the present application may include the following steps:
and step 11, acquiring an exception return instruction, wherein the exception return instruction comprises an operation code, and the operation code is used for instructing the processor to execute the last instruction of the exception handling function.
Since the instructions executed by the processor are stored in the memory, the processor will in turn execute instructions fetched from the memory. Therefore, in the embodiment of the present application, the exception handling function corresponding to the exception request received by the processor stores the corresponding instruction in the memory, and therefore, when executing the exception handling function, the processor sequentially fetches the instruction from the memory and sequentially executes the instruction.
In the embodiment of the present application, in order to make the processor know in time when the execution of the exception handling function is finished, an instruction for identifying the end of the exception handling function is added at the end of the exception handling function, which is defined as an exception Return instruction (INT _ RET). For example, as shown in fig. 2, since the start instruction of the exception handling function is INT _ BEG, the end instruction of the exception handling function (i.e., the exception return instruction) is INT _ RET, and INT _ BEG and the exception return instruction INT _ RET are part of the exception handling function, the exception return instruction can be obtained when the processor executes the exception handling function, that is, the exception return instruction can be obtained when the processor executes to the end of the exception handling function.
Optionally, the exception return instruction in this application includes an operation code, and when the processor acquires the exception return instruction, the operation code in the exception return instruction may be obtained through parsing, and it is determined that the operation code is the same as the operation code of the last instruction of the set exception handling function through analyzing the operation code, so that the operation code may be used to instruct the processor to execute the last instruction of the exception handling function.
And step 12, executing the exception return instruction to modify the value of the program counter, popping the information of the target register file pressed into the exception stack from the exception stack, and returning to continue executing the interrupted normal processing function.
In the embodiment of the present application, when the processor executes the above exception return instruction, the processor is triggered to simultaneously execute the following two operations.
Specifically, when the processor executes the exception return instruction, on one hand, the processor is triggered to modify the program counter value, modify the program counter value into a PC value of a target valid instruction, and clear an exception identification field on a system control register that stores a processor state in the processor, where the PC value of the target valid instruction is used to indicate an instruction address where an exception request corresponds to an exception occurrence. For example, in fig. 2, the instruction at which the exception occurs is instruction i, i.e., firstly, the program counter value in the processor is modified to point to the first instruction of the exception handling function, and secondly, when the exception returns after the execution of the exception handling function is completed, the program counter value in the processor is modified to point to instruction i of the normal program. It should be noted that the exception handling function may modify the value in the system control register that previously held the value of the PC instruction at which the exception occurred, so that the program counter may not point to instruction i of the normal program when the exception returns.
Therefore, when the processor executes the exception return instruction, it indicates that the last instruction executed to the exception handling function, that is, the exception event corresponding to the exception request is executed completely, so that the processor may be triggered to modify the PC value in the processor so as to point to the instruction address (for example, instruction i in fig. 2) where the exception corresponding to the exception request occurs, return to the normal handling function, and enter the execution mode of the normal handling function.
When the processor executes the exception return instruction, on the other hand, the processor is triggered to pop the information which is pushed to the target register file of the exception stack before the exception request response to the exception stack so as to recover the exception field.
It is worth to be noted that the step of triggering the processor to modify the PC value occupies a normal execution path of the processor, and after the step is completed, the processor can continue to fetch the instruction corresponding to the normal processing function from the program counter for execution; and the step of triggering the processor to pop the information pressed into the target register file of the exception stack from the exception stack occupies a background exception stack maintenance path, and the path does not influence the normal execution path of the processor and can run in the background. Thus, utilizing an exception return instruction will reduce the average exception handling time. In addition, the method can also well support embedded exception, the exception handling bandwidth of the processor core is improved, and the method only consumes less hardware resources and has low power consumption.
According to the method for recovering the abnormal site, the abnormal return instruction is obtained and comprises the operation code, the operation code is used for indicating the processor to execute the last instruction of the abnormal processing function, and then the abnormal return instruction is executed, so that the processor can modify the value of a program counter and return to continuously execute the interrupted normal processing function after the information pressed into a target register file of an abnormal stack is popped from the abnormal stack. According to the technical scheme, the exception stack information is popped by the exception return instruction, the software code is not required to recover the exception field, the space occupied by the software code and the power consumption are reduced, and the execution efficiency of the processor is improved.
As an example, fig. 3 is a schematic flow chart of a second embodiment of an abnormal scene restoration method provided in the embodiment of the present application. The present embodiment is a detailed description of the above step 11 on the basis of the above embodiment. As shown in fig. 3, in the embodiment of the present application, the obtaining of the exception return instruction may include the following steps:
Specifically, in the embodiment of the present application, when the processor executes the exception handling function, the processor sequentially fetches instructions from the memory in which the exception handling function is stored, and sequentially executes the instructions in sequence until all the instructions corresponding to the exception handling function are fetched and executed.
And 32, analyzing the instruction to acquire the operation code in the instruction.
Optionally, each instruction executed by the processor includes an operation code, and the operation code is used for indicating a position where the processor executes the instruction or a function of the corresponding instruction. In the embodiment of the application, the processor analyzes the instruction obtained from the memory storing the exception handling function to obtain the operation code in the instruction. Because the operation codes included in each instruction are different, the processor can determine the position, specific meaning or function of the corresponding instruction by analyzing each operation code.
And step 33, when the operation code in the instruction is consistent with the operation code of the preset abnormal return instruction, determining that the instruction is the abnormal return instruction.
Optionally, the designer defines the instruction by setting different operation codes, so that when the processor acquires an operation code in the instruction, the processor may analyze the operation code to determine what the acquired instruction is. If the operation code in the instruction is judged to be the same as the operation code of the preset exception return instruction in the processor, the instruction can be determined to be an exception handling instruction, namely the processor is considered to execute the last instruction of the exception handling function, and the exception handling function is determined to be completed. Therefore, when the processor executes the exception return instruction subsequently, the processor can be triggered to modify the program counter value to point to the normal processing function at the exception occurrence position, and meanwhile, the stack popping of the exception stack is automatically carried out in the background so as to recover the exception field.
According to the method for recovering the abnormal site, the instruction is obtained from the memory for storing the abnormal processing function, the instruction is analyzed, the operation code in the instruction can be obtained, and the instruction can be determined to be the abnormal return instruction when the operation code in the instruction is consistent with the operation code of the preset abnormal return instruction. According to the technical scheme, the exception return instruction is arranged at the tail end of the exception handling function, so that when the processor executes the exception return instruction, the exception handling function is determined to be completed, the processor can be triggered to modify the value of the program counter and perform stack popping processing on information pressed into a target register file of an exception stack, and a foundation is laid for shortening the average exception handling time of the processor.
Optionally, on the basis of the foregoing embodiment, fig. 4 is a schematic flow chart of a third embodiment of an abnormal site recovery method provided in the embodiment of the present application. As shown in fig. 4, in the embodiment of the present application, before step 11, that is, before an exception return instruction is obtained, the method for recovering an exception field according to the embodiment of the present application further includes the following steps:
and step 41, interrupting the normal processing function in execution when the exception request is acquired.
If the processor is interrupted by an exception source such as an external event, a system call, or a program instruction exception during the process of executing the normal processing function, that is, the exception source issues an exception request, the processor may obtain the exception request. Furthermore, the processor, upon acquiring the exception request, suspends execution of the executing normal processing function, i.e., interrupts execution of the normal processing function.
And 42, pressing the information in the target register file corresponding to the normal processing function into an exception stack, and forwarding to the exception processing function corresponding to the execution exception request.
In order to ensure that the processor can return to continue executing the interrupted normal processing function after executing the exception processing function corresponding to the exception request, before the processor responds to the exception request and executes the exception processing function corresponding to the exception request, not only the exception field needs to be protected, that is, information in a target register file storing information corresponding to the normal processing function in the processor needs to be saved, but also a target valid instruction at the exception occurrence place needs to be determined, a program counter value corresponding to the target valid instruction is saved in a system control register of the processor, and an exception identification field is arranged on the system control register storing the processor state in the processor, the exception identification field is used for indicating that the processor is in an exception mode, and in addition, a Program Counter (PC) value in the processor needs to be modified, the program counter is directed to a first instruction of the exception handling function to which the exception request corresponds to divert the processor to execute the exception handling function.
In the embodiment of the application, in order to solve the problems of low execution efficiency and high power consumption of a processor in software field protection in the prior art, the function of the processor is expanded, and the processor is used for performing stack pushing processing on information in a target register file corresponding to a normal processing function.
Specifically, referring to fig. 2, when the processor acquires the exception request, the processor pushes the information in the target register file corresponding to the normal processing function into the exception stack for storage, and then modifies the program counter value in the processor to switch to executing the exception processing function corresponding to the exception request.
According to the abnormal site recovery method provided by the embodiment of the application, before the abnormal return instruction is obtained and when the abnormal request is obtained, the normal processing function which is being executed is interrupted, the information in the target register file corresponding to the normal processing function is pressed into the abnormal stack, and then the abnormal processing function corresponding to the abnormal request is executed, so that a foundation is laid for realizing the stack pressing processing of the information in the target register file by executing the abnormal return instruction subsequently.
As an example, in the foregoing embodiment of the present application, a stack maintenance module is disposed in the processor, and when the processor obtains an exception request, the stack maintenance module may be used to perform stack pushing and stack popping processing on information in a target register corresponding to a normal processing function.
Specifically, in step 42, the information in the target register file corresponding to the normal processing function is pushed to the exception stack, which may be implemented by the following steps:
and pushing the information in the target register file corresponding to the normal processing function into an abnormal stack through the stack maintenance module.
Accordingly, the step 12 of executing the exception return instruction to modify the program counter value and pop the information pushed to the target register file of the exception stack from the exception stack, and returning to continue executing the interrupted normal processing function can be implemented by the following steps:
and executing the exception return instruction to modify the value of the program counter, sequentially popping the information pressed into the exception stack through the stack maintenance module, writing the information into a register of a corresponding number in a target register file, and returning to continuously execute the interrupted normal processing function when all the information pressed into the exception stack is popped.
Specifically, in the embodiment of the present application, when the processor executes the exception return instruction, the exception stack maintenance of the stack maintenance module is actually executed in the background. And writing the popped information into a corresponding number register of the general register file or the system control register once each time the processor pops the stack, correspondingly, subtracting one from the abnormal stack pointer, and popping the stack next time until all the information of the target register saved before is popped up.
In the embodiment of the application, since the exception stack maintenance of the stack maintenance module is performed in the background, the processor is considered to be executing a section of program at this time. If the processor is executing an instruction but the source operands required by the instruction have not been popped, the processor pipeline may stall until the required source operands are popped and the instruction may not continue execution, a process that is hardware-assured and transparent to software.
The following describes a specific implementation of a stack maintenance module in a processor by using a specific example.
Optionally, fig. 5 is an architecture diagram illustrating maintenance of a normal execution path and an exception stack of a processor in the embodiment of the present application. FIG. 6A is a first block diagram illustrating an architecture of an exception maintenance register in the stack maintenance module in the embodiment shown in FIG. 5. Fig. 6B is a schematic diagram illustrating an architecture of an exception maintenance register in the stack maintenance module in the embodiment shown in fig. 5. Referring to the analysis of the embodiment shown in fig. 1 and 4 in conjunction with fig. 5, a stack maintenance module is disposed in the processor. As an implementation example, a register protection field and an exception stack pointer are arranged in the stack maintenance module, the register protection field is used for indicating the number of the target register files, and the exception stack pointer is used for indicating the position of the target register files.
Optionally, in an embodiment of the application, the target register file includes: a general register file and a system control register file.
The general register file is a combination of general registers used for saving data operation in the processor, and the system control register file is a combination of system control registers used for saving processor state in the processor.
Specifically, the general purpose register is a register in the processor, which is involved in saving the operation data, and the source operation register and the destination operation register of the general instruction belong to the general purpose register. A system control register file is a register used to save the state of a processor, e.g., regardless of whether the processor is in user or kernel mode, there is a field indication of the corresponding system control register. When abnormal field protection is carried out, most or even all general registers need to be protected, and a few or even zero system control registers need to be protected, wherein the protection is determined according to the architecture of a processor.
For example, as shown in FIG. 5, the stack maintenance module includes an exception maintenance register (INT _ SP) whose composition is shown in FIG. 6A or FIG. 6B. FIG. 6A illustrates the composition of an exception maintenance register in a 32-bit processor, and FIG. 6B illustrates the composition of an exception maintenance register in a 64-bit processor. As shown in fig. 6A and 6B, the high order bit (Interrupt _ SP, i.e., I _ SP) of the exception maintenance register in the processor is the high order bit of an exception stack pointer indicating the location of the target register file, and the low order bit of the exception maintenance register is complemented by 0, defined as a register protection field (Protect _ Num) indicating the number of target register files.
For example, referring to fig. 6A, in the exception maintenance register of the 32-bit processor, the register protection field occupies 2 lower bits, and at this time, the exception stack pointer is { I _ SP, 2 'b 00}, where 2' b00 indicates the position of the 2 lower bits is complemented by 0 to indicate the number of registers to be protected in the exception field.
Optionally, table 1 is a description of the register protection domain of the exception maintenance register in the 32-bit processor. As shown in table 1, the register protection domain is 0x0, which indicates that the stack maintenance module does not maintain any register, which is equivalent to not starting an exception stack maintenance mechanism; the register protection domain is 0x1, and represents that the stack maintenance module maintains the first 8 general registers in the register file; the register protection field is 0x2, which indicates that the stack maintenance module maintains the first 16 general registers in the register file; the register protection field is 0x3, indicating that the stack maintenance module maintains the first 32 general purpose registers in the register file.
TABLE 1
| Register protection field | Description of the invention |
| 0x0 | Maintenance mechanism for not maintaining any register and equivalently not starting exception stack |
| 0x1 | Maintaining the first 8 general purpose registers in a register file |
| 0x2 | Maintaining the first 16 general purpose registers in a register file |
| 0x3 | Maintaining the first 32 general purpose registers in a register file |
Similarly, referring to fig. 6B, in the exception maintenance register of the 64-bit processor, the register protection field occupies 3 lower bits, and at this time, the exception stack pointer is { I _ SP, 3 'B000 }, where 3' B000 indicates that the position of the lower 3 bits is complemented by 0 to indicate the number of registers that need to be protected in the exception field.
It should be noted that, in the embodiment of the present application, the number and the location of the system control registers to be maintained depend on the architecture of the processor, and the number and the location of the system control registers to be maintained by the stack maintenance module are not described herein again.
Referring to fig. 5, the processor includes two paths, one is a normal execution path, which is mainly used for executing a normal processing function, and the other is an exception stack maintenance path, which is mainly used for recovering an exception field when an exception occurs. The architecture diagram shown in fig. 5 is a general architecture diagram of a processor for handling exception events, and the comparison is generalized.
Specifically, as shown in fig. 5, when the processor is normally executed, the processor first obtains an instruction, decodes the obtained instruction by using the decoding unit, and then directly executes the instruction by using the execution unit, for example, the operation unit participates in the operation, the physical register file stores data participating in the operation or stores the state of the processor, and the memory access operation is implemented between the memory access unit and the memory.
Optionally, the architecture diagram shown in fig. 5 further includes a renaming unit, a transmitting unit, a reordering queue, a memory access correlation unit, and the like. I.e. when the processor is in an out-of-order execution architecture, a rename unit, a launch unit, a reorder queue, etc. are also included. The renaming unit is used for solving the problem of inverse dependence, and renaming processing is required when out-of-order execution is carried out. The renaming process corresponds a register number (referred to as a "logical register") described in a program to a physical register number. The logical register to which each instruction writes the result must be allocated to a free physical register. The issue unit may issue a plurality of instructions to the execution unit in one cycle. The reordering queue is used for adjusting the order of the instructions to be executed by the processor, so as to achieve the purpose of out-of-order execution. The memory access correlation unit may write the result of the search instruction into the corresponding memory.
It should be noted that the rename unit, the issue unit, and the reorder queue described above are not required for a processor to execute out-of-order.
Optionally, as shown in fig. 5, after the processor obtains the exception request, the processor also obtains the instruction from the memory and decodes the instruction by using the decoding unit, but after the processor pushes the information of the target register file in the physical register file by using the stack maintenance module, the exception handling function is executed, and finally, after the exception handling function is executed, the stack maintenance module is used to pop the information of the target register file pushed into the exception stack.
Referring to fig. 5, the exception stack is located in the memory, so that the access interface of the processor is multiplexed when the exception stack maintenance module accesses the exception stack, and therefore, no additional access resource is required to be added, and the power consumption is low.
Optionally, the exception maintaining register (INT _ SP) in the stack maintaining module may be implemented by using a system control register, or may actually be implemented by using a general register, which may be set according to an actual situation, and the embodiment of the present application does not limit the present application. Optionally, in the embodiment of the present application, the exception stack pointer may be set in multiple ways, and in the set exception maintenance register, the set register protection field enables the processor to select which registers are protected, the register protection field may have multiple allocation schemes, or may not have the field, and does not give software option (for example, default protection of all general purpose registers and necessary system control registers, etc.).
The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.
Fig. 7 is a schematic structural diagram of a first embodiment of an abnormal field recovery device according to an embodiment of the present application. As shown in fig. 7, the abnormal site restoration apparatus of the present embodiment may include: an instruction fetch module 71 and an instruction execution module 72.
The instruction fetching module 71 is configured to fetch an exception return instruction, where the exception return instruction includes an operation code, and the operation code is used to instruct the processor to execute a last instruction to the exception handling function.
The instruction execution module 72 is configured to execute an exception return instruction to modify the program counter value and pop information pushed to the target register file of the exception stack from the exception stack, and return to continue execution of the interrupted normal processing function.
The abnormal site recovery apparatus in this embodiment may be used to execute the implementation scheme of the method embodiment shown in fig. 1, and the specific implementation manner and the technical effect are similar and will not be described here again.
Optionally, in the above embodiment, the instruction obtaining module 71 is configured to obtain an exception return instruction, and specifically:
the instruction obtaining module 71 is specifically configured to obtain an instruction in a memory storing the exception handling function, analyze the instruction, obtain an operation code in the instruction, and determine that the instruction is the exception return instruction when the operation code in the instruction is consistent with a preset operation code of the exception return instruction.
Optionally, on the basis of the foregoing embodiment, fig. 8 is a schematic structural diagram of a second embodiment of the abnormal site recovery device provided in the embodiment of the present application. As shown in fig. 8, the abnormal site restoration apparatus according to the present embodiment may further include: a processing module 81.
The processing module 81 is configured to, before the instruction obtaining module 71 obtains the exception return instruction, when an exception request is obtained, break the normal processing function being executed, push information in the target register file corresponding to the normal processing function to the exception stack, and forward to execute the exception processing function corresponding to the exception request.
Further, on the basis of the above embodiment, a stack maintenance module is disposed in the processor.
The processing module 81 is configured to push information in the target register file corresponding to the normal processing function to the exception stack, and specifically includes:
the processing module 81 is specifically configured to push the information in the target register file corresponding to the normal processing function to the exception stack through the stack maintenance module.
Correspondingly, the instruction execution module 72 is configured to execute the exception return instruction, so as to modify the program counter value, pop the information pushed into the target register file of the exception stack from the exception stack, and return to continue executing the interrupted normal processing function, specifically:
the instruction execution module 72 is specifically configured to execute the exception return instruction, modify a program counter value, sequentially pop up and write information pushed into the exception stack into a register of a corresponding number in the target register file through the stack maintenance module, and when all information pushed into the exception stack is popped up, return to continue executing the interrupted normal processing function.
In the above embodiment of the present application, the stack maintenance module is provided with a register protection domain and an exception stack pointer.
Wherein the register protection field is used to indicate the number of the target register files, and the exception stack pointer is used to indicate the location of the target register files.
As an example, in the above embodiment, the target register file includes: a general register file and a system control register file.
The general register file is a combination of general registers used for saving data operation in the processor, and the system control register file is a combination of system control registers used for saving processor state in the processor.
The abnormal field recovery device provided by the embodiment of the application executes the stacking and popping of the information in the target register file corresponding to the normal processing function by using the stack maintenance module, and triggers by using the abnormal return instruction at the end of the abnormal processing function when popping the stack, so that the field protection is not needed by software codes, the code space and the power consumption are reduced, and the problems of excessive code redundancy or hardware resource consumption, large power consumption and low execution efficiency in the abnormal field protection in the prior art are solved.
The embodiment of the application provides a computer device, which comprises a processor, a memory and a computer program which is stored on the memory and can run on the processor, wherein when the processor executes the program, the technical scheme of the embodiment of the abnormal field recovery method is realized.
The embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, where the program, when executed by a processor, implements the technical solution of the above-mentioned abnormal field recovery method embodiment.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (13)
1. An abnormal scene restoration method, comprising:
obtaining an exception return instruction, wherein the exception return instruction comprises an operation code, and the operation code is used for instructing a processor to execute a last instruction of an exception handling function; the processor comprises a normal execution path and an abnormal stack maintenance path; the exception return instruction is used for identifying the end of the exception handling function so as to control the following steps of executing the exception field recovery in the normal execution path and the exception stack maintenance path;
executing the exception return instruction to modify the value of a program counter and pop information pushed into a target register file of an exception stack from the exception stack, and returning to continue executing the interrupted normal processing function;
said step of modifying a program counter value occupies a normal execution path of said processor; meanwhile, the step of popping the information of the target register file pressed into the abnormal stack from the abnormal stack occupies a background abnormal stack maintenance path; the step of modifying the program counter value executed in the normal execution path is executed in parallel with the step of popping the information pushed to the target register file of the exception stack from the exception stack executed in the exception stack maintenance path.
2. The method of claim 1, wherein said fetching an exception return instruction comprises:
fetching an instruction in a memory storing the exception handling function;
analyzing the instruction to obtain an operation code in the instruction;
and when the operation code in the instruction is consistent with the preset operation code of the abnormal return instruction, determining that the instruction is the abnormal return instruction.
3. The method of claim 1 or 2, prior to said fetching exception return instructions, further comprising:
when an abnormal request is obtained, interrupting the normal processing function which is being executed;
and pushing the information in the target register file corresponding to the normal processing function into the exception stack, and forwarding to execute the exception processing function corresponding to the exception request.
4. The method of claim 3, wherein a stack maintenance module is disposed in the processor;
the pushing the information in the target register file corresponding to the normal processing function to the exception stack includes:
pushing the information in the target register file corresponding to the normal processing function into the abnormal stack through the stack maintenance module;
said executing said exception return instruction to modify a program counter value and pop information pushed to a target register file of an exception stack off said exception stack and return to continue executing the interrupted normal processing function, comprising:
executing the exception return instruction to modify the value of a program counter and sequentially popping and writing the information pressed into the exception stack into a register of a corresponding number in the target register file through the stack maintenance module;
and returning to continue executing the interrupted normal processing function when all the information pushed into the abnormal stack is popped up.
5. The method of claim 4, wherein a register protection field and an exception stack pointer are provided in the stack maintenance module;
the register protection field is used for indicating the number of the target register files, and the exception stack pointer is used for indicating the position of the target register files.
6. The method of claim 1 or 2, wherein the target register file comprises: a general register file and a system control register file;
the general register file is a combination of general registers used for saving data operations in the processor, and the system control register file is a combination of system control registers used for saving processor states in the processor.
7. An abnormal field restoration device, comprising:
the instruction acquisition module is used for acquiring an exception return instruction, wherein the exception return instruction comprises an operation code, and the operation code is used for indicating the processor to execute the last instruction of an exception handling function; the processor comprises a normal execution path and an abnormal stack maintenance path; the exception return instruction is used for identifying the end of the exception handling function so as to control the following steps of executing the exception field recovery in the normal execution path and the exception stack maintenance path;
the instruction execution module is used for executing the exception return instruction so as to modify the value of a program counter, popping information of a target register file pressed into an exception stack from the exception stack, and returning to continue to execute the interrupted normal processing function;
wherein the step of modifying the program counter value occupies a normal execution path of the processor; meanwhile, the step of popping the information of the target register file pressed into the abnormal stack from the abnormal stack occupies a background abnormal stack maintenance path; the step of modifying the program counter value executed in the normal execution path is executed in parallel with the step of popping the information pushed to the target register file of the exception stack from the exception stack executed in the exception stack maintenance path.
8. The apparatus according to claim 7, wherein the instruction fetching module is configured to fetch an exception return instruction, specifically:
the instruction obtaining module is specifically configured to obtain an instruction in a memory storing the exception handling function, analyze the instruction, obtain an operation code in the instruction, and determine that the instruction is the exception return instruction when the operation code in the instruction is consistent with a preset operation code of the exception return instruction.
9. The apparatus of claim 7 or 8, further comprising: a processing module;
the processing module is configured to, before the instruction obtaining module obtains the exception return instruction, break the normal processing function being executed when obtaining the exception request, push information in the target register file corresponding to the normal processing function to the exception stack, and forward to execute the exception processing function corresponding to the exception request.
10. The apparatus of claim 9, wherein a stack maintenance module is disposed in the processor;
the processing module is configured to push information in the target register file corresponding to the normal processing function to the exception stack, specifically:
the processing module is specifically configured to push information in the target register file corresponding to the normal processing function to the exception stack through the stack maintenance module;
the instruction execution module is configured to execute the exception return instruction to modify a program counter value and pop information pushed into a target register file of an exception stack from the exception stack, and return to continue executing the interrupted normal processing function, and specifically:
the instruction execution module is specifically configured to execute the exception return instruction to modify a program counter value, sequentially pop up and write information pushed into the exception stack into a register of a corresponding number in the target register file through the stack maintenance module, and return to continue executing the interrupted normal processing function when all information pushed into the exception stack is popped up.
11. The apparatus of claim 10, wherein a register protection field and an exception stack pointer are disposed in the stack maintenance module;
the register protection field is used for indicating the number of the target register files, and the exception stack pointer is used for indicating the position of the target register files.
12. The apparatus of claim 7 or 8, wherein the target register file comprises: a general register file and a system control register file;
the general register file is a combination of general registers used for saving data operations in the processor, and the system control register file is a combination of system control registers used for saving processor states in the processor.
13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of the claims 1-6.
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| US20020144099A1 (en) * | 2001-01-25 | 2002-10-03 | Muro Manuel R. | Hardware architecture for fast servicing of processor interrupts |
| CN1208721C (en) * | 2003-09-19 | 2005-06-29 | 清华大学 | Graded task switching method based on PowerPC processor structure |
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