CN108037951B - Method and device for rapidly switching interrupt of DTP (delay tolerant protocol) processor - Google Patents
Method and device for rapidly switching interrupt of DTP (delay tolerant protocol) processor Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
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- G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/327—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for interrupts
Abstract
The invention discloses a method and a device for rapidly switching interruption of a DTP processor, wherein the method comprises the following steps: receiving an interrupt signal, wherein the interrupt signal comprises that the DTP processor is switched from a user mode to an IRQ general interrupt mode, or is switched from the user mode to an SWI soft interrupt mode, or is switched from the user mode to a WATCH monitoring point interrupt mode; according to the interrupt signal, the numerical value in the CPSR register in the user mode is respectively copied to the SPSR register in the IRQ general interrupt mode, the SPSR register in the SWI soft interrupt mode or the SPSR register in the WATCH monitoring point interrupt mode, and the switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debugging mode is completed. The invention solves the problem of complex interrupt switching judgment conditions of the traditional multi-core processor and is beneficial to improving the processing efficiency of the RISC processor.
Description
Technical Field
The invention relates to a method and a device for rapidly switching interrupt of a DTP processor.
Background
RISC (reduced instruction set computer) and CISC (complex instruction set computer) are two architectures for current CPUs. They differ in different CPU design concepts and methods.
Early CPUs were all CISC architectures designed to perform the required computational tasks with a minimum of machine language instructions. For example, for multiplication, on a CPU in a CISC architecture, you may need such an instruction: MUL ADDRA, ADDRB may multiply the numbers in ADDRA and ADDRB and store the result in ADDRA. The operations of reading the data in ADDRA, ADDRB into a register, multiplying and writing the result back to memory are all implemented depending on the logic designed in the CPU. Such an architecture would increase the complexity of the CPU architecture and the requirements on the CPU process, but would be advantageous for compiler development. For example, a ═ b in the C program can be directly compiled into a multiply instruction. Today only Intel and its compatible CPUs are still using CISC architecture.
RISC architectures require software to specify the various operational steps. If the above example is to be implemented on a RISC architecture, the operations of reading the data in ADDRA, ADDRB into registers, multiplying and writing the result back to memory must be implemented by software, such as: MOV a, ADDRA; MOV B, ADDRB; MUL A, B; STR ADDRA, a. This architecture can reduce the complexity of the CPU and allow a more powerful CPU to be produced at the same process level, but with higher requirements on the compiler design.
At present, with the continuous improvement of the performance and the processing speed of a multimedia chip by people, in order to better adapt to the real-time throughput processing requirement of embedded multimedia, the RISC processor of a reduced instruction set computer is rapidly popularized and rapidly developed, the development of the RISC technology is gradually mature and perfect, and the application of the RISC processor in the market is very much. However, there are few methods for designing RISC interrupt fast switching.
The patent application number "CN 201611027899.1" Chengdu Haishawa science and technology Limited liability company invents a reconfigurable signal processor ASIC architecture and a reconfiguration method thereof, the reconfigurable signal processor ASIC architecture accesses the working state register through a RISC CPU through a bus and is used for confirming the working state of the current RISC instruction analyzer, when the working state register is in an idle state, the RISC CPU sends a configuration instruction to the RISC instruction analyzer, and corresponding configuration information is stored in the configuration register after the instruction is analyzed. This patent only gives a method of controlling the interrupt, but no solution to interrupt fast transitions.
The invention discloses a method and a device for distributing interrupts in a multi-core processor system, which are invented by Qingdao Haixin Mobile communication technology, Inc., with the patent application number of CN201610395264.0, aiming at interrupt requests and distribution interrupts in the multi-core processor, the interrupt distribution flow under the environment of the multi-core processor is optimized, and the interrupt processing efficiency of the multi-core processor is improved. Although the judgment method and the switching process of the interrupt switching are given, the interrupt switching method in the single-core processor environment is not given only for the multi-core processor, and the judgment of the interrupt switching process is complex, so that the method is not suitable for the common situation.
In summary, the prior art lacks an effective solution to the problem of how to quickly switch interrupts in a RISC processor.
Disclosure of Invention
Aiming at the defects in the prior art and solving the problem of how to quickly switch the interrupt in the RISC processor in the prior art, the invention provides a method and a device for quickly switching the interrupt of a DTP processor.
The first purpose of the invention is to provide an interrupt fast switching method of a DTP processor.
In order to achieve the purpose, the invention adopts the following technical scheme:
an interrupt fast switching method of a DTP processor comprises the following steps:
receiving an interrupt signal, wherein the interrupt signal comprises that the DTP processor is switched from a user mode to an IRQ general interrupt mode, or is switched from the user mode to an SWI soft interrupt mode, or is switched from the user mode to a WATCH monitoring point interrupt mode;
according to the interrupt signal, the numerical value in the CPSR register in the user mode is respectively copied to the SPSR register in the IRQ general interrupt mode, the SPSR register in the SWI soft interrupt mode or the SPSR register in the WATCH monitoring point interrupt mode, and the switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debugging mode is completed.
As a further preferred scheme, the CPSR register or the SPSR register has flag bits of a current DTP processor mode, where the flag bits include four modes 00, 01, 10, and 11, which respectively correspond to a user mode, a WATCH monitor point interrupt mode, an IRQ general interrupt mode, and an SWI soft interrupt mode.
As a further preferable scheme, the method further comprises: after receiving the interrupt signal, judging an interrupt response condition in the interrupt signal, and if the interrupt response condition meets an IRQ general interrupt response condition, switching from a user mode to an IRQ general interrupt mode; if the SWI soft interrupt response condition is met, switching from the user mode to the SWI soft interrupt mode; if the interrupt response condition of the WATCH monitoring point is met, switching from the user mode to the interrupt mode of the WATCH monitoring point; otherwise, the program continues to execute normally;
the IRQ general interrupt response condition is that an interrupt is enabled and an IRQ pin is available; the SWI soft interrupt response condition is that an SWI instruction is executed; the WATCH monitoring point interrupt response condition is that a monitoring point is enabled and a special monitoring point is triggered.
As a further preferable scheme, in the user mode, the SPSR register of the DTP processor is inaccessible, and the return value of the SPSR register is set to 0.
As a further preferred scheme, when switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debug mode, a stack pointer, a link register, a shift register or an SPSR register in the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH checkpoint interrupt mode is used.
As a further preferred scheme, the specific step of switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode, or the walk debug mode includes:
inhibiting the transmission of a subsequent command signal according to the interrupt signal;
respectively copying the numerical value in the CPSR register in the user mode to the SPSR register in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode, and storing breakpoint addresses;
identifying an interrupt source of an interrupt signal to obtain a stroke interrupt vector address;
storing the content of each register to be used in an interrupt service program in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode;
opening the interrupt so that the interrupts can be nested;
and executing substantive processing of the interrupt service program in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode.
As a further preferred scheme, the method further includes switching from an IRQ general interrupt mode, a SWI soft interrupt mode, or a WATCH debug mode to a user mode, and after performing substantial processing of the interrupt service program in the IRQ general interrupt mode, the SWI soft interrupt mode, or the WATCH monitor point interrupt mode, the method includes:
turning off interruption to ensure that the field recovery process is not interrupted by the interruption signal any more;
restoring the register content used in the interrupt service program in the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode, and restoring the hardware to store the site in the user mode;
the DTP processor stores the contents in the SPSR register under the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode into the CPSR register under the user mode again, completes the switching from the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debugging mode to the user mode, and returns the breakpoint of the interrupted program to continue executing.
As a further preferred solution, the DTP processor further comprises a prefetch buffer with a depth of four instructions for branch prediction.
It is a second object of the present invention to provide a computer-readable storage medium.
In order to achieve the purpose, the invention adopts the following technical scheme:
a computer readable storage medium storing a plurality of instructions, the instructions being loaded by a processor and performing the process of:
receiving an interrupt signal, wherein the interrupt signal comprises that the DTP processor is switched from a user mode to an IRQ general interrupt mode, or is switched from the user mode to an SWI soft interrupt mode, or is switched from the user mode to a WATCH monitoring point interrupt mode;
according to the interrupt signal, the numerical value in the CPSR register in the user mode is respectively copied to the SPSR register in the IRQ general interrupt mode, the SPSR register in the SWI soft interrupt mode or the SPSR register in the WATCH monitoring point interrupt mode, and the switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode is completed.
A third object of the present invention is to provide an interrupt fast switching apparatus of a DTP processor.
In order to achieve the purpose, the invention adopts the following technical scheme:
an interrupt fast switching device of a DTP processor comprises the DTP processor, which is used for realizing each instruction; and a storage device for storing a plurality of instructions, wherein the instructions are loaded by the DTP processor and perform the following:
receiving an interrupt signal, wherein the interrupt signal comprises that the DTP processor is switched from a user mode to an IRQ general interrupt mode, or is switched from the user mode to an SWI soft interrupt mode, or is switched from the user mode to a WATCH monitoring point interrupt mode;
according to the interrupt signal, the numerical value in the CPSR register in the user mode is respectively copied to the SPSR register in the IRQ general interrupt mode, the SPSR register in the SWI soft interrupt mode or the SPSR register in the WATCH monitoring point interrupt mode, and the switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode is completed.
The invention has the beneficial effects that:
1. the method and the device for rapidly switching the interrupt of the DTP processor solve the problem of complex interrupt switching judgment conditions of the traditional multi-core processor and are beneficial to improving the processing efficiency of the RISC processor.
2. The method and the device for rapidly switching the interruption of the DTP processor can interrupt rapid switching only by using the DTP processor, cross judgment of complex external conditions such as a RISC instruction resolver and the like, and are beneficial to improving conversion efficiency.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
The specific implementation mode is as follows:
the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It is noted that the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods and systems according to various embodiments of the present disclosure. It should be noted that each block in the flowchart or block diagrams may represent a module, a segment, or a portion of code, which may comprise one or more executable instructions for implementing the logical function specified in the respective embodiment. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The invention is further described with reference to the following figures and examples.
Example 1:
the object of this embodiment 1 is to provide a method for fast interrupt switching of a DTP processor.
In order to achieve the purpose, the invention adopts the following technical scheme:
as shown in figure 1 of the drawings, in which,
an interrupt fast switching method of a DTP processor comprises the following steps:
step (1): receiving an interrupt signal, wherein the interrupt signal comprises that the DTP processor is switched from a user mode to an IRQ general interrupt mode, or is switched from the user mode to an SWI soft interrupt mode, or is switched from the user mode to a WATCH monitoring point interrupt mode;
step (2): according to the interrupt signal, the numerical value in the CPSR register in the user mode is respectively copied to the SPSR register in the IRQ general interrupt mode, the SPSR register in the SWI soft interrupt mode or the SPSR register in the WATCH monitoring point interrupt mode, and the switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debugging mode is completed.
The DTP processor of the invention has the following overall structure:
the DTP processor architecture is based on Reduced Instruction Set Computer (RISC) principles. The core of which contains a three-stage pipeline to efficiently process instructions. The DTP processor is a scalar processor. The instruction width is 16 bits wide. The memory data path is 32 bits wide, which allows two instructions to be fetched in one memory cycle.
The DTP processor has 16 general purpose registers. One of the 16 general purpose registers is a program counter and one is a link register. The general purpose registers are 32 bits wide. 16 32-bit general purpose registers are readily available.
The general purpose registers in the DTP processor have special functions: r15 is a program counter; r14 is a stack pointer; r13 is a link register.
The DTP processor supports a variety of operating modes including a user mode, an IRQ general interrupt mode, a SWI soft interrupt mode, and a watchc interrupt mode.
The user mode is the user normal program execution state, and the IRQ general interrupt mode, the SWI soft interrupt mode and the WATCH monitoring point interrupt mode are interrupt states.
The input mode for each operation mode is as follows:
1. after the system is reset, the DTP processor enters a user mode;
2. enabling the interrupt and the IRQ pin is available, and the DTP processor enters an IRQ mode;
3. upon execution of the SWI instruction, the DTP processor enters SWI mode;
4. the monitoring points are enabled and the special monitoring points are triggered, the DTP processor enters the WATCH mode.
When the DTP switches to an interrupt mode (IRQ general interrupt mode, SWI soft interrupt mode, or watchc checkpoint interrupt mode), the appropriate "banked" register (stack pointer/link register) will be used instead of the standard user mode register. Stack pointers, link registers, shift registers, or SPSR registers in IRQ general interrupt mode, SWI soft interrupt mode, or watchc checkpoint interrupt mode are used. Table 1 is the core register of the special-purpose code stream processor, and the shaded registers in the table indicate that the register is of the "banked" type. ,
TABLE 1
All internal registers are 32 bits wide except for the shift register, the CPSR register, and the SPSR register in IRQ general interrupt mode, SWI soft interrupt mode, or in watchc checkpoint interrupt mode. The shift register is 5 bits wide, and the CPSR register and the SPSR register each contain 11 bits of information.
In this embodiment, the CPSR register or the SPSR register has flag bits of a current DTP processor mode, where the flag bits include 00, 01, 10, and 11, which respectively correspond to a user mode, a WATCH monitor point interrupt mode, an IRQ general interrupt mode, and an SWI soft interrupt mode.
The reset values for all status registers are "00001-00000" (user mode, prediction enabled, interrupt disabled, reverse branch taken assumed, pre-fetch data access assumed, and all status flags are 0). The format of the CPSR/SPSR register is shown in Table 2.
TABLE 2
The IRQ general interrupt response condition is that an interrupt is enabled and an IRQ pin is available; the SWI soft interrupt response condition is that an SWI instruction is executed; the WATCH monitoring point interrupt response condition is that a monitoring point is enabled and a special monitoring point is triggered.
In the user mode, the SPSR register of the DTP processor is inaccessible, and the return value of the SPSR register is set to be 0.
In this embodiment, the specific steps of the interrupt processing include: and after the interrupt program is executed, switching from the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debugging mode to the user mode.
Step (2-1): after receiving the interrupt signal, the DTP processor judges the interrupt response condition (shielding and priority) in the interrupt signal, and if the interrupt response condition meets the IRQ general interrupt response condition, the DTP processor is switched from a user mode to an IRQ general interrupt mode; if the SWI soft interrupt response condition is met, switching from the user mode to the SWI soft interrupt mode; if the interrupt response condition of the WATCH monitoring point is met, switching from the user mode to the interrupt mode of the WATCH monitoring point; otherwise, the program continues normal execution.
Step (2-2): inhibiting the transmission of a subsequent command signal according to the interrupt signal; will complete with the issued interrupt instruction execution.
Step (2-3): respectively copying the numerical value in the CPSR register in the user mode to the SPSR register in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode, and storing breakpoint addresses; and saving the breakpoint address.
Step (2-4): and identifying the interrupt source of the interrupt signal to obtain the stroke interrupt vector address.
Step (2-5): and storing the contents of each register to be used in an interrupt service program in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode.
Step (2-6): opening the interrupt so that the interrupts can be nested;
step (2-7): and executing substantive processing of the interrupt service program in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode.
Step (2-8): and turning off the interruption to ensure that the field recovery process is not interrupted by the interruption signal any more.
Step (2-9): restoring the register content used in the interrupt service routine in IRQ general interrupt mode, SWI soft interrupt mode or WATCH monitor point interrupt mode, and restoring the saving of the field in user mode by hardware.
Step (2-10): the DTP processor stores the contents in the SPSR register under the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode into the CPSR register under the user mode again, completes the switching from the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debugging mode to the user mode, and returns the breakpoint of the interrupted program to continue executing.
In this embodiment, the DTP processor further includes a prefetch buffer with four instruction depths for branch prediction. The prediction is a forward or backward assumption set on a static basis. Branch prediction may be disabled entirely. The instruction set is designed to support a complete downstream stack.
Example 2:
the object of this embodiment 2 is to provide a computer-readable storage medium.
In order to achieve the purpose, the invention adopts the following technical scheme:
a computer readable storage medium storing a plurality of instructions, the instructions being loaded by a processor and performing the process of:
receiving an interrupt signal, wherein the interrupt signal comprises that the DTP processor is switched from a user mode to an IRQ general interrupt mode, or is switched from the user mode to an SWI soft interrupt mode, or is switched from the user mode to a WATCH monitoring point interrupt mode;
according to the interrupt signal, the numerical value in the CPSR register in the user mode is respectively copied to the SPSR register in the IRQ general interrupt mode, the SPSR register in the SWI soft interrupt mode or the SPSR register in the WATCH monitoring point interrupt mode, and the switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode is completed.
Example 3:
the object of this embodiment 3 is to provide an interrupt fast switching device of a DTP processor.
In order to achieve the purpose, the invention adopts the following technical scheme:
an interrupt fast switching device of a DTP processor comprises the DTP processor, which is used for realizing each instruction; and a storage device for storing a plurality of instructions, wherein the instructions are loaded by the DTP processor and perform the following:
receiving an interrupt signal, wherein the interrupt signal comprises that the DTP processor is switched from a user mode to an IRQ general interrupt mode, or is switched from the user mode to an SWI soft interrupt mode, or is switched from the user mode to a WATCH monitoring point interrupt mode;
according to the interrupt signal, the numerical value in the CPSR register in the user mode is respectively copied to the SPSR register in the IRQ general interrupt mode, the SPSR register in the SWI soft interrupt mode or the SPSR register in the WATCH monitoring point interrupt mode, and the switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode is completed.
It is noted that in embodiments 2 and 3, the computer program product may comprise a computer readable storage medium having computer readable program instructions embodied thereon for carrying out various aspects of the present disclosure. The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.
The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.
The computer program instructions for carrying out operations of the present disclosure may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry can execute computer-readable program instructions to implement aspects of the present disclosure by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).
It should be noted that although several modules or sub-modules of the device are mentioned in the above detailed description, such division is merely exemplary and not mandatory. Indeed, the features and functionality of two or more of the modules described above may be embodied in one module in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module described above may be further divided into embodiments by a plurality of modules.
The invention has the beneficial effects that:
1. the method and the device for rapidly switching the interrupt of the DTP processor solve the problem of complex interrupt switching judgment conditions of the traditional multi-core processor and are beneficial to improving the processing efficiency of the RISC processor.
2. The method and the device for rapidly switching the interruption of the DTP processor can interrupt rapid switching only by using the DTP processor, cross judgment of complex external conditions such as a RISC instruction resolver and the like, and are beneficial to improving conversion efficiency.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (8)
1. An interrupt fast switching method of a DTP processor is characterized by comprising the following steps:
receiving an interrupt signal, wherein the interrupt signal comprises that the DTP processor is switched from a user mode to an IRQ general interrupt mode, or is switched from the user mode to an SWI soft interrupt mode, or is switched from the user mode to a WATCH monitoring point interrupt mode;
according to the interrupt signal, the numerical values in the CPSR register file in the user mode are respectively and completely mapped and copied to the SPSR flag register file in the IRQ general interrupt mode, the SPSR flag register file in the SWI soft interrupt mode or the SPSR flag register file in the WATCH monitoring point interrupt mode, and the switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debugging mode is completed by using a special stack pointer, a link register, a shift register and corresponding flag SPSR registers in different interrupt modes;
the specific steps of switching from the user mode to the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debug mode include:
inhibiting the transmission of a subsequent command signal according to the interrupt signal;
respectively copying the numerical value in the CPSR register in the user mode to the SPSR register in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode, and storing breakpoint addresses;
identifying an interrupt source of an interrupt signal to obtain a stroke interrupt vector address;
storing the content of each register to be used in an interrupt service program in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode;
opening the interrupt so that the interrupts can be nested;
executing substantive processing of the interrupt service program in an IRQ general interrupt mode, an SWI soft interrupt mode or a WATCH monitoring point interrupt mode;
after the substantive processing of the interrupt service program in IRQ general interrupt mode, SWI soft interrupt mode or WATCH monitor point interrupt mode is executed, the method comprises the following steps:
turning off interruption to ensure that the field recovery process is not interrupted by the interruption signal any more;
restoring the register content used in the interrupt service program in the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode, and restoring the hardware to store the site in the user mode;
the DTP processor stores the contents in the SPSR register under the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH monitoring point interrupt mode into the CPSR register under the user mode again, completes the switching from the IRQ general interrupt mode, the SWI soft interrupt mode or the WATCH debugging mode to the user mode, and returns the breakpoint of the interrupted program to continue executing.
2. The method as claimed in claim 1, wherein the CPSR register or SPSR register has flag bits of current DTP processor mode, the flag bits include four modes of 00, 01, 10 and 11, corresponding to user mode, watchh checkpoint interrupt mode, IRQ general interrupt mode and SWI soft interrupt mode, respectively.
3. The method of claim 1, further comprising: after receiving the interrupt signal, judging an interrupt response condition in the interrupt signal, and if the interrupt response condition meets an IRQ general interrupt response condition, switching from a user mode to an IRQ general interrupt mode; if the SWI soft interrupt response condition is met, switching from the user mode to the SWI soft interrupt mode; if the interrupt response condition of the WATCH monitoring point is met, switching from the user mode to the interrupt mode of the WATCH monitoring point; otherwise, the program continues to execute normally;
the IRQ general interrupt response condition is that an interrupt is enabled and an IRQ pin is available; the SWI soft interrupt response condition is that an SWI instruction is executed; the WATCH monitoring point interrupt response condition is that a monitoring point is enabled and a special monitoring point is triggered.
4. The method of claim 3, wherein in the user mode, the SPSR register of the DTP processor is not accessible, and wherein the return value of the SPSR register is set to 0.
5. The method of claim 3, wherein switching from user mode to IRQ general interrupt mode, SWI soft interrupt mode, or WATCH debug mode uses stack pointer, link register, shift register, or SPSR register in IRQ general interrupt mode, SWI soft interrupt mode, or WATCH checkpoint interrupt mode.
6. The method of claim 1, further comprising a four instruction deep prefetch buffer in the DTP processor for branch prediction.
7. A computer-readable storage medium storing a plurality of instructions for loading by a processor and performing the method of any one of claims 1-6.
8. A control apparatus comprising a processor for implementing instructions; and a storage device for storing a plurality of instructions, wherein the instructions are loaded by the processor and perform the method of any of claims 1-6.
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| CN109376000B (en) * | 2018-10-24 | 2022-02-15 | 芯来科技(武汉)有限公司 | Quick interrupt control system and method for RISC-V architecture |
| CN111722916B (en) * | 2020-06-29 | 2023-11-14 | 长沙新弘软件有限公司 | Method for processing MSI-X interrupt through mapping table |
| CN111782368B (en) * | 2020-06-30 | 2024-02-09 | 珠海全志科技股份有限公司 | Interrupt nesting processing method, device, terminal and storage medium |
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