CN111722916B - Method for processing MSI-X interrupt through mapping table - Google Patents
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- CN111722916B CN111722916B CN202010601585.8A CN202010601585A CN111722916B CN 111722916 B CN111722916 B CN 111722916B CN 202010601585 A CN202010601585 A CN 202010601585A CN 111722916 B CN111722916 B CN 111722916B
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- 238000013507 mapping Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000012545 processing Methods 0.000 title claims abstract description 8
- 239000013598 vector Substances 0.000 claims abstract description 74
- 230000008569 process Effects 0.000 claims abstract description 12
- 230000008859 change Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- COCAUCFPFHUGAA-MGNBDDOMSA-N n-[3-[(1s,7s)-5-amino-4-thia-6-azabicyclo[5.1.0]oct-5-en-7-yl]-4-fluorophenyl]-5-chloropyridine-2-carboxamide Chemical compound C=1C=C(F)C([C@@]23N=C(SCC[C@@H]2C3)N)=CC=1NC(=O)C1=CC=C(Cl)C=N1 COCAUCFPFHUGAA-MGNBDDOMSA-N 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Abstract
A method for processing MSI-X interrupt by mapping table sets a global mapping table, the mapping table is an array formed by a group of units, each unit contains an integer reference value B, and each unit corresponds to an interrupt vector. When registering an interrupt, the initialization program sets the reference value B of one interrupt vector corresponding unit as the reference value of one interrupt number. When the hardware device submits an interrupt to the processor, the processor generating the interrupt searches a corresponding unit in the mapping table according to the interrupt vector, calculates an interrupt number N according to a reference value B in the corresponding unit and a current processor number L, and then transmits the interrupt number N as a parameter to the interrupt processing program. And the interrupt processing program processes the corresponding hardware interrupt process according to the interrupt number N.
Description
Technical Field
The invention relates to the field of computer system software programming, in particular to a method for processing MSI-X interrupt through a mapping table in a hardware device driver.
Background
Interrupts are a common method for a hardware device to notify system software of completion of an IO operation or change of state of the hardware device in a computer system, usually, one hardware device has only one interrupt, and an interrupt handler of the system software determines that the interrupt has occurred by reading a specific hardware interrupt state register value after the interrupt occurs. With the progress of hardware technology, MSI (Message Signal Interrupt) and MSI-X multi-interrupt mechanisms are developed on the basis of the prior art to adapt to higher IO throughput rate and more processor cores, so that one hardware can simultaneously have a plurality of interrupts and each interrupt corresponds to a different function. While interrupt functions become more powerful from a hardware technology perspective, interrupt processing becomes more complex from a software programming perspective. Because in the conventional interrupt handling mode it is sufficient to set one interrupt handler (Interrupt Service Routine), multiple interrupt handlers need to be set for MSI-X interrupts and multiple interrupt vectors need to be applied. For example, gigabit network adapter (Gigabit Network Adapter) using 82576 and I350 chips in Intel corporation PRO/1000 family network cards has a maximum of 8 receive queues and 8 transmit queues, each corresponding to one interrupt, plus up to 17 interrupts to handle network connection state changes. Common operating systems require applying an interrupt vector for each interrupt and setting a corresponding interrupt handler for each vector, making drive development overly complex and wasting too much resources.
Disclosure of Invention
It is an object of the present invention to overcome the above-mentioned deficiencies of the prior art by providing a method of handling MSI-X interrupts through a mapping table. The Interrupt vector is converted into continuous Interrupt numbers (Interrupt numbers) corresponding to the hardware device Interrupt through the mapping table, then the Interrupt numbers are used as parameters to be transmitted to an Interrupt processing program, and the Interrupt processing program processes Interrupt processes corresponding to the hardware device according to the Interrupt numbers.
The first technical scheme of the invention is as follows: a global mapping table is set, wherein the mapping table is an array formed by a group of units, each unit comprises an integer reference value B, and each unit corresponds to an interrupt vector. When registering an interrupt, the initialization program sets the reference value B of one interrupt vector corresponding unit as the reference value of one interrupt number. When an interrupt vector binds a plurality of different processors at the same time, the corresponding unit in the mapping table further includes an interrupt size value S, S being equal to the number of processors bound by the vector, and for convenience in calculation, the number of processors bound must be 1, 2, 4, 8, 16, 32 and …, which are integer power values of 2. When the hardware device submits the interrupt to the processor, the processor generating the interrupt firstly searches the corresponding unit in the mapping table according to the interrupt vector, and then calculates the interrupt number N according to the reference value B, the interrupt processor number L and the interrupt scale value S in the corresponding unit. The calculation formula is as follows: n is equal to B plus L divided by S, i.e., n=b+ (L% S), when S is an integer power of 2, the calculation formula can be reduced to n=b+ (L AND (S-1)), AND it is apparent that n=b+ (L AND 0) =b when S is equal to 1, i.e., the interrupt vector is bound to only one processor.
In one embodiment, the network adapter has 8 receive queues and 8 transmit queues, requiring one interrupt for each queue, plus one network connection state change interrupt for a total of 17 interrupts. The 1 st to 17 th items of the MSI-X table are respectively corresponding to interrupt numbers 1 to 17, and each item of the MSI-X table comprises a message address of a processor and an interrupt vector for setting the binding relation between the interrupt vector and the processor. The interrupt numbers of the 8 receiving queues are 1 to 8, the interrupt numbers of the 8 transmitting queues are 9 to 16, and the interrupt number of the network connection state change is 17. 3 interrupt vectors 90, 91 and 92 are distributed from the system, reference values B of corresponding units of the 3 interrupt vectors in the mapping table are respectively set to be 1, 9 and 17, and then 17 interrupt items of the MSI-X table are set as follows:
setting MSI-X table entry 1 to interrupt vector 90 bound to processor number 0;
setting MSI-X table entry 2 to interrupt vector 90 bound to processor number 1;
setting MSI-X table entry 3 to interrupt vector 90 bound to processor number 2;
setting MSI-X table entry 4 to interrupt vector 90 bound to processor number 3;
setting MSI-X table entry 5 to interrupt vector 90 bound to processor number 4;
setting MSI-X table entry 6 to interrupt vector 90 bound to processor number 5;
setting MSI-X table entry 7 to interrupt vector 90 bound to processor number 6;
setting MSI-X table entry 8 to interrupt vector 90 bound to processor number 7;
setting MSI-X table entry 9 to interrupt vector 91 bound to processor number 0;
setting MSI-X table entry 10 to interrupt vector 91 bound to processor number 1;
setting MSI-X table entry 11 to interrupt vector 91 bound to processor number 2;
setting MSI-X table entry 12 to interrupt vector 91 bound to processor number 3;
setting MSI-X table entry 13 to interrupt vector 91 bound to processor number 4;
setting MSI-X table entry 14 to interrupt vector 91 bound to processor number 5;
setting MSI-X table entry 15 to interrupt vector 91 bound to processor number 6;
setting MSI-X table entry 16 to interrupt vector 91 bound to processor number 7;
setting MSI-X table entry 17 to interrupt vector 92 bound to processor number 0;
since both interrupt vectors 90 and 91 bind 8 processors at the same time, the interrupt size S of the corresponding unit of these two vectors in the mapping table is set to 8. When the 2 nd receiving queue generates an interrupt, 90 vector interrupts bound to the No. 1 processor in the 2 nd item of the MSI-X table are activated, the No. 1 processor searches the reference value B of the corresponding unit in the mapping table to be 1 according to the interrupt vector 90 after the interrupt occurs, the interrupt scale S is 8, AND then the interrupt number N=1+ (1 AND 7) =2 is calculated according to the current processor number. And then the interrupt number is transferred to an interrupt processing program, and the interrupt processing program processes the data received by the 2 nd receiving queue according to the interrupt number 2. Similarly, when the 3 rd transmission queue generates an interrupt, the 91 st vector interrupt bound to the No. 2 processor in the 11 th item of the MSI-X table is activated, the No. 2 processor checks the reference value B of the corresponding unit in the mapping table to be 9 according to the interrupt vector 91 after the interrupt occurs, the interrupt scale S is 8, AND then the interrupt number N=9+ (2 AND 7) =11 is calculated according to the number of the current processor. The interrupt handler processes the data that the 3 rd transmit queue has been transmitted according to the interrupt number 11.
The second technical scheme of the invention is as follows: a mapping table is set for each processor in the system, each mapping table is an array formed by a group of units, each unit comprises an interrupt number N, and each unit corresponds to an interrupt vector. When registering an interrupt, the initialization program sets the interrupt number N of the interrupt vector corresponding unit to the interrupt number bound to the processor. When the hardware device submits an interrupt to the processor, the processor generating the interrupt searches a corresponding unit in a mapping table of the current processor according to the interrupt vector, then transmits an interrupt number N in the corresponding unit as a parameter to an interrupt processing program, and the interrupt processing program processes a corresponding hardware interrupt process according to the interrupt number N. When one interrupt vector is bound to a plurality of different processors at the same time, mapping tables of each processor need to be set respectively, and interrupt numbers N of corresponding units of the interrupt vector in each mapping table are set to different values. Compared with the first technical scheme, the method has poor mobility although calculation is not needed, for example, in the embodiment of the first technical scheme, the calculation result of the interrupt number N is not affected when the interrupt items of the receiving and transmitting queues in the MSI-X table are dynamically bound to processors No. 8 to No. 15. And when the second technical scheme is adopted, the dynamic modification of the bound processor is required to modify the mapping table corresponding to the processor at the same time.
Compared with the prior art, the invention has the following characteristics: the invention describes a binary parameter formed by interrupt vector and processor number, which is converted into interrupt number by mapping table and transferred to interrupt processing program as parameter. Under the condition of insufficient interrupt vector resources, a plurality of hardware interrupts are realized by binding one vector to different processors at the same time, so that the utilization rate of interrupt vector resources is improved. Meanwhile, the interrupt processing program can be well compatible with the traditional interrupt processing, and standardization of a driver interface is facilitated.
The detailed structure of the present invention is further described below with reference to the accompanying drawings and detailed description.
Drawings
FIG. 1 is a first technical scheme, wherein a reference value B corresponding to an interrupt vector is searched through a global mapping table, and then an interrupt number N is calculated according to the reference value B and a processor number L;
fig. 2 is a schematic diagram of a second technical solution, in which an interrupt number N corresponding to an interrupt vector is searched by a mapping table of each processor.
Detailed Description
As shown in fig. 1: three interrupt vectors, 90, 91 and 92 respectively, are arranged in the MSI-X table; the reference values B corresponding to the three vectors in the mapping table are 1, 9 and 17 respectively, wherein the vectors 90 and 91 are respectively bound with 8 processors, the processor numbers L are respectively 0 to 7, and the corresponding interrupt scale S is equal to 8; the interruption number N of each entry of the MSI-X table from top to bottom is calculated to be 1 to 17 according to the calculation formula n=b+ (L AND (S-1)).
As shown in fig. 2: three interrupt vectors, 90, 91 and 92 respectively, are arranged in the MSI-X table; each processor has a separate mapping table, wherein vectors 90 and 91 bind 8 processors respectively, the processor numbers L are 0 to 7 respectively, and the mapping table of each processor sets different values for interrupt numbers N of the units; the interrupt number N is directly queried through the mapping table of the binding processor, and the interrupt number N of each item from top to bottom of the query MSI-X table is 1 to 17.
The present invention relates to MSI-X interrupts in hardware technology, MSI-X being one embodiment of a multiple interrupt technology, and incorporating the technical information disclosed herein to those skilled in the art. The ability to practice the invention in similar multiple interrupt schemes should not be construed to be outside the scope of the invention.
Noun interpretation
MSI-X interrupts: is a solution for performing a functional extension on the basis of Message Signaled Interruption (MSI), a plurality of interrupts are configured by means of an additional interrupt configuration table, each entry of the interrupt configuration table containing a message address of a processor and an interrupt vector.
Claims (3)
1. A method for processing MSI-X interrupts through a mapping table, characterized by: setting a global mapping table which is an array formed by a group of units, wherein each unit comprises an integer reference value B, and each unit corresponds to an interrupt vector; when registering an interrupt, the initialization program sets a reference value B of an interrupt vector corresponding unit as a reference value of an interrupt number; when the hardware equipment submits an interrupt to the processor, the processor generating the interrupt searches a corresponding unit in the mapping table according to the interrupt vector, calculates an interrupt number N according to a reference value B in the corresponding unit and a current processor number L, and then transmits the interrupt number N as a parameter to an interrupt processing program; the interrupt processing program processes the corresponding hardware interrupt process according to the interrupt number N;
when an interrupt vector is bound with a plurality of different processors at the same time, the corresponding unit in the mapping table also comprises an interrupt scale value S, wherein S is equal to the number of the processors bound by the vector; when the hardware equipment submits an interrupt to the processor, the processor which generates the interrupt searches a corresponding unit in the mapping table according to the interrupt vector, and then calculates an interrupt number N according to a reference value B and an interrupt scale value S in the corresponding unit and a current processor number L, wherein a calculation formula is a remainder value of dividing B by L by S, namely N=B+ (L%S); when S is an integer power of 2, the calculation formula can be simplified to n=b+ (LAND (S-1)); n=b+ (LAND 0) =b when S is equal to 1, i.e. the interrupt vector binds only one processor.
2. A method of handling MSI-X interrupts through a mapping table according to claim 1, in which: when the number of processors bound by one interrupt vector is smaller than the total number of processors in the system, the bound processors can rebind the interrupt vector to another processor after an interrupt occurs, and the new processor number M is equal to the current processor number L plus an interrupt scale value S, namely M=L+S; if the new processor number M is greater than the maximum processor number in the system, then dividing M by the interrupt size value S takes the remainder, i.e., m=m% S, where m=mand (S-1) when S is an integer power of 2.
3. A method for processing MSI-X interrupts through a mapping table, characterized by: setting a mapping table for each processor in the system, wherein each mapping table is an array formed by a group of units, each unit comprises an interrupt number N, and each unit corresponds to an interrupt vector; when registering an interrupt, the initialization program sets an interrupt number N of an interrupt vector corresponding unit as an interrupt number bound to the processor; when the hardware device submits an interrupt to the processor, the processor generating the interrupt searches a corresponding unit in a mapping table of the current processor according to the interrupt vector, then transmits an interrupt number N in the corresponding unit as a parameter to an interrupt processing program, and the interrupt processing program processes a corresponding hardware interrupt process according to the interrupt number N;
when an interrupt vector is simultaneously bound with a plurality of different processors, the interrupt number N of a corresponding unit in a mapping table of each processor needs to be set with different values, and the corresponding unit of the interrupt vector in the mapping table also comprises an interrupt scale value S, wherein S is equal to the number of the processors bound by the vector; when the hardware equipment submits an interrupt to the processor, the processor which generates the interrupt searches a corresponding unit in the mapping table according to the interrupt vector, and then calculates an interrupt number N according to a reference value B and an interrupt scale value S in the corresponding unit and a current processor number L, wherein a calculation formula is a remainder value of dividing B by L by S, namely N=B+ (L%S); when S is an integer power of 2, the calculation formula can be simplified to n=b+ (LAND (S-1)); n=b+ (LAND 0) =b when S is equal to 1, i.e. the interrupt vector binds only one processor.
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