CN111722916A - Method for processing MSI-X interruption by mapping table - Google Patents
Method for processing MSI-X interruption by mapping table Download PDFInfo
- Publication number
- CN111722916A CN111722916A CN202010601585.8A CN202010601585A CN111722916A CN 111722916 A CN111722916 A CN 111722916A CN 202010601585 A CN202010601585 A CN 202010601585A CN 111722916 A CN111722916 A CN 111722916A
- Authority
- CN
- China
- Prior art keywords
- interrupt
- processor
- mapping table
- vector
- msi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013507 mapping Methods 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000013598 vector Substances 0.000 claims abstract description 79
- 230000007812 deficiency Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
A method for processing MSI-X interruption by mapping table is to set a global mapping table, the mapping table is an array formed by a group of units, each unit contains an integer reference value B, and each unit corresponds to an interruption vector. When registering interrupt, the initialization program sets the reference value B of a unit corresponding to an interrupt vector as the reference value of an interrupt number. When the hardware equipment submits the interrupt to the processor, the processor which generates the interrupt searches the corresponding unit in the mapping table according to the interrupt vector, then calculates the interrupt number N according to the reference value B in the corresponding unit and the current processor number L, and then transmits the interrupt number N as a parameter to the interrupt processing program. And the interrupt processing program processes the corresponding hardware interrupt process according to the interrupt number N.
Description
Technical Field
The invention relates to the field of computer system software programming, in particular to a method for processing MSI-X interrupt through a mapping table in a hardware device driver.
Background
An interrupt in a computer system is a common method for a hardware device to notify the system software of the completion of data IO operation or the change of the state of the hardware device, usually, one hardware device has only one interrupt, and an interrupt handler of the system software determines which interrupt occurs by reading a specific hardware interrupt state register value after the interrupt occurs. With the advance of hardware technology, in order to adapt to higher IO throughput and more processor cores, an MSI (message signal interrupt) and MSI-X multi-interrupt mechanism is developed on the original basis, so that one piece of hardware can simultaneously have multiple interrupts, and each interrupt corresponds to a different function. Although interrupt functions become more powerful from a hardware technology point of view, interrupt processing becomes more complex from a software programming point of view. Because only one Interrupt handler (Interrupt Service Routine) needs to be set in the conventional Interrupt handling mode, a plurality of Interrupt handlers need to be set for the MSI-X Interrupt, and a plurality of Interrupt vectors need to be applied. For example, a Gigabit Network Adapter (Gigabit Network Adapter) using 82576 and I350 chips in the PRO/1000 series Network card of Intel corporation has at most 8 receiving queues and 8 sending queues, each queue corresponds to one interrupt, and the total number of interrupts for processing Network connection state changes can reach 17 interrupts. A common operating system needs to apply for an interrupt vector for each interrupt and set a corresponding interrupt handler for each vector, so that driver development becomes too complicated and wastes too many resources.
Disclosure of Invention
It is an object of the present invention to overcome the above-mentioned deficiencies of the prior art and to provide a method of handling MSI-X interrupts through a mapping table. Converting the interrupt vector into a continuous interrupt number (interrupt number) corresponding to the interrupt of the hardware equipment through a mapping table, then transmitting the interrupt number as a parameter to an interrupt handler, and processing the interrupt process corresponding to the hardware equipment by the interrupt handler according to the interrupt number.
The first technical scheme of the invention is as follows: and setting a global mapping table, wherein the mapping table is an array formed by a group of units, each unit comprises an integer reference value B, and each unit corresponds to an interrupt vector. When registering interrupt, the initialization program sets the reference value B of a unit corresponding to an interrupt vector as the reference value of an interrupt number. When an interrupt vector binds a plurality of different processors simultaneously, the corresponding unit in the mapping table also includes an interrupt size value S, S is equal to the number of processors bound by the vector, and the number of bound processors must be an integer power value of 2, such as 1, 2, 4, 8, 16, 32 …, for convenience of calculation. When the hardware equipment submits the interrupt to the processor, the processor which generates the interrupt firstly searches the corresponding unit in the mapping table according to the interrupt vector, and then calculates the interrupt number N according to the reference value B in the corresponding unit, the processor number L of the interrupt and the interrupt scale value S. The calculation formula is as follows: n equals B plus the remainder of L divided by S, i.e. N = B + (L% S), the calculation formula can be reduced to N = B + (L AND (S-1)) when S is an integer power of 2, obviously N = B + (L AND 0) = B when S equals 1, i.e. the interrupt vector binds only one processor.
In one embodiment, where the network adapter has 8 receive queues and 8 transmit queues, it is necessary to configure one interrupt for each queue, plus one network connection state change interrupt, for a total of 17 interrupts. And respectively corresponding 1 st item to 17 th item of the MSI-X table to interrupt numbers 1 to 17, wherein each item in the MSI-X table comprises a message address of a processor and an interrupt vector and is used for setting the binding relationship between the interrupt vector and the processor. The interrupt numbers of 8 receive queues are 1 to 8, the interrupt numbers of 8 transmit queues are 9 to 16, and the interrupt number of the network connection state change is 17. Distributing 3 interrupt vectors 90, 91 and 92 from the system, respectively setting reference values B of corresponding units of the 3 interrupt vectors in a mapping table to be 1, 9 and 17, and then setting 17 interrupt items of an MSI-X table as follows:
setting item 1 of the MSI-X table as an interrupt vector 90 and binding the interrupt vector to a processor number 0;
setting item 2 of the MSI-X table as an interrupt vector 90 and binding the interrupt vector to a processor number 1;
setting item 3 of the MSI-X table as an interrupt vector 90 and binding the interrupt vector to a processor number 2;
setting item 4 of the MSI-X table as an interrupt vector 90 and binding the interrupt vector to a processor number 3;
setting an MSI-X table item 5 as an interrupt vector 90 to be bound to a processor number 4;
setting item 6 of the MSI-X table as an interrupt vector 90 to be bound to a processor number 5;
setting item 7 of the MSI-X table as an interrupt vector 90 to be bound to a processor number 6;
setting an MSI-X table item 8 as an interrupt vector 90 to be bound to a processor number 7;
setting item 9 of the MSI-X table as an interrupt vector 91 and binding the interrupt vector to a processor number 0;
setting item 10 of the MSI-X table as an interrupt vector 91 and binding the interrupt vector to a processor number 1;
setting an MSI-X table item 11 as an interrupt vector 91 and binding the interrupt vector to a processor number 2;
setting an MSI-X table item 12 as an interrupt vector 91 and binding the interrupt vector to a processor number 3;
setting item 13 of the MSI-X table as an interrupt vector 91 and binding the interrupt vector to a processor number 4;
setting item 14 of the MSI-X table as an interrupt vector 91 to be bound to a processor number 5;
setting an MSI-X table item 15 as an interrupt vector 91 to be bound to a processor number 6;
setting item 16 of the MSI-X table as an interrupt vector 91 to be bound to a processor number 7;
setting item 17 of the MSI-X table as an interrupt vector 92 to be bound to a processor number 0;
since the interrupt vectors 90 and 91 are both bound to 8 processors at the same time, the interrupt size S of the corresponding unit in the mapping table for these two vectors is set to 8. When the 2 nd receiving queue generates interruption, the 90 vector interruption which is bound to the processor No. 1 in the 2 nd item in the MSI-X table is activated, after the processor No. 1 generates interruption, the reference value B of the corresponding unit in the mapping table is found to be 1 according to the interruption vector 90, the interruption scale S is 8, AND then the interruption number N = 1 + (1 AND 7) = 2 is obtained by calculation according to the current processor number. And then transmitting the interrupt number to an interrupt processing program, and processing the data received by the 2 nd receiving queue by the interrupt processing program according to the interrupt number 2. Similarly, when the 3 rd send queue generates interrupt, 91 vector interrupt binding the 11 th entry in the MSI-X table to the processor No. 2 is activated, after the processor No. 2 generates interrupt, the reference value B of the corresponding unit in the mapping table is found to be 9 according to the interrupt vector 91, the interrupt scale S is 8, AND then the interrupt number N = 9 + (2 AND 7) = 11 is calculated according to the current processor number. And the interrupt processing program processes the data which is sent by the 3 rd sending queue according to the interrupt number 11.
The second technical scheme of the invention is as follows: and setting a mapping table for each processor in the system, wherein each mapping table is an array formed by a group of units, each unit comprises an interrupt number N, and each unit corresponds to an interrupt vector. When registering interrupt, the initialization program sets the interrupt number N of the interrupt vector corresponding unit as the interrupt number bound to the processor. When the hardware equipment submits the interrupt to the processor, the processor which generates the interrupt searches the corresponding unit in the mapping table of the current processor according to the interrupt vector, then transmits the interrupt number N in the corresponding unit as a parameter to the interrupt processing program, and the interrupt processing program processes the corresponding hardware interrupt process according to the interrupt number N. When one interrupt vector binds a plurality of different processors at the same time, a mapping table of each processor needs to be set respectively, and the interrupt number N of the corresponding unit of the interrupt vector in each mapping table is set to different values. Compared with the first technical solution, although the calculation is not needed, the mobility is worse, for example, in the embodiment of the first technical solution, when the interrupt items of the receiving and sending queues in the MSI-X table are dynamically bound to the processors No. 8 to No. 15, the calculation result of the interrupt number N is not affected. When the second technical scheme is adopted, the bound processor is dynamically modified, and a mapping table corresponding to the processor needs to be modified.
Compared with the prior art, the invention has the following characteristics: the invention discloses a method for processing an interrupt handler by converting binary parameters formed by an interrupt vector and a processor number into interrupt numbers through a mapping table and transmitting the interrupt numbers to the interrupt handler as the parameters. Under the condition that the resources of the interrupt vectors are insufficient, a plurality of hardware interrupts are realized by simultaneously binding one vector to different processors, and the utilization rate of the resources of the interrupt vectors is improved. Meanwhile, the interrupt processing program can be well compatible with the traditional interrupt processing, and the standardization of a driver interface is facilitated.
The detailed structure of the present invention will be further described with reference to the accompanying drawings and the detailed description.
Drawings
FIG. 1 is a first technical solution, which is to search a reference value B corresponding to an interrupt vector through a global mapping table, and then calculate an interrupt number N according to the reference value B and a processor number L;
fig. 2 shows a second technical solution, which searches the mapping table of each processor for the interrupt number N corresponding to the interrupt vector.
Detailed Description
As shown in figure 1: three interrupt vectors, 90, 91 and 92 respectively, are set in the MSI-X table; reference values B corresponding to three vectors in a mapping table are respectively 1, 9 and 17, wherein the vectors 90 and 91 are respectively bound with 8 processors, the processor numbers L are respectively 0 to 7, and the corresponding interrupt scale S is equal to 8; the MSI-X table is calculated according to the calculation formula N = B + (L AND (S-1)) with the interrupt numbers N of each entry from top to bottom being 1 to 17.
As shown in fig. 2: three interrupt vectors, 90, 91 and 92 respectively, are set in the MSI-X table; each processor has a separate mapping table, wherein vectors 90 and 91 are respectively bound with 8 processors, processor numbers L are respectively 0 to 7, and the interrupt number N of a corresponding unit of the mapping table of each processor is set with different values; directly querying the interrupt number N through a mapping table of the binding processor, and querying each item of the MSI-X table from top to bottom, wherein the interrupt number N is 1 to 17.
The present invention relates to MSI-X interrupts in hardware technology, MSI-X being an implementation of a multiple interrupt technique, and to those skilled in the art, incorporating the technical information disclosed herein. The present invention can be practiced in a similar multi-break solution and these implementations should not be construed as beyond the scope of the present invention.
Noun interpretation
MSI-X interruption: the method is a technical scheme for carrying out function expansion on the basis of Message Signaled Interrupts (MSI), and a plurality of interrupts are configured through an additional interrupt configuration table, wherein each item of the interrupt configuration table comprises a message address of a processor and an interrupt vector.
Claims (5)
1. A method for processing MSI-X interruption by mapping table is characterized in that: setting a global mapping table, wherein the mapping table is an array formed by a group of units, each unit comprises an integer reference value B, and each unit corresponds to an interrupt vector; when the registration is interrupted, the initialization program sets a reference value B of a unit corresponding to an interrupt vector as a reference value of an interrupt number; when the hardware equipment submits the interrupt to the processor, the processor which generates the interrupt searches a corresponding unit in the mapping table according to the interrupt vector, then calculates an interrupt number N according to a reference value B in the corresponding unit and a current processor number L, and transmits the interrupt number N as a parameter to an interrupt processing program; and the interrupt processing program processes the corresponding hardware interrupt process according to the interrupt number N.
2. A method of handling MSI-X interrupts through a mapping table as claimed in claim 1, wherein: when one interrupt vector binds a plurality of different processors at the same time, the corresponding unit in the mapping table also comprises an interrupt scale value S, wherein S is equal to the number of the processors bound by the vector; when the hardware equipment submits an interrupt to the processor, the processor which generates the interrupt searches a corresponding unit in the mapping table according to the interrupt vector, then calculates an interrupt number N according to a reference value B and an interrupt scale value S in the corresponding unit and a current processor number L, and the calculation formula is a remainder value of B plus L divided by S, namely N = B + (L% S); when S is an integer power of 2, the calculation formula can be simplified to N = B + (L AND (S-1)); n = B + (L AND 0) = B when S equals 1, i.e. the interrupt vector binds only one processor.
3. A method of handling MSI-X interrupts through a mapping table as claimed in claim 2, wherein: when the number of processors bound by one interrupt vector is less than the total number of processors in the system, the bound processors can bind the interrupt vector to another processor again after the interrupt occurs, and the new processor number M is equal to the current processor number L plus the interrupt size value S, namely M = L + S; if the new processor number M is greater than the maximum processor number in the system, then divide M by the interrupt size value S for the remainder, i.e., M = M% S, AND M = M AND (S-1) when S is an integer power of 2.
4. A method for processing MSI-X interruption by mapping table is characterized in that: setting a mapping table for each processor in the system, wherein each mapping table is an array formed by a group of units, each unit comprises an interrupt number N, and each unit corresponds to an interrupt vector; when registering interrupt, the initialization program sets the interrupt number N of the interrupt vector corresponding unit as the interrupt number bound to the processor; when the hardware equipment submits the interrupt to the processor, the processor which generates the interrupt searches the corresponding unit in the mapping table of the current processor according to the interrupt vector, then transmits the interrupt number N in the corresponding unit as a parameter to the interrupt processing program, and the interrupt processing program processes the corresponding hardware interrupt process according to the interrupt number N.
5. The method of processing MSI-X interrupts via a mapping table as claimed in claim 4, wherein: when one interrupt vector binds a plurality of different processors at the same time, the interrupt number N of the corresponding unit in the mapping table of each processor needs to be set to a different value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010601585.8A CN111722916B (en) | 2020-06-29 | 2020-06-29 | Method for processing MSI-X interrupt through mapping table |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010601585.8A CN111722916B (en) | 2020-06-29 | 2020-06-29 | Method for processing MSI-X interrupt through mapping table |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111722916A true CN111722916A (en) | 2020-09-29 |
| CN111722916B CN111722916B (en) | 2023-11-14 |
Family
ID=72569363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010601585.8A Active CN111722916B (en) | 2020-06-29 | 2020-06-29 | Method for processing MSI-X interrupt through mapping table |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111722916B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114726657A (en) * | 2022-03-21 | 2022-07-08 | 京东科技信息技术有限公司 | Method and device for interrupt management and data receiving and sending management and intelligent network card |
| CN118132243A (en) * | 2024-05-07 | 2024-06-04 | 浪潮电子信息产业股份有限公司 | Interrupt signal processing method, device, equipment, medium, circuit and system |
Citations (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1047931A (en) * | 1989-05-17 | 1990-12-19 | 国际商业机器公司 | The method and the device of direct transmission information between the application program that does not adopt the service of one or two operating system and in different processor, move |
| JPH04318654A (en) * | 1991-02-13 | 1992-11-10 | Hewlett Packard Co <Hp> | Redirection system for interruption to microprocessor |
| CN1230722A (en) * | 1989-05-17 | 1999-10-06 | 国际商业机器公司 | Uncoupling central processing unit from its associated hardware for interaction with data handling apparatus alien to operating system controlling said unit and hardware |
| EP0992916A1 (en) * | 1998-10-06 | 2000-04-12 | Texas Instruments Inc. | Digital signal processor |
| WO2000036513A2 (en) * | 1998-12-18 | 2000-06-22 | Unisys Corporation | A memory address translation system and method for a memory having multiple storage units |
| US6163829A (en) * | 1998-04-17 | 2000-12-19 | Intelect Systems Corporation | DSP interrupt control for handling multiple interrupts |
| TW482960B (en) * | 2000-06-23 | 2002-04-11 | Inventec Corp | Method for preventing process contradiction between each processors in a multi-processor computer |
| US6678801B1 (en) * | 1998-04-17 | 2004-01-13 | Terraforce Technologies Corp. | DSP with distributed RAM structure |
| US6738847B1 (en) * | 2000-11-10 | 2004-05-18 | Unisys Corporation | Method for assigning a multiplicity of interrupt vectors in a symmetric multi-processor computing environment |
| US20070124523A1 (en) * | 2005-11-28 | 2007-05-31 | Hitachi, Ltd. | Heterogeneous multiprocessor system and OS configuration method thereof |
| CN101135982A (en) * | 2006-08-28 | 2008-03-05 | 国际商业机器公司 | Method and device for managing information transmission interruption resources |
| CN101140530A (en) * | 2006-09-07 | 2008-03-12 | 环隆电气股份有限公司 | Application program intercept and capture and monitoring system control break method |
| WO2008122746A1 (en) * | 2007-04-10 | 2008-10-16 | Cambridge Consultants Limited | Data processing apparatus |
| CN101645005A (en) * | 2008-08-06 | 2010-02-10 | 中国人民解放军信息工程大学 | Processor structure and instruction system representation method based on multi-dimensional variable description table |
| CN102521177A (en) * | 2011-12-07 | 2012-06-27 | 福建星网锐捷网络有限公司 | Interrupt processing method and device, central processing unit and processing apparatus |
| CN103761145A (en) * | 2009-01-26 | 2014-04-30 | 超威半导体公司 | Guest interrupt controllers for each processor to aid interrupt virtualization |
| US9047208B1 (en) * | 2012-12-10 | 2015-06-02 | Qlogic, Corporation | Method and system of configuring virtual function in peripheral devices |
| CN105183541A (en) * | 2015-08-10 | 2015-12-23 | 上海斐讯数据通信技术有限公司 | Response interrupting method and system |
| US20160055108A1 (en) * | 2014-08-20 | 2016-02-25 | Red Hat Israel, Ltd. | Managing message signaled interrupts in virtualized computer systems |
| WO2016059692A1 (en) * | 2014-10-16 | 2016-04-21 | 株式会社日立製作所 | Computer and i/o processing control method |
| US20160147679A1 (en) * | 2014-11-25 | 2016-05-26 | Intel Corporation | Posted interrupt architecture |
| CN105993009A (en) * | 2013-11-18 | 2016-10-05 | 华为技术有限公司 | Method and apparatus for delivering msi-x interrupts through non-transparent bridges to computing resources in pci-express clusters |
| US20170177518A1 (en) * | 2015-12-21 | 2017-06-22 | Intel Corporation | Emulated MSI Interrupt Handling |
| CN108037951A (en) * | 2017-12-27 | 2018-05-15 | 山东师范大学 | The interruption fast switch over method and device of a kind of DTP processors |
| CN109977061A (en) * | 2017-12-28 | 2019-07-05 | 中兴通讯股份有限公司 | A kind of interruption processing method and interrupt processing device |
-
2020
- 2020-06-29 CN CN202010601585.8A patent/CN111722916B/en active Active
Patent Citations (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1047931A (en) * | 1989-05-17 | 1990-12-19 | 国际商业机器公司 | The method and the device of direct transmission information between the application program that does not adopt the service of one or two operating system and in different processor, move |
| CN1230722A (en) * | 1989-05-17 | 1999-10-06 | 国际商业机器公司 | Uncoupling central processing unit from its associated hardware for interaction with data handling apparatus alien to operating system controlling said unit and hardware |
| JPH04318654A (en) * | 1991-02-13 | 1992-11-10 | Hewlett Packard Co <Hp> | Redirection system for interruption to microprocessor |
| US6163829A (en) * | 1998-04-17 | 2000-12-19 | Intelect Systems Corporation | DSP interrupt control for handling multiple interrupts |
| US6678801B1 (en) * | 1998-04-17 | 2004-01-13 | Terraforce Technologies Corp. | DSP with distributed RAM structure |
| EP0992916A1 (en) * | 1998-10-06 | 2000-04-12 | Texas Instruments Inc. | Digital signal processor |
| WO2000036513A2 (en) * | 1998-12-18 | 2000-06-22 | Unisys Corporation | A memory address translation system and method for a memory having multiple storage units |
| TW482960B (en) * | 2000-06-23 | 2002-04-11 | Inventec Corp | Method for preventing process contradiction between each processors in a multi-processor computer |
| US6738847B1 (en) * | 2000-11-10 | 2004-05-18 | Unisys Corporation | Method for assigning a multiplicity of interrupt vectors in a symmetric multi-processor computing environment |
| US20070124523A1 (en) * | 2005-11-28 | 2007-05-31 | Hitachi, Ltd. | Heterogeneous multiprocessor system and OS configuration method thereof |
| US20080126617A1 (en) * | 2006-08-28 | 2008-05-29 | Sean Thomas Brownlow | Message Signaled Interrupt Management for a Computer Input/Output Fabric Incorporating Dynamic Binding |
| CN101135982A (en) * | 2006-08-28 | 2008-03-05 | 国际商业机器公司 | Method and device for managing information transmission interruption resources |
| CN101140530A (en) * | 2006-09-07 | 2008-03-12 | 环隆电气股份有限公司 | Application program intercept and capture and monitoring system control break method |
| WO2008122746A1 (en) * | 2007-04-10 | 2008-10-16 | Cambridge Consultants Limited | Data processing apparatus |
| CN101645005A (en) * | 2008-08-06 | 2010-02-10 | 中国人民解放军信息工程大学 | Processor structure and instruction system representation method based on multi-dimensional variable description table |
| CN103761145A (en) * | 2009-01-26 | 2014-04-30 | 超威半导体公司 | Guest interrupt controllers for each processor to aid interrupt virtualization |
| CN102521177A (en) * | 2011-12-07 | 2012-06-27 | 福建星网锐捷网络有限公司 | Interrupt processing method and device, central processing unit and processing apparatus |
| US9047208B1 (en) * | 2012-12-10 | 2015-06-02 | Qlogic, Corporation | Method and system of configuring virtual function in peripheral devices |
| CN105993009A (en) * | 2013-11-18 | 2016-10-05 | 华为技术有限公司 | Method and apparatus for delivering msi-x interrupts through non-transparent bridges to computing resources in pci-express clusters |
| US20160055108A1 (en) * | 2014-08-20 | 2016-02-25 | Red Hat Israel, Ltd. | Managing message signaled interrupts in virtualized computer systems |
| WO2016059692A1 (en) * | 2014-10-16 | 2016-04-21 | 株式会社日立製作所 | Computer and i/o processing control method |
| US20160147679A1 (en) * | 2014-11-25 | 2016-05-26 | Intel Corporation | Posted interrupt architecture |
| CN105183541A (en) * | 2015-08-10 | 2015-12-23 | 上海斐讯数据通信技术有限公司 | Response interrupting method and system |
| US20170177518A1 (en) * | 2015-12-21 | 2017-06-22 | Intel Corporation | Emulated MSI Interrupt Handling |
| CN108037951A (en) * | 2017-12-27 | 2018-05-15 | 山东师范大学 | The interruption fast switch over method and device of a kind of DTP processors |
| CN109977061A (en) * | 2017-12-28 | 2019-07-05 | 中兴通讯股份有限公司 | A kind of interruption processing method and interrupt processing device |
Non-Patent Citations (3)
| Title |
|---|
| B. CHEN: "Optimizing Network I/O Virtualization for Scale-Out Processor", 《2018 IEEE SMARTWORLD, UBIQUITOUS INTELLIGENCE & COMPUTING, ADVANCED & TRUSTED COMPUTING, SCALABLE COMPUTING & COMMUNICATIONS, CLOUD & BIG DATA COMPUTING, INTERNET OF PEOPLE AND SMART CITY INNOVATION》 * |
| J. S. S. PRASAD, K. N. V. PRASAD AND G. NARAYANAN: "Timer Based Digital Implementation of Advanced Bus-Clamping PWM Techniques", 《2018 INTERNATIONAL CONFERENCE ON COMPUTING, POWER AND COMMUNICATION TECHNOLOGIES (GUCON)》 * |
| 崔晨;李清宝;胡刚;王炜: "基于中断向量表重构的固件代码反汇编技术", 《计算机科学》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114726657A (en) * | 2022-03-21 | 2022-07-08 | 京东科技信息技术有限公司 | Method and device for interrupt management and data receiving and sending management and intelligent network card |
| CN118132243A (en) * | 2024-05-07 | 2024-06-04 | 浪潮电子信息产业股份有限公司 | Interrupt signal processing method, device, equipment, medium, circuit and system |
| CN118132243B (en) * | 2024-05-07 | 2024-07-19 | 浪潮电子信息产业股份有限公司 | Interrupt signal processing method, device, equipment, medium, circuit and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111722916B (en) | 2023-11-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9258171B2 (en) | Method and system for an OS virtualization-aware network interface card | |
| CN110888827B (en) | Data transmission method, device, equipment and storage medium | |
| CN102483705B (en) | User-level interrupt mechanism for multi-core architectures | |
| US9396154B2 (en) | Multi-core processor for managing data packets in communication network | |
| US7953915B2 (en) | Interrupt dispatching method in multi-core environment and multi-core processor | |
| US5619705A (en) | System and method for cascading multiple programmable interrupt controllers utilizing separate bus for broadcasting interrupt request data packet in a multi-processor system | |
| CN104503728A (en) | Hardware accelerator and chip | |
| WO2005116799A2 (en) | Processor timing apparatus, systems, and methods | |
| CN109739786B (en) | DMA controller and heterogeneous acceleration system | |
| CN110278161B (en) | Message distribution method, device and system based on user mode protocol stack | |
| CN111722916A (en) | Method for processing MSI-X interruption by mapping table | |
| CN101634974A (en) | Method, device and system for processing multiple interrupt types | |
| US20030204655A1 (en) | Prioritizing vector generation in interrupt controllers | |
| US6012121A (en) | Apparatus for flexible control of interrupts in multiprocessor systems | |
| CN114265800A (en) | Interrupt message processing method and device, electronic equipment and readable storage medium | |
| US6256660B1 (en) | Method and program product for allowing application programs to avoid unnecessary packet arrival interrupts | |
| CN104123252A (en) | Multi-channel direct memory access controller and control method thereof | |
| US7302548B1 (en) | System and method for communicating in a multi-processor environment | |
| US20230153153A1 (en) | Task processing method and apparatus | |
| CN111104119A (en) | MPI program conversion method and device for memory center type computer | |
| US11281609B2 (en) | Arithmetic processor and control method for arithmetic processor | |
| JP2739830B2 (en) | Data communication device for multiprocessor system | |
| CA2413712A1 (en) | Node-to-node data transfer method and node-to-node data transfer apparatus | |
| US11816049B2 (en) | Interrupt request signal conversion system and method, and computing device | |
| US12111779B2 (en) | Node identification allocation in a multi-tile system with multiple derivatives |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |