CN1074320A - Be used for the horizontal blanking of multiple rate scanning - Google Patents

Be used for the horizontal blanking of multiple rate scanning Download PDF

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Publication number
CN1074320A
CN1074320A CN92114368A CN92114368A CN1074320A CN 1074320 A CN1074320 A CN 1074320A CN 92114368 A CN92114368 A CN 92114368A CN 92114368 A CN92114368 A CN 92114368A CN 1074320 A CN1074320 A CN 1074320A
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China
Prior art keywords
signal
phase
timing signal
blanking
horizontal
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CN92114368A
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CN1040603C (en
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R·E·芬斯勒
W·特卢斯卡洛
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Technicolor USA Inc
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Thomson Consumer Electronics Inc
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Publication of CN1074320A publication Critical patent/CN1074320A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/24—Blanking circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)
  • Synchronizing For Television (AREA)

Abstract

In a horizontal deflection system, a nf HF in timing signal and the vision signal HHorizontal synchronization component synchronously produces, wherein nf HBe one and compare f HHigher frequency.First circuit is in response to nf HThe nf of timing signal for generating and this signal Synchronization HThe scan-synchronized signal.Horizontal deflection stage is with nf HWork and and nf HThe scan-synchronized signal response.Second circuit is in response to identical nf HThe timing signal for generating horizontal steady pulse that disappears.Nf HTiming signal can be produced by first phase-locked loop and frequency divider.First circuit can comprise second phase-locked loop.Second circuit can comprise drive(r) stage/phase inverter.Horizontal blanking impulse and vertical blanking pulse combination are to form a composite blanking signal.

Description

Be used for the horizontal blanking of multiple rate scanning
The present invention relates to be used for the field of the synchro system of TV and similar device, specially refer to generation the horizontal blanking signal of many sweep speeds operations.For example, with 2f HThe horizontal blanking signal that produces, f herein HIt is the horizontal frequency of a routine.
Suitable width and deflection/video is important obtaining one aspect the overlapping video signal regularly.With many times of line frequency (nf H) in the high end-receiver of work, and less overscanning occurs and be even more important.Compare with the 10%-12% overscanning that for the sweep speed of routine is, for multiple frequence scanning, over-scanning amount is about 5%-7%.Therefore, the accurate timing to horizontal blanking signal is very necessary.
Typically, horizontal blanking is to obtain the action of low-voltage pulse from the secondary winding of high pressure kickback transformer.A problem of this scheme is, the rise time of pulse can not be near being enough to eliminate fully by a video (signal) in more during the horizontal deflection current reversal that produces of high voltage pulse.In addition, unless strong differential is carried out in this pulse, expand then, otherwise the initial timing of blanking lags with regard to this actual needs so that pulse is sufficiently wide.Unfortunately, carry out strong differential and will produce other problem, promptly become when being high enough to trigger (blanking) circuit when flyback damped oscillation pulse, will present the situation of blanking circuit false triggering.
The known a kind of method of these problems that overcomes is to utilize two electric capacity that are arranged in the capacitor voltage divider circuit arrangement.This has just eliminated the problem of its vibration of secondary resistance, and provided the timing better than secondary winding method.But the problem of this method is to need a high-voltage capacitance in frequency divider at least.
Another method is to produce a blanking pulse from the timing signal before retrace interval, and this can realize by utilizing a pair of single one-shot multivibrator that triggers.Utilize a horizontal-drive signal to trigger this list and trigger first of one-shot multivibrator, just determine the almost initial delay of whole horizontal line.Utilize first single one-shot multivibrator output signal when this delay finishes that triggers to trigger second single one-shot multivibrator that triggers, just determine pulse duration, but, exist and single relevant problem of one-shot multivibrator that triggers, for example false triggering, this will produce wrong timing blanking.
Better solution according to a creative circuit arrangement is specially adapted to multirow synchronous circuit frequently, and this multirow synchronous circuit frequently has one with 1f HWork first phase-locked loop (PLL) and one with 2f HSecond phase-locked loop of work.Have this first and second phase-locked loops, and be used for a 32f HThe output of oscillator with 16 frequency divisions to obtain 2f HThe synchronous circuit of the circuit of signal at United States Patent (USP) NO.5, is described in 043,813, and this patent was announced on August 27th, 1991.And in european patent application 91104749.6, be described, this patent application is open on October 2nd, 1991, and its publication number is EP0449198A2.
First phase-locked loop comprises a nf HOscillator, for example 32f H, and synchronous with an incoming video signal.Second phase-locked loop and horizontal deflecting circuit are synchronous.Can be with a 32f H/ 16
The 1f that the form of frequency counter realizes HTo 2f HConverter circuit and 32f HOscillator response, and by the 1f of first phase-locked loop HOutput institute synchronously.Frequency divider provides a 36f for second phase-locked loop H/ 16(is 2f H) pumping signal, this is by using numeral 16 with 32f HCarry out repeatedly that frequency division realizes.The creative circuit arrangement that vibrates is from 32f HThe identical synchronizing signal that/16 frequency dividers obtain is for 2f HRed green orchid (RGB) drive(r) stage of work provides a timing signal source that is used for blanking.In addition, by providing divider ratio to be different from 16 digit expected to one of frequency counter prestrain, the phase place of blanking signal just becomes adjustable aspect increment.
Fig. 1 is the block diagram according to the horizontal-synchronizing circuit of a creative device and horizontal blanking generator, includes two phase-locked loops that are connected by a frequency converter.
Fig. 2 realizes being shown in Fig. 1 as 32f for being used for HThe digital circuit block diagram of the frequency converter of/16 frequency dividers.
Fig. 3 is the line map that is used to realize be shown in the horizontal blanking generator of Fig. 1.
Fig. 4 (a) and 4(b) be the timing diagram of comparing.Fig. 4 (a) is the resistance R among Fig. 3 5And R 6The signal at continuous point of contact place, Fig. 4 (b) then are the 214th row of Philips video and graphic (Philips video pattern).
Fig. 5 (a) and 5(b) be the timing diagram of comparing, Fig. 5 (a) is 2f HYoke current, and Fig. 5 (b) is the 214th row of Philips video and graphic.
Figure 1 illustrates the 2f that is used for that utilizes two phase-locked loops HA horizontal-synchronizing circuit of scanning.A monolithic processor 12 provides intermediate frequency (IF), video, colourity and deflection.Phase-locked loop 14 in monolithic processor is by will be from the 32f of voltage controlled oscillator 13 HClock signal is carried out 32 frequency divisions and is produced a 1f HOutput.Because phase-locked loop 14 makes this 1f HOutput is synchronous with the horizontal synchronization component of incoming video signal.Constitute a 1f HTo 2f H16 frequency dividing circuits 16 of frequency converter provide a 2f HOutput, this is by with 32f HCommon 16 frequency divisions realization is carried out in the output of oscillator.This 1f HOutput is used for synchronous 16 frequency dividing circuits.
32f by the frequency converter generation HThe phase place of/16 timing signals can be adjusted with respect to the synchronized component of incoming video signal.This is by a starting numeral is pre-loaded to a 32f HPulse descends the frequency division counting circuit 16 of frequency division to finish.This numeral can be provided by a microprocessor (not shown), so that control phase easily, for example in 2 microsecond steps.This phase-condition system is described among the european patent application NO.91104520.1, and this patent application is open on October 2nd, 1991, and publication number is EP0449130 A2.
This 32f H/ 16 timing signals make second phase-locked loop 18 synchronous with output deflection level 20.Phase-locked loop 18 is with 2f HWork also produces a 2f HThe scan-synchronized signal, its (phase-locked loop 18) and 32f H/ 16 timing signals are synchronous.Speed is 2f HThe flyback pulse of speed is coupled to a ramp generator 22 as input (signal).This ramp generator exchanges the flyback input that (AC) is coupled to second phase-locked loop 18 by capacitor C.Variable resistor 24 provides the fine setting of further phase place, from 0 to ± 2 microsecond for example, and this is to realize by the phase comparator in second phase-locked loop being changed slightly its direct current (DC) biasing.This 32f H/ 16 timing signals also provide an input (signal) to the horizontal blanking generator 17 that contains a phase inverter/driving circuit 19.
A digital circuit that is used to realize the circuit 16 of 16 frequency divisions is shown in Fig. 2.1f HAnd 32f HSignal is respectively by phase inverter 26 and 28 bufferings.1f through buffering HSignal is coupled to the D input of first D flip-flop 30.The Q output of trigger 30 then is the input of second D flip-flop 32 and another phase inverter 34.The Q output of trigger 32 and the output of phase inverter 34 then are and non-(NAND) door input of 36, load (LDN) input of the output control counting 38 of NAND gate 36 is in order to load starting, and this starting counting is from the signal on the bus that is connected to processor.In the drawings, the general expression of input title with " N " ending is a logic NOT input signal.
This postpones a 32f HAlso there is a 32f clock cycle HThe treated 1f of clock cycle width HRate signal, with bus data, μ PBUSO, μ PBUS1, μ PBUS2 and μ PBUS3 are loaded into counter 38.32f through phase inverter 28 bufferings HSignal then is trigger 30 and 32 and the input of the clock of counter 38.The Q of counter 38 0And Q 1Output is the input of NAND gate 40.The Q of counter 38 2And Q 3Output then is the input of NOR gate 42.The output of NAND gate 40 and NOR gate 42 is the input of NAND gate 44.The output signal of NAND gate 44 is 32f H/ 16 or 2f H, this signal excitation second phase-locked loop.32f H/ 16 or 2f HAnd the relative phase between the output of the timing signal of counter 38 is determined by the starting numeral that microcomputer loaded.According to shown in embodiment, this phase place can be expressed as with Boolean term (Boolean terms):
[（Q0·Q1）′·（Q 2+Q 3）′]′
Wherein: presentation logic " with "
+ presentation logic " or "
' presentation logic " non-" or signals reverse.
Wherein the most effective position is Q 0, and counter counts down, and the output of NAND gate 44 corresponds respectively at binary number 0000,0100 or 1100(+system several 0,4 or 12) Shi Weizhen (low).Therefore, this circuit is to 32f HEight (between 12 to 5, being between 1100 to 0101 in the=system promptly) in the clock cycle one of work provides phase change.Concerning shown in embodiment, required phase change is little.Utilizing a gate means (for example replacing NAND gate 40 from 15 to 0 countings with a NOR gate) also is possible with 16 cycles that obtain phase change.Usually, necessary phase changing capacity is that blanking pulse of generation is desired, and this blanking pulse may be more early wideer than other, and from just tracking exactly of scanning beginning.
Output 32f H/ 16, or 2f HAnd the lock-out pulse of timing signal can be loaded into data on the counter 38 by change, moves through 1f with the step of 2 microseconds HVideo cycle.Output 2f HLock-out pulse is an active low TTL(transistor-transistor logic) level pulse, 6 microseconds are wide.32f H/ 16 lock-out pulses and the 2f that draws H2f is determined on the flyback slope HScanning is with respect to the 1f of input HVideo (signal) phase place, this is by suitable Digital Signal Processing, with 2f HRate calculations is come out.Therefore, on picture tube, make 2f HVideo (signal) and 2f HScanning (signal) is synchronous.The fine setting phase control of 0 to ± 2 microsecond can obtain by the direct current biasing that changes phase comparator slightly, at the phase comparator place, its slope as explained above be AC coupled.The fine setting phase control can be by changing the slope slope or introduce a little variable resistor that is in series with ramp generator electric capacity and realize.
Because 32f HIt is wide that/16 signal pulses when empty are about 6 microseconds, and a typical 2f HRetrace interval is 5.7 microseconds, then just can be from 32f from the integer flyback pulse that produces the slope HThe forward position of/16 timing signal pulses postpones about 200 microseconds forward.Horizontal blanking will begin too lately.If horizontal blanking is from 32f HThis identical pulse of/16 timing signals triggers, and then according to the present invention, it will start at the last slightly point of retrace interval, and this retrace interval is wideer slightly, and therefore correct blanking timing and width just be provided.
The timing diagram of comparing of Fig. 4 and Fig. 5 shows 32f HHow/16 timing signal pulses are used to produce a blanking signal.Fig. 4 (a) shows the resistance R 5 among Fig. 3 and the signal at R6 point of contact place, and Fig. 4 (b) shows the 214th row of Philips video and graphic.The black-out intervals of Fig. 4 (a) began before need be by the video signal portions of blanking just as can be seen, and stopped before the effective video signal of blanking as next line.Fig. 5 (a) shows 2f HYoke current, and Fig. 5 (b) shows identical the 214th row of Philips video and graphic demonstrates how they exactly to fall in black-out intervals.
Must be noted that to reduce to minimum to the waiting time effect, and guarantee that blanking pulse finished and not blanking effective video signal in the suitable time if horizontal blanking generator 17 uses an outside inverter transistor.According to a creative method, a suitable circuit 19 that is used for blanking circuit as paraphase and drive(r) stage is shown in Fig. 3.Phase inverter/drive(r) stage comprises transistor Q 132f H/ 16 timing signals pass through capacitor C 1Be ac-coupled to phase inverter.Resistance R 1, R 2And R 3Provide sufficiently high impedance, to stop any effective signal loading.Diode CR1 oxide-semiconductor control transistors Q 1Full closing, so that waiting time and output width are reduced to minimum.Select resistance R 4The clip level on edge after the control impuls, and capacitor C 2Then provide a fixing forward position to start fast.Transistor Q 1Slope on the emitter is to produce during closing breakpoint in pulse and lower clip level, is therefore keeping suitable blanking width.
Resistance R 5And R 6Form a voltage divider to provide to buffer transistor Q 2Connection, Q 2Then be set to one and penetrate a grade follower.Level and vertical blanking signal are at point of contact (that is the transistor Q of diode CR2 and CR3 2Base stage) locate to make up.Transistor Q 2Output be a composite blanking signal.
Therefore, in case set up slowed-down video through the Video processing passage, and the direct current biasing by the numerical data (from microprocessor or connect firmly cross-line) and second phase-locked loop gives set with phase place, then blanking just along with vision signal by suitably regularly.

Claims (16)

1, a kind of equipment, it contains:
First phase-locked loop (14) is with f HWork is also synchronous by the horizontal synchronization component of vision signal;
A f HTo nf HFrequency converter (16) is used for obtaining a nf from the output (signal) of described first phase-locked loop (14) HTiming signal, n is an integer herein; And
Second phase-locked loop (18) is with described nf HTiming signal is synchronous, is used to nf HThe deflection level (20) of work produces a nf HThe scan-synchronized signal;
It is characterized in that:
Device (17) is in response to described nf HTiming signal also can be worked, to produce a blanking signal that is used for retouching in the horizontal flyback sweep of described deflection level a cut-off beam.
2, equipment according to claim 1 is characterized in that a mf HOscillator (13) forms the part of first phase-locked loop (14), and with one of its output (32f H) offering can be in response to the f of this output HTo nf HFrequency converter, m is the integral multiple of a n herein.
3, equipment according to claim 2 is characterized in that m equals 32 and n equals 2.
4, equipment according to claim 1 is characterized in that n equals 2.
5, equipment according to claim 1, wherein said f HTo nf HFrequency converter (16) is characterised in that with a counter (38) and removes clock signal (32f H), described horizontal blanking signal has the pulse by the determined width of integral multiple cycle of this clock signal.
6, equipment according to claim 1, its feature also is: device (CR2, CR3, Q 2) be used for described horizontal blanking signal and vertical blanking signal are made up to draw a composite blanking signal.
7, horizontal blanking signal generator has:
One first phase-locked loop (14) is f with having frequency HThe vision signal of horizontal synchronization component link to each other, and include according to mf HSignal produces the oscillator (13) of a signal;
A frequency divider (16) is used for by removing this mf HSignal and with mf HSignal transformation is a nf HTiming signal;
One second phase-locked loop (18) is with described nf HTiming signal is synchronous, is used to nf HThe deflection level (20) of work produces a nf HThe scan-synchronized signal; And
The device (μ PBUS), be used for to frequency divider (16) provide continuously be chosen as control described nf HTiming signal and mf HThe starting numeral of signal phase relation;
It is characterized in that:
Device (17) is in response to described 2f HTiming signal is to produce the video signal level blanking pulse.
8, signal generator according to claim 7, its feature also are to revise nf with one of phase place and pulse duration at least HTiming signal.
9, signal generator according to claim 7 is characterized in that n equals 2.
10, signal generator according to claim 7, it is characterized in that m equal 32 and n equal 2.
11, a kind of horizontal deflection system comprises:
Device (14,16) is used for producing the f with a vision signal HThe nf that horizontal synchronization component is synchronous HTiming signal, wherein nf HBe one than f HHigher frequency;
First device (18) is in response to this nf HTiming signal is to produce one and this nf HThe nf that timing signal is synchronous HThe scan-synchronized signal; And
A horizontal deflection stage (20) is with nf HWork and in response to nf HThe scan-synchronized signal;
It is characterized in that:
Second device (17) is in response to this nf HTiming signal is to produce horizontal blanking impulse.
12, system according to claim 11, its feature also are device (CR2, CR3, Q 2) be used for described horizontal blanking impulse and vertical blanking pulse are made up to obtain a composite blanking signal.
13, system according to claim 11 wherein saidly is used to produce nf HThe device of timing signal is characterised in that: it comprises one first phase-locked loop (14) and a frequency divider (16).
14, system according to claim 13 is wherein in response to described nf HTiming signal is to produce nf HFirst device of scan-synchronized signal is characterised in that and comprises one second phase-locked loop (18).
15, system according to claim 11 wherein is used to produce described nf HThe device of timing signal is characterised in that:
Device (13) is used for mf HProduce clock signal, a mf herein HBe one and compare nf HHigher frequency, and
Device (38) is used for this mf HClock signal is cut apart (removing) to produce described nf HTiming signal.
16, system according to claim 11, wherein said in response to nf HSecond device of timing signal is characterised in that and comprises a drive(r) stage/phase inverter (19).
CN92114368A 1991-12-13 1992-12-12 Horizontal blanking for multiple rate scanning Expired - Fee Related CN1040603C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB919126550A GB9126550D0 (en) 1991-12-13 1991-12-13 Improved horizontal blanking
GB9126550.4 1991-12-13

Publications (2)

Publication Number Publication Date
CN1074320A true CN1074320A (en) 1993-07-14
CN1040603C CN1040603C (en) 1998-11-04

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CN92114368A Expired - Fee Related CN1040603C (en) 1991-12-13 1992-12-12 Horizontal blanking for multiple rate scanning

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JP (1) JP3464497B2 (en)
KR (1) KR100256160B1 (en)
CN (1) CN1040603C (en)
DE (1) DE4240876A1 (en)
GB (2) GB9126550D0 (en)
MY (1) MY110315A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100490051C (en) * 1995-08-03 2009-05-20 株式会社日立等离子体专利许可 Plasma display panel and driving method and plasma display equipment
CN101887697B (en) * 2009-05-11 2012-12-12 联咏科技股份有限公司 Method for reducing resonance energy of liquid crystal display panel and liquid crystal display

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6169581B1 (en) * 1994-04-01 2001-01-02 Honeywell Inc. Phase-locked sync stripper
DE10202967A1 (en) * 2002-01-26 2003-07-31 Philips Intellectual Property Circuit arrangement and method for generating the control signal of the deflection transistor of a cathode ray tube

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100490051C (en) * 1995-08-03 2009-05-20 株式会社日立等离子体专利许可 Plasma display panel and driving method and plasma display equipment
CN101887697B (en) * 2009-05-11 2012-12-12 联咏科技股份有限公司 Method for reducing resonance energy of liquid crystal display panel and liquid crystal display

Also Published As

Publication number Publication date
KR100256160B1 (en) 2000-05-15
DE4240876A1 (en) 1993-06-17
GB9225326D0 (en) 1993-01-27
GB2262408A (en) 1993-06-16
JP3464497B2 (en) 2003-11-10
GB2262408B (en) 1995-08-02
MY110315A (en) 1998-04-30
JPH05308539A (en) 1993-11-19
GB9126550D0 (en) 1992-02-12
CN1040603C (en) 1998-11-04
KR930015670A (en) 1993-07-24

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