CN107402830B - Register abnormality detection device - Google Patents
Register abnormality detection device Download PDFInfo
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- CN107402830B CN107402830B CN201710272530.5A CN201710272530A CN107402830B CN 107402830 B CN107402830 B CN 107402830B CN 201710272530 A CN201710272530 A CN 201710272530A CN 107402830 B CN107402830 B CN 107402830B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
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- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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Abstract
The register abnormality detection device of the present invention can improve the reliability of abnormality detection without using a CPU of high processing capability. In an IC (2), after calculating a CRC expected value of data written in a register (2A), a CRC current value is repeatedly calculated, and the calculated CRC current value is updated and stored in a CRC current value storage unit (2E). Every time the CRC current value is calculated, the coincidence/non-coincidence between the CRC expected value and the CRC current value is judged once, and the judgment result is written into an error detection register (2H). A CPU (1) periodically reads out the determination result written in the error detection register (2H) and the CRC status value stored in a CRC status value storage unit (2E), and detects an abnormality of the data written in the register (2A) based on the read-out determination result (1 st determination result) and the determination result (2 nd determination result) obtained by using the CRC status value.
Description
Technical Field
The present invention relates to a register abnormality detection device that detects an abnormality in data written in a register.
Background
In an electronic Circuit that performs various kinds of Processing using a microcomputer, data sent from a CPU (Central Processing Unit) is written into a register inside an IC (Integrated Circuit). In the electronic circuit using the microcomputer, data (register value) written in a register in the IC may be accidentally rewritten due to noise or the like.
Therefore, conventionally, the following processes (1) and (2) are performed on the CPU side.
(1) In the case where the register value is changed although the register value is not written, it is determined that an abnormality has occurred in the register value (data written in the register), and an accurate value is written.
(2) After the initial setting of the register, the same value as that at the initial setting is continuously written at a constant interval. Thus, even if the register value changes due to the influence of noise or the like, the register value is overwritten with the correct value.
[ Prior art documents ]
[ non-patent literature ]
Non-patent document 1 discloses "24-bit sigma-delta ADC-Analog Devices for 20 μ s stable 250 kSPS" (20 μ s セトリング,24 ビット sigma-delta ADC-Analog Devices for 250 kSPS) [ search 4/5/2016 ], website < URL: http:// www.analog.com/media/jp/technical-documentation/data-sheets/AD7176-2_ jp. pdf # search ═ 20 +% CE% BCs% E3% 82% BB% E3% 83% 88% E3% 83% AA% E3% 83% B3% E3% 82% B0% E3% 80% 81250+ kSPS% E3% 81% AE' >
[ non-patent document 2 ] 8-Channel, Low No ise, Low Power,24-Bit, Sigma-Delta ADC with PGA and Reference ", [ 2016 search 4/5/2016 ], URL: http:// www.analog.com/media/en/technical-documentation/data-sheets/AD7124-8.pdf # search ═ 8 Channel% 2C + Low + "No" ise% 2C + Low + Power% 2C +24 Bit% 2C' >, and
disclosure of Invention
[ problem to be solved by the invention ]
However, in order to perform the processes (1) and (2) on the CPU side, a CPU having a high processing capability must be selected. In addition, in order to check an abnormality of data written in the register (register abnormality), access from the CPU to the IC increases, which causes an increase in power consumption.
Further, there is an example in which the following configurations (3) and (4) are incorporated on the IC side, not the CPU side (for example, refer to non-patent documents 1 and 2).
(3) 2 registers are prepared, one register is used as an operation setting register, and the other register is used as an expected value storage register. The same value as that written from the CPU to the operation setting register is also copied to the expected value storage register. When the value written in the operation setting register is different from the value written in the expected value storage register even though the writing from the CPU to the operation setting register does not occur, the error detection register is used to notify the CPU of the register abnormality.
(4) When a CRC (Cyclic Redundancy Code) value of data written in a register is repeatedly calculated and the calculated CRC value (current CRC value) does not match an expected value (expected CRC value) although no writing is performed from a CPU to the register, an error detection register is used to notify the CPU of a register abnormality. The CRC value is one of indexes for checking for detecting an abnormality of data written in a register, and is defined as a remainder (remainder) obtained by dividing data by a constant, taking the data as a value. The CRC expected value is a CRC value defined as a value that the data written in the register originally should have.
However, in the configuration of the above (3), the register of 2 times the normal register is used, and thus, the configuration is disadvantageous in terms of area. In the configuration of (4), although the number of registers required for abnormality detection can be reduced, there is a possibility that erroneous detection may be performed when an abnormality such as a garbled code occurs in a bit of the error detection register itself. That is, there is a case where the error detection register itself is abnormal, and it is determined to be abnormal although it is normal. Conversely, there is a case where the determination is normal despite being abnormal.
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a register abnormality detection device capable of improving the reliability of abnormality detection without using a CPU having a high processing capability.
[ MEANS FOR SOLVING PROBLEMS ] A method for producing a semiconductor device
In order to achieve the above object, the present invention provides a register abnormality detection device (100) including an arithmetic processing unit (1) and a register (2A) into which data sent from the arithmetic processing unit (1) is written, the register abnormality detection device (100) detecting an abnormality of the data written in the register (2A), the register abnormality detection device (100) comprising: a data writing unit (2B) that writes the data sent from the arithmetic processing unit (1) into the register (2A); an expected value calculation unit (2C) that calculates an expected value of an index for inspection that detects an abnormality in the data written in the register (2A); a current value calculation unit (2D) that repeatedly calculates a current value corresponding to an expected value of the check index of the data written in the register (2A); a current value storage unit (2E) for updating and storing the current value of the index for inspection calculated by the current value calculation unit (2D) each time; and a coincidence/non-coincidence determination unit (2G) that, each time the current value of the inspection index is calculated by the current value calculation unit (2D), determines coincidence/non-coincidence between the calculated current value of the inspection index and the expected value, writes the determination result as a 1 st determination result into the error detection register (2H), and reads out at least one of the 1 st determination result written into the error detection register (2H) and the current value of the inspection index stored in the current value storage unit (2E) by the arithmetic processing unit (1).
In the present invention, when data sent from an arithmetic processing unit (1) is written into a register (2A), an expected value (CRC expected value) of a check index for detecting an abnormality in the data written into the register (2A) is calculated. Then, after the expected value of the check index is calculated, the current value (CRC current value) corresponding to the expected value of the check index of the data written in the register (2A) is repeatedly calculated, and the calculated current value of the check index is updated and stored (overwritten) in a current value storage unit (2E). Further, every time the calculation of the current value of the check index is repeated, the match/mismatch between the calculated current value of the check index and the expected value is determined, and the determination result is written as the 1 st determination result into the error detection register (2H).
The arithmetic processing unit (1) detects an abnormality of the data written in the register (2A) based on the 1 st determination result written in the error detection register (2H) and the 2 nd determination result obtained by using the current value of the inspection index stored in the current value storage unit (2E). For example, when the 1 st determination result is "match" and the 2 nd determination result is also "match", the data written in the register (2A) is determined to be normal, and otherwise, it is determined to be abnormal.
In the present invention, an arithmetic processing unit (1) reads at least one of the 1 st determination result written in an error detection register (2H) and the current value of the inspection index stored in a current value storage unit (2E). Thus, for example, the 2 nd determination result can be obtained using the current value of the check index stored in the current value storage unit (2E), and the abnormality of the data written in the register (2A) can be detected from the 2 nd determination result obtained using the current value of the check index and the 1 st determination result written in the error detection register (2H).
In this case, the 2 nd determination result is obtained using the current value of the inspection index read out from the current value storage unit (2E), for example, the current value of the inspection index stored in the current value storage unit (2E) is periodically read out, the first current value of the inspection index read out from the current value storage unit (2E) is used as the expected value on the arithmetic processing unit (1) side, and then, every time the current value of the inspection index is read out from the current value storage unit (2E), the coincidence/non-coincidence between the read current value of the inspection index and the expected value on the arithmetic processing unit (1) side is determined, and the determination result is used as the 2 nd determination result.
In this case, although the abnormality of the data written in the register (2A) is detected based on the 1 st and 2 nd determination results, the abnormality of the data written in the register (2A) may be detected only by the 1 st determination result, and the abnormality of the data written in the register (2A) may be detected only by the 2 nd determination result. For example, the 1 st, 2 nd, and 3 rd modes may be selected as the mode of detecting an abnormality of the register, and when the 1 st mode is selected, an abnormality is detected using only the 1 st determination result, when the 2 nd mode is selected, an abnormality is detected using only the 2 nd determination result, and when the 3 rd mode is selected, an abnormality is detected based on the 1 st determination result and the 2 nd determination result.
In the present invention, the 1 st determination result written in the error detection register (2H) may be periodically read by the arithmetic processing unit (1), or may be included in a response byte accessed by an SPI (Serial Peripheral Interface) with a checksum, or the like, and transmitted to the arithmetic processing unit (1) in a communication protocol.
In the above description, the components on the drawings corresponding to the components of the invention are indicated by bracketed reference numerals, as an example.
[ Effect of the invention ]
According to the present invention, since at least one of the 1 st determination result written in the error detection register and the current value of the check index stored in the current value storage unit is read, for example, the 2 nd determination result is obtained using the current value of the check index stored in the current value storage unit, and an abnormality or the like of data written in the register is detected based on the 2 nd determination result obtained using the current value of the check index and the 1 st determination result written in the error detection register, whereby the reliability of abnormality detection can be improved without using a CPU having a high processing capability.
Drawings
Fig. 1 is a diagram showing a configuration of essential parts of a register abnormality detection device according to an embodiment of the present invention.
Fig. 2 is a state machine diagram of the inside of the CRC value calculation section in the register abnormality detection apparatus.
Fig. 3 is a timing chart showing an operation performed by the CRC value calculation unit.
Fig. 4 is a diagram in which the IC-side processing function is blocked.
Fig. 5 is a flowchart showing the IC-side processing.
Fig. 6 is a flowchart showing the CPU-side processing.
Fig. 7 is a flowchart showing a process performed on the CPU side in the case where the 1 st mode is selected.
Fig. 8 is a flowchart showing processing performed on the CPU side in the case where the 2 nd embodiment is selected.
Fig. 9 is a diagram showing an example in which the value of the error detection register is included in the response byte of the SPI access with checksum.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Fig. 1 is a diagram showing a configuration of essential parts of a register abnormality detection apparatus 100 according to an embodiment of the present invention.
In fig. 1, 1 denotes a CPU (arithmetic processing unit) and 2 denotes an IC. The IC2 is provided with a data receiving circuit 21, a command control unit 22, a data transmitting circuit 23, and an internal register 24. The internal register 24 is provided with a CRC value calculation target register 24-1, a CRC value calculation non-target register 24-2, a CRC value calculation unit 24-3, and an error detection register 24-4.
In the register abnormality detection apparatus 100, data sent from the CPU1 is received by the data reception circuit 21, subjected to serial-parallel conversion, sent to the internal register 24 via the command control section 22, and written into the CRC value calculation target register 24-1.
In the internal register 24, the CRC value calculation section 24-3 calculates a CRC expected value and a CRC present value of the data written in the CRC value calculation target register 24-1, determines whether the calculated CRC present value matches or does not match the CRC expected value, and writes the determination result to the error detection register 24-4.
The current CRC value calculated by the CRC value calculation unit 24-3 is written to the CRC value calculation non-target register 24-2. The CPU1 periodically reads the CRC value to calculate the CRC present value written in the non-target register 24-2 and the determination result written in the error detection register 24-4.
In fig. 1, CS is a chip select signal, SCLK is a serial clock signal, MISO (Master In Slave Out) is a Master In Slave Out signal, MOSI (Master Output Slave Input) is a Master Out Slave In signal, and REG _ ERR _ DET is an abnormal detection state (determination result) read from the error detection register 24-4.
Fig. 2 shows a state machine diagram of the inside of the CRC value calculation section 24-3. When the CRC calculation enable is valid, the CRC value calculation unit 24-3 repeatedly calculates the current CRC value (current CRC value) of the data written in the CRC value calculation target register 24-1 (state S1), repeatedly compares the calculated CRC value with the CRC expected value (state S2), and when a CRC expected value calculation command is received from the CPU1, starts calculating the CRC expected value (state S3). When the calculation of the CRC expected value is completed, the value of the error detection register 24-4 is cleared and set to "0" (state S4), and the CRC present value is repeatedly calculated (state S1).
When the value of the data written in the CRC value calculation target register 24-1 is rewritten due to an abnormality such as noise during repetition of the calculation of the CRC current value and the CRC expected value does not match, the CRC value calculation unit 24-3 sets "1" to the value of the error detection register 24-4.
As is clear from this state machine diagram, the CRC value calculation unit 24-3 determines whether the calculated CRC present value matches or does not match the CRC expected value every time the calculation of the CRC present value is repeated, and writes the determination result in the error detection register 24-4.
In the present embodiment, the value of the error detection register 24-4 is initially set to "0", and when there is a mismatch between the CRC present value and the CRC expected value, the value of the error detection register 24-4 is rewritten to "1". That is, when the determination result of the coincidence/non-coincidence between the CRC present value and the CRC expected value is "coincidence", the value (abnormality detection state) of the error detection register 24-4 is set to "0", and when "non-coincidence", it is set to "1". In the case of "coincidence", the value of the error detection register 24-4 is not rewritten, but it can be said that "0" is written in terms of the result.
In fig. 2, "IDLE" indicates an initial state (state S0), "CALC" indicates a state in which the CRC present value is calculated (state S1), "RESULT" indicates a state in which the CRC present value is compared with the CRC expected value (state S2), "REF _ CALC" indicates a state in which the CRC expected value is calculated (state S3), and "REF _ RESULT" indicates a state in which the abnormality detection state is cleared (state S4).
In fig. 2, the CRC value is repeatedly calculated in the state S1, and the CRC value calculation non-target register 24-2 is updated and stored (overwritten) every time the CRC value is calculated. In the state S3, the CRC expected value is calculated, and the calculated value is obtained 1 time by the CRC expected value calculation command and stored in the memory in the CRC value calculation unit 24-3.
In fig. 1, the CPU1 periodically reads out the determination result and the CRC value written in the error detection register 24-4 to calculate the CRC present value stored in the non-target register 24-2. Then, an abnormality of the data written in the CRC value calculation target register 24-1 is detected from the read determination result (1 st determination result) and the determination result (2 nd determination result) obtained using the CRC present value. For example, if the 1 st determination result is "match" and the 2 nd determination result is also "match", the data written in the CRC value calculation target register 24-1 is determined to be normal, and otherwise, it is determined to be abnormal.
In the present embodiment, the CRC value that the CPU1 can read from the IC2 is only the current CRC value. That is, the CPU1 should obtain the determination result of the match/mismatch between the CRC expected value of the data written in the CRC value calculation target register 24-1 and the CRC present value read out from the IC2 as the determination result (the 2 nd determination result) obtained using the CRC present value, but the CRC expected value calculated by the CRC value calculation unit 24-3 cannot be read out.
In this case, the CPU1 may obtain the CRC expected value of the data written in the CRC value calculation target register 24-1, but the processing load of the CPU1 increases. Therefore, in the present embodiment, the first CRC present value read from the CRC value calculation non-target register 24-2 (the first CRC present value after issuance of the CRC expected value calculation command) is set as the CRC expected value on the CPU1 side in the CPU1, and then, every time the CRC present value is read from the CRC value calculation non-target register 24-2, the correspondence/non-correspondence between the read CRC present value and the CRC expected value on the CPU1 side is determined, and the determination result is used as the determination result (the 2 nd determination result) obtained using the CRC present value.
Fig. 3 is a timing chart showing the operation performed by the CRC value calculation unit 24-3. In this figure, (a) to (h) are input/output signals of the CRC value calculation section 24-3, and (i) and (j) are internal signals of the CRC value calculation section 24-3.
When the CRC value calculation unit 24-3 receives the CRC expected value calculation command from the CPU1 (point t1 shown in fig. 3 (c)), the calculation of the CRC expected value is started (point t1 shown in fig. 3 (j)). Then, when the calculation of the CRC expected value is finished (points t2 to t3 shown in fig. 3 (j)), the values of the error detection register 24-4 are cleared (points t2 to t3 shown in fig. 3 (f)), and the calculation of the CRC present value is started (point t3 shown in fig. 3 (j)).
The CRC value calculation unit 24-3 compares the current CRC value with the expected CRC value every time the current CRC value is calculated, and when it is confirmed that the calculated current CRC value does not match the expected CRC value (points t4 to t5 shown in fig. 3 (j)), the value (abnormality detection state) of the error detection register 24-4 is set to "1" (points t4 to t5 shown in fig. 3 (g)).
In the processing operation performed by the CRC value calculation unit 24-3, the time (CRC expected value calculation period) TA required for calculating the CRC expected value is the same as the time (CRC present value calculation period) TB required for calculating the CRC present value. For example, when the CRC value calculation target register 24-1 is 60 bytes and CRC calculation is performed 1 byte at a time, the time required for CRC calculation is 60 cycles.
Fig. 4 is a block diagram of the processing function on the IC2 side. The IC2 includes a register 2A, a data write unit 2B, CRC expected value calculation unit 2C, CRC current value calculation unit 2D, CRC current value storage unit 2E, CRC expected value storage unit 2F, a match/mismatch determination unit 2G, and an error detection register 2H.
In this functional block diagram, the register 2A corresponds to the CRC value calculation target register 24-1, the CRC present value storage section 2E corresponds to the CRC value calculation non-target register 24-2, and the error detection register 2H corresponds to the error detection register 24-4 in fig. 1. The CRC expected value calculation unit 2C, CRC the current state value calculation unit 2D, CRC expected value storage unit 2F and the coincidence/non-coincidence determination unit 2G correspond to the processing functions in the CRC value calculation unit 24-3.
In the functional block diagram, the CRC expected value calculation unit 2C and the CRC present value calculation unit 2D are shown as being divided into 2 parts to distinguish the processing functions, but are not present as separate circuits in hardware, and are provided as a common circuit (the same circuit). That is, in the shared circuit, the CRC value calculated after receiving the CRC expected value calculation command is determined to be a CRC expected value and stored in the CRC expected value storage section 2F, and the CRC value calculated in a time other than this is stored in the CRC present value storage section 2E as a CRC present value. That is, since the generation of the CRC expected value and the generation of the CRC present value are calculated by the same calculation formula, it is not necessary to have different circuits. If the CRC expected value and the CRC present value are calculated at the same time, it is necessary to prepare different circuits, but in this example, the calculation of the CRC expected value and the CRC present value is performed exclusively. Of course, although the CRC expected value and the present CRC value may be repeated, a circuit for calculating the expected CRC value and the present CRC value may be prepared as different circuits.
In the IC2, the data writing unit 2B receives a register write command (data + command) from the CPU1, and writes data from the CPU1 into the register 2A. The CRC expected value calculation unit 2C receives a CRC expected value calculation command from the CPU1, and calculates a CRC expected value of the data written in the register 2A. The CRC expected value storage section 2F stores the CRC expected value calculated by the CRC expected value calculation section 2C.
After the CRC expected value is calculated by the CRC expected value calculation unit 2C, the CRC present value calculation unit 2D repeatedly calculates a CRC present value corresponding to the CRC expected value of the data written in the register 2A. The CRC present value storage section 2E updates and stores the calculated CRC present value every time the CRC present value is calculated by the CRC present value calculation section 2D.
Every time the CRC present value is calculated by the CRC present value calculation unit 2D, the match/mismatch determination unit 2G determines match/mismatch between the calculated CRC present value and the CRC expected value, and writes the determination result ("0"/"1") as the 1 st determination result into the error detection register 2H. Further, the value written in the error detection register 2H is cleared each time the calculation of the CRC expected value in the CRC expected value calculation section 2C is completed.
Fig. 5 is a flowchart showing the process on the IC2 side. When the data writing unit 2B receives a register write command from the CPU1 (yes in step S101), data is written into the register 2A (step S102). When the CRC expected value calculation unit 2C receives a CRC expected value calculation command from the CPU1 after the issuance of the register write command (yes in step S103), it calculates a CRC expected value (step S104). After the calculation of the CRC expected value, the value of the error detection register 2H is cleared (step S105).
When the calculation of the CRC expected value by the CRC expected value calculation unit 2C is completed, the CRC present value calculation unit 2D starts the calculation of the CRC present value (step S106). When the calculation of the CRC present value by the CRC present value calculation unit 2D is completed, the matching/mismatching determination unit 2G determines matching/mismatching between the calculated CRC present value and the CRC expected value calculated by the CRC expected value calculation unit 2C (step S107).
The match/mismatch determination unit 2G repeats the determination of match/mismatch in the match/mismatch determination unit 2G every time the CRC current value is calculated by the CRC current value calculation unit 2D (the repetition of step S101 → S106 → S107), and when a determination result of "mismatch" is obtained in the repetition of the calculation of the CRC current value, the match/mismatch determination unit 2G sets the value of the error detection register 2H to "1" (step S108).
Fig. 6 is a flowchart showing the processing on the CPU1 side. After releasing the reset of IC2 (step S201), CPU1 checks whether or not a register write command has been issued to IC2 (step S202). When the issuance of the register write command to IC2 is confirmed (yes in step S202), the CRC expected value calculation command is issued to IC2 (step S203).
Then, the CPU1 waits for completion of the calculation of the CRC value in the IC2 (step S204), reads out the CRC present value stored in the CRC present value storage section 2E (the first CRC present value after the issuance of the CRC expected value calculation command), and stores the read-out CRC present value as the CRC expected value on the CPU1 side (step S205).
Then, the CPU1 reads out the determination result (1 st determination result) written in the error detection register 2H and the CRC present value stored in the CRC present value storage section 2E (step S206), and when the determination result (1 st determination result) read out from the error detection register 2H is "0" and the CRC value read out from the CRC present value storage section 2E matches the CRC expected value on the CPU1 side stored in step S205 (the 2 nd determination result is "0") (yes "in step S207), that is, when the 1 st determination result is" match "and the 2 nd determination result is also" match ", determines that the data written in the register 2A is normal, and returns to step S202.
When the CPU1 issues the register write command to the IC 21 time, the processing of steps S202, S206, 207 is repeated until the next register write command is issued. If the 1 st determination result is "match" and the 2 nd determination result is also "match" are not obtained in the repetition of the processing of steps S202, S206, and S207 (no in step S207), that is, if at least one of the 1 st determination result and the 2 nd determination result is "mismatch", the CPU1 determines that an abnormality has occurred in the data written in the register 2A and performs an abnormality processing (step S208). The content of the exception processing in step S208 is determined to be appropriate for each system.
As described above, according to the register abnormality detection apparatus 100 of the present embodiment, when both the determination result (1 st determination result) on the IC2 side and the determination result (2 nd determination result) on the CPU1 side are "matched", the data written in the register 2A is determined to be normal, and otherwise, it is determined to be abnormal. Thus, the reliability of abnormality detection can be improved without using a CPU of high processing capability as the CPU 1.
Although the description is omitted above, the register abnormality detection apparatus 100 can select whether to detect an abnormality of data written in the register 2A based on the 1 st determination result on the IC2 side and the 2 nd determination result on the CPU1 side, to detect an abnormality of data written in the register 2A based on only the 1 st determination result on the IC2 side, or to detect an abnormality of data written in the register 2A based on only the 2 nd determination result on the CPU1 side.
In this case, when the 1 st mode is selected as the abnormality detection mode of the register, the CPU1 detects an abnormality of the data written in the register 2A only by the 1 st determination result on the IC2 side, when the 2 nd mode is selected, the CPU1 detects an abnormality of the data written in the register 2A only by the 2 nd determination result on the CPU1 side, and when the 3 rd mode is selected, the CPU1 detects an abnormality of the data written in the register 2A from the 1 st determination result on the IC2 side and the 2 nd determination result on the CPU1 side.
Fig. 7 is a flowchart showing a process performed on the CPU1 side when the 1 st mode is selected. In this case, after releasing the reset of IC2 (step S301), CPU1 checks whether or not a register write command has been issued to IC2 (step S302). When the issuance of the register write command to IC2 is confirmed (yes in step S302), the CRC expected value calculation command is issued to IC2 (step S303).
Then, the CPU1 waits for the completion of the calculation of the CRC value in the IC2 (step S304), reads out the determination result (1 st determination result) written in the error detection register 2H (step S305), and when the determination result (1 st determination result) read out from the error detection register 2H is not "1" (no in step S306), that is, when the 1 st determination result is "0", determines that the data written in the register 2A is normal, and returns to step S302.
When the CPU1 issues the register write command to the IC 21 time, the processing of steps S302, S305, S306 is repeated until the next register write command is issued. If the 1 st determination result is "1" in the repetition of the processing of steps S302, S305, and S306 (yes in step S306), that is, if the 1 st determination result is "mismatch", the CPU1 determines that an abnormality has occurred in the data written in the register 2A and performs an abnormality processing (step S307). The contents of the exception processing in step S307 are determined to be appropriate for each system.
Fig. 8 is a flowchart showing processing operations performed on the CPU1 side when the 2 nd embodiment is selected. In this case, after releasing the reset of IC2 (step S401), CPU1 checks whether or not a register write command has been issued to IC2 (step S402). When the issuance of the register write command to IC2 is confirmed (yes in step S402), the CRC expected value calculation command is issued to IC2 (step S403).
Then, the CPU1 waits for completion of the calculation of the CRC value in the IC2 (step S404), reads out the CRC present value stored in the CRC present value storage section 2E (the first CRC present value after the issuance of the CRC expected value calculation command), and stores the read-out CRC present value as the CRC expected value on the CPU1 side (step S405).
Then, the CPU1 reads out the CRC present value stored in the CRC present value storage section 2E (step S406), and when the CRC present value read out from the CRC present value storage section 2E matches the CRC expected value on the CPU1 side stored in step S405 (yes in step S407), that is, when the 2 nd determination result is "match", determines that the data written in the register 2A is normal, and returns to step S402.
When the CPU1 issues the register write command to the IC 21 time, the processing of steps S402, S406, S407 is repeated until the next register write command is issued. If the result of "match" in the 2 nd determination result is not obtained in the repetition of the processing in steps S402, S406, and S407 (no in step S407), that is, if the result of "mismatch" in the 2 nd determination result is obtained, the CPU1 determines that an abnormality has occurred in the data written in the register 2A and performs an abnormality processing (step S408). The content of the exception processing in step S408 is determined to be appropriate for each system.
When the 3 rd embodiment is selected, the processing described with reference to fig. 6 is performed. Further, the configuration of the 1 st, 2 nd, and 3 rd aspects is not necessarily required, and the 3 rd aspect may be adopted alone. In the present embodiment, the CPU1 reads out at least one of the abnormality detection state and the CRC present value from the IC2, but how the read-out abnormality detection state and CRC present value are used is determined by the user.
In the above embodiment, although the specific method of calculating the CRC value is not described, the polynomial expression of "CRC-16-CCITT (X ^16+ X ^12+ X ^5+ 1)" is actually used. Of course, other polynomials (e.g., "CRC-16", "CRC-32") may be used to calculate the CRC value. Note that CRC may be used instead of "2's complement and 2's complement" used for "MODBUS ASCII" checksum calculation.
[ derived effect ]
In fig. 1, an arbitrary value is always written into the CRC value calculation target register 24-1 before the operation, and therefore the CRC value of the data written into the CRC value calculation target register 24-1 is different from the initial value in the operation of the IC 2. Therefore, by monitoring the CRC present value by the CPU1 during the operation of the IC2, it can be confirmed whether or not an unexpected reset has occurred due to the influence of noise or the like. That is, if a reset occurs, the current CRC value becomes an initial value, and by utilizing this, it is possible to confirm whether an unexpected reset has occurred.
In addition, in fig. 1, as a method of notifying the CPU1 of an abnormality, there is also a method of including the value of the error detection register 24-4 in the communication protocol. For example, as shown in fig. 9, "0 x 04" of the MISO signal is assigned as the internal register exception detection, so that the IC internal state is also included in the response of the SPI access with checksum. Thus, the frequency of polling the error detection register 24-4 by the CPU1 can be reduced.
[ extension of embodiment ]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various modifications can be made to the configuration and details of the present invention within the scope of the technical idea of the present invention, which will be apparent to those skilled in the art.
Description of the symbols
1 CPU (arithmetic processing unit)
2 IC
21 data receiving circuit
22 command control part
23 data transmission circuit
24 internal register
24-1 CRC value calculation target register
24-2 CRC value calculation non-object registers
24-3 CRC value calculating section
24-4 error detection register
2A register
2B data write section
2C CRC expected value calculation unit
2D CRC present value calculation unit
2E CRC present value storage section
2F CRC expected value storage unit
2G coincidence/non-coincidence determination unit
2H error detection register
100 register exception detection means.
Claims (2)
1. A register abnormality detection device including an arithmetic processing unit and a register to which data sent from the arithmetic processing unit is written, the register abnormality detection device detecting an abnormality of the data written in the register, the register abnormality detection device comprising:
a data writing unit that writes the data sent from the arithmetic processing unit into the register;
an expected value calculation unit that calculates an expected value of an index for inspection for detecting an abnormality in the data written in the register;
a current value calculation unit that repeatedly calculates a current value corresponding to an expected value of the check index of the data written in the register;
a current value storage unit configured to update and store the current value of the inspection index calculated by the current value calculation unit each time; and
a match/mismatch determination unit that determines, each time the current value of the check index is calculated by the current value calculation unit, a match/mismatch between the calculated current value of the check index and the expected value, and writes the determination result as a 1 st determination result in an error detection register,
the arithmetic processing unit reads the 1 st determination result written in the error detection register and the current value of the check index stored in the current value storage unit,
every time the current value is read out from the current value storage unit, the coincidence/non-coincidence of the read current value and the expected value stored in the arithmetic processing unit is determined, and the determination result is regarded as the 2 nd determination result,
the arithmetic processing unit detects an abnormality in the data written in the register, except when the 1 st determination result is identical and the 2 nd determination result is identical.
2. The register exception detection apparatus according to claim 1,
the 1 st determination result written in the error detection register is included in a communication protocol and sent to the arithmetic processing unit.
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| JP7350488B2 (en) * | 2019-01-30 | 2023-09-26 | ラピスセミコンダクタ株式会社 | Peripheral device control system and peripheral device control method |
| CN111949547A (en) * | 2020-08-22 | 2020-11-17 | 深圳市捷诚技术服务有限公司 | Problem positioning method based on single chip microcomputer abnormity, single chip microcomputer, equipment and system |
| CN115220972A (en) * | 2022-06-07 | 2022-10-21 | 中科驭数（北京）科技有限公司 | Equipment fault detection method, device, equipment and computer readable storage medium |
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| CN104679196A (en) * | 2015-03-10 | 2015-06-03 | 江苏邦融微电子有限公司 | Processor-based self-detection and abnormality reset system and implementation method thereof |
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| JP4343945B2 (en) * | 2006-12-28 | 2009-10-14 | 三菱電機株式会社 | Electronic control unit |
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| US9087192B2 (en) * | 2013-09-10 | 2015-07-21 | Infineon Technologies Ag | Electronic circuit and method for monitoring a data processing |
| JP6273979B2 (en) * | 2014-04-01 | 2018-02-07 | 株式会社デンソー | Control device or control system |
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| CN102693176A (en) * | 2011-01-19 | 2012-09-26 | 株式会社东芝 | Processor operation monitoring system and monitoring method thereof |
| CN104679196A (en) * | 2015-03-10 | 2015-06-03 | 江苏邦融微电子有限公司 | Processor-based self-detection and abnormality reset system and implementation method thereof |
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