CN108780385B

CN108780385B - Analog-to-digital conversion result reading circuit

Info

Publication number: CN108780385B
Application number: CN201780014289.4A
Authority: CN
Inventors: 栗林英毅; 平山博文
Original assignee: Azbil Corp
Current assignee: Azbil Corp
Priority date: 2016-03-03
Filing date: 2017-02-28
Publication date: 2021-08-17
Anticipated expiration: 2037-02-28
Also published as: WO2017150491A1; KR102035768B1; JP2017157060A; JP6499602B2; KR20180108723A; CN108780385A

Abstract

The invention provides an AD conversion result reading circuit, comprising: a read detection circuit which validates the detection signal when receiving the high order bit of the command from the serial peripheral interface host and determining as a read command, and validates the transmission permission signal when receiving all the commands and determining as a read command; a clock changing circuit for outputting an internal register value change inhibiting signal according to the signal; an AD conversion result register for importing an AD conversion result when a data preparation completion signal from the AD converter is valid and an internal register value change prohibition signal is invalid; and a data transmission circuit for transmitting the AD conversion result to the serial peripheral interface host when the transmission permission signal is valid. According to the present invention, the time-series design burden of the designer can be reduced. Furthermore, the performance required of the host for the serial peripheral interface can be relaxed.

Description

Analog-to-digital conversion result reading circuit

Technical Field

The present invention relates to an Analog-to-Digital (AD) conversion result reading circuit that reads an AD conversion result from an AD converter.

Background

In a conventional general Δ Σ AD converter, when an AD conversion result is read from a Central Processing Unit (CPU) or the like via a Serial Peripheral Interface (SPI), an SPI master needs to be designed so as to monitor a DRDY signal indicating a conversion state and read the AD conversion result until the next conversion is completed after a drop of the DRDY signal is detected (see non-patent documents 1 and 2).

The reason for this restriction is that if the timing of the readout of the conversion result of the SPI master is delayed by another process after the drop of the DRDY signal is detected, the update of the next AD conversion result and the readout from the SPI master collide, resulting in the read AD conversion result becoming an indefinite value. Further, the AD converter does not provide a method for determining and confirming that the AD conversion result is an indeterminate value. Therefore, timing delay is never allowed when reading out the AD conversion result, and the designer of the CPU constituting the SPI master as the external device must perform extremely strict time management.

Documents of the prior art

Non-patent document

Non-patent document 1: "24-bit A/D converter ADS1248 facing temperature sensor", Texas Instruments, Inc. < http:// www.tij.co.jp/jp/lit/ds/symlink/ADS1248. pdf' >

Non-patent document 2: "20 μ s Stable (setting), 250kSPS 24 bit E- Δ ADC AD 7176-2", Analog Devices (Analog Devices) Inc., 2012, < http: // www.analog.com/media/jp/technical-documentation/data-sheets/AD7176-2_ jp.pdf >

Disclosure of Invention

Problems to be solved by the invention

As described above, in the past, a designer designing an external device such as an SPI master which reads an AD conversion result must strictly manage the time. Therefore, the designer is burdened with timing design. Furthermore, a CPU with a margin in processing capability must be selected in the external device.

The present invention is made to solve the above problems, and an object of the present invention is to reduce the time-series design load of a designer. Further, it is an object to provide an AD conversion result reading circuit capable of relaxing performance required for a CPU constituting an external device.

Means for solving the problems

An AD conversion result reading circuit of the present invention includes: a detection circuit that validates a detection signal when a high-order bit of a command from an external device as a transmission destination of an AD conversion result of the AD converter is received and it is determined as a read command, and validates a transmission permission signal when all commands from the external device are received and it is determined as a read command; a clock change circuit that outputs an internal register value change disable signal synchronized with a clock of the AD converter in accordance with the detection signal synchronized with a clock of the external device; a first AD conversion result register that, when a data preparation completion signal from the AD converter is valid and the internal register value change prohibition signal is invalid, introduces an AD conversion result of the AD converter; and a data transmission circuit configured to read the AD conversion result from the first AD conversion result register and transmit the AD conversion result to the external device when the transmission permission signal is asserted.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, by providing the detection circuit, the clock modification circuit, the first AD conversion result register, and the data transmission circuit, the AD conversion result can be transmitted to the external device without particularly restricting the external device, and therefore, the time series design load of the designer can be reduced. Furthermore, the performance required for the CPU constituting the external device can be relaxed.

Drawings

Fig. 1 is a block diagram showing a configuration of an AD conversion result reading circuit according to a first embodiment of the present invention.

Fig. 2 is a flowchart illustrating an operation of a READ (READ) detection circuit of the AD conversion result reading circuit according to the first embodiment of the present invention.

Fig. 3 is a timing chart illustrating the operation of each unit of the AD conversion result reading circuit according to the first embodiment of the present invention.

Fig. 4 is a block diagram showing a configuration example of a clock modification circuit of the AD conversion result reading circuit according to the first embodiment of the present invention.

Fig. 5 is a timing diagram illustrating the timing relationship for preventing a metastable (metastable) state.

FIG. 6 is a timing diagram illustrating the timing relationship for preventing a meta-stable condition.

Fig. 7 is a timing chart showing an operation when the clock frequency on the AD converter side is increased in the conventional AD conversion result reading circuit.

Fig. 8 is a timing chart illustrating the operation of each unit of the AD conversion result reading circuit according to the second embodiment of the present invention.

Fig. 9 is a block diagram showing a configuration of an AD conversion result reading circuit according to a third embodiment of the present invention.

Description of the symbols

1: AD converter

2. 3: register for AD conversion result

4. 4 a: read detection circuit

5: clock changing circuit

6. 6 a: data transmission circuit

7: SPI host

8. 9: register for identification data

50. 51: flip-flop

Detailed Description

[ first embodiment ]

Embodiments of the present invention will be described below with reference to the drawings.

Fig. 1 is a block diagram showing a configuration of an AD conversion result reading circuit according to a first embodiment of the present invention. The AD conversion result reading circuit of the present embodiment includes: an AD conversion result register 2 and an AD conversion result register 3 for temporarily storing AD conversion results of an AD converter (hereinafter, ADC)1, respectively; a read detection circuit 4 that validates the detection signal when receiving the high-order bit of the command from the SPI master 7 as the external device and determining it as the read command, and validates the transmission permission signal when receiving all the commands from the SPI master 7 and determining it as the read command; a clock change circuit 5 that outputs an internal register value change prohibition signal synchronized with the clock of the ADC1, based on a detection signal synchronized with the clock of the SPI master 7; and a data transmission circuit 6 for reading the AD conversion result from the AD conversion result register 2 and transmitting the AD conversion result to the SPI host 7 when the transmission permission signal is active.

The AD conversion result reading circuit according to the first embodiment includes two AD

conversion result registers

2 and 3, but in the present invention, any one of them may be provided, and the provision of two AD conversion result registers is not an essential component.

Next, with respect to the operation of the AD conversion result reading circuit, an example of an operation using only one AD conversion result register 2 will be described with reference to fig. 2 and 3. Fig. 2 is a flowchart for explaining the operation of the read detection circuit 4, and fig. 3 is a timing chart for explaining the operation of each unit of the AD conversion result read circuit.

In the present embodiment, the clock of the ADC1 is CLK _ REG, and the clock of the SPI master 7 including the CPU is SCLK. In the configuration of the AD conversion result reading circuit shown in fig. 1, the AD conversion result register 2, the AD conversion result register 3, and the clock changeover circuit 5 operate in synchronization with CLK _ REG, and the read detection circuit 4, the clock changeover circuit 5, and the data transmission circuit 6 operate in synchronization with SCLK.

In fig. 3, CS indicates a chip select signal, MOSI (Master Out Slave In) and MISO (Master In Slave Out) indicate signal lines of the SPI Master 7, SCLK _ INV indicates an inversion signal of a clock SCLK, CNT is a clock count value, READ _ ACT indicates a detection signal of a READ command, RDATA _ EN indicates a transmission permission signal of an AD conversion RESULT, READ _ ACT _ SYNC indicates an internal register value change prohibition signal, DRDY indicates a data preparation completion signal of the ADC1, RESULT indicates an AD conversion RESULT output from the ADC1, RESULT _ BUF indicates an AD conversion RESULT stored In the AD conversion RESULT register 3, and RESULT _ LATCH indicates an AD conversion RESULT stored In the AD conversion RESULT register 2.

First, when a command is transmitted from the SPI host 7 including the CPU via the signal line MOSI, the read detection circuit 4 determines whether or not the high order 3 bit of the command matches the high order 3 bit of the RDATA command, that is, the high order 3 bit of the read command of the AD conversion result, at the time point when the high order 3 bit of the command is received (step S1 in fig. 2) (step S2 in fig. 2). In the example of fig. 3, C7 to C5 are the high-order 3 bits of the command, and are determined at the time point of time t 1. The reason for performing the determination with the high-order 3 bits will be described later.

When the high-order 3 bits of the command from the SPI host 7 coincide with the high-order 3 bits of the READ command (yes in step S2), the READ detection circuit 4 sets the detection signal READ _ ACT to "1" (active) (step S3 of fig. 2).

Further, when receiving all the 8-bit commands from the SPI host 7 with the lower order 5 bits of the command (step S4 in fig. 2), the read detection circuit 4 determines whether or not the 8-bit command matches the RDATA command, that is, the read command of the AD conversion result (step S5 in fig. 2). In the example of FIG. 3, C4-C0 are the low order 5 bits of the command.

When the 8-bit command from the SPI host 7 matches the READ command (Y in step S5), the READ detection circuit 4 holds the detection signal READ _ ACT at "1" (step S6 in fig. 2), and issues a single pulse of the transmission permission signal RDATA _ EN.

When the transmission permission signal RDATA _ EN of one pulse is issued, the data transmission circuit 6 reads out the AD conversion result of 8 bits from the AD conversion result register 2 (step S7 in fig. 2), and transmits the AD conversion result of 8 bits as transmission data to the SPI host 7 via the signal line MISO serial (serial) (step S8 in fig. 2). In the example of fig. 3, the AD conversion result of 8 bits of D0 to D7 is transmitted as transmission data to the SPI host 7 in accordance with the transmission permission signal RDATA _ EN at time t 3.

Next, the read detection circuit 4 determines whether transmission of the number of data corresponding to the command, for example, transmission of the AD conversion result is completed (step S9 in fig. 2), and if transmission is not completed (no in step S9), returns to step S7 and again issues the one-pulse transmission permission signal RDATA _ EN. When the read detection circuit 4 issues the one-pulse transmission permission signal RDATA _ EN, the data transmission circuit 6 further reads the AD conversion result of 8 bits from the AD conversion result register 2 and serially transmits the result to the SPI host 7 (step S8 in fig. 2). In the example of fig. 3, the AD conversion result of 8 bits of D8 to D15 is transmitted as transmission data to the SPI host 7 in accordance with the transmission permission signal RDATA _ EN at time t 4.

In this way, the processing of step S7 and step S8 is repeatedly executed until the transmission of the number of data corresponding to the command, that is, the transmission of the AD conversion result is completed. In the present embodiment, the AD conversion result transmitted in response to the read command from the SPI host 7 is set to 24 bits. Therefore, the transmission permission signal RDATA _ EN is issued three times, and the determination result in step S9 becomes "Y" at the time point when the 24-bit data of D0 to D23 is transmitted (time t 5).

When the data transmission is completed and the determination result at step S9 becomes "Y", the READ detection circuit 4 sets the detection signal READ _ ACT to "0" (invalid) (step S10 of fig. 2).

The READ detection circuit 4 may set the detection signal READ _ ACT to "0" (inactive) when it receives all commands from the external device and determines that the command is not a READ command after setting the detection signal READ _ ACT to "1" (active). This is because, in the determination in step S2, even if the high-order 3 bit of the command from the SPI host 7 matches the high-order 3 bit of the read command, there is a possibility that an erroneous determination is made. Thus, after the high-order 3 bits of the command from the SPI host 7 coincide with the high-order 3 bits of the READ command and the detection signal READ _ ACT is set to "1" (valid) (step S3 of fig. 2), if the 8-bit command from the SPI host 7 does not coincide with the READ command as a result of analyzing all the 8-bit commands in step S5 (N in step S5 of fig. 2), the detection signal READ _ ACT is set to "0", and the determination results in step S2 and step S3 are cancelled.

Next, a configuration that operates in synchronization with the clock CLK _ REG of the ADC1 will be described with reference to fig. 3.

First, when it is notified that the data preparation completion signal DRDY output from the ADC1 has dropped from "1" (invalid) to "0" (valid) and the data preparation of the ADC1 has been completed, the AD conversion RESULT register 2 indicates that the internal register value change prohibition signal READ _ ACT _ SYNC at this time is "0" (invalid) and the READ command is not detected, and therefore the AD conversion RESULT from the ADC1 is introduced. As described above, the AD conversion RESULT is 24 bits. The imported AD conversion RESULT is stored in the AD conversion RESULT register 2, and the output RESULT _ LATCH of the AD conversion RESULT register 2 is updated. In the example of fig. 3, RESULT _ LATCH shows an update from "old" representing an old conversion RESULT to "new" representing a newly imported conversion RESULT.

On the other hand, the clock changing circuit 5 generates an internal register value change disable signal READ _ ACT _ SYNC synchronized with the clock CLK _ REG of the ADC1 based on the detection signal READ _ ACT output from the READ detecting circuit 4.

Fig. 4 is a block diagram showing a configuration example of the clock modification circuit 5. The clock changing circuit 5 includes two flip-flops (flip-flops) 50 and 51. As shown in fig. 4, the flip-flop 51 is connected in cascade (cascade) with the flip-flop 50, and the two flip-

flops

50 and 51 are driven by the clock CLK _ REG of the ADC 1.

As shown in fig. 4, the clock change process for a 1-bit signal often uses a method of performing two-stage reception with a clock on the reception side. When this method is used, the internal register value change disable signal READ _ ACT _ SYNC is delayed by a time at most 2 times the period of CLK _ REG with respect to the detection signal READ _ ACT (the detection signal READ _ ACT is delayed by the flip-flop 50 to generate the signal READ _ ACT _1D, and the signal READ _ ACT _1D is delayed by the flip-flop 51 to generate the internal register value change disable signal READ _ ACT _ SYNC). In the example of fig. 3, after the detection signal READ _ ACT becomes "1" (active) at time t1, the internal register value change prohibition signal READ _ ACT _ SYNC becomes "1" (active) at time t 2. Further, after the detection signal READ _ ACT becomes "0" (inactive) at time t5, the internal register value change inhibit signal READ _ ACT _ SYNC becomes "0" (inactive) at time t 6. The time difference between the time t1 and the time t2 and the time difference between the time t5 and the time t6 are delays caused by the clock modification circuit 5 shown in fig. 4, respectively.

If the SPI master 7 reads out the conversion result without considering the conversion cycle of the ADC1, the data may be destroyed and the correct data may not be read out. The reason why the data is destroyed is that the relationship between the clock SCLK of the SPI master 7 and the clock CLK _ REG of the ADC1 is asynchronous, and therefore, when data is transferred based on different clocks, if rising edges of the two clocks come close by chance, the setup/hold time (setup/hold time) of the flip-flop does not become satisfied. The phenomenon is referred to as "metastability". Metastable, for example, in the literature "column: asynchronous clock and verification method-2 ", attima (Altima) corporation, < http: // www.altima.jp/products/software/implementation/fv/column/cdc-2. html >.

Fig. 5 and 6 are timing diagrams illustrating the timing of altering a clock to prevent such metastability. Fig. 5 shows a case where the clock change time is short (a case where the clock CLK _ REG rises immediately after the rise of the detection signal READ _ ACT), and fig. 6 shows a case where the clock change time is long (a case where the detection signal READ _ ACT rises immediately after the rise of the clock CLK _ REG).

In order to prevent metastability, it is necessary to set the internal register value change disable signal READ _ ACT _ SYNC to "1" (active) before the timing of transmitting the AD conversion result to the SPI master 7, and to control the register value so as not to change during the transmission of the AD conversion result. That is, in fig. 5 and 6, T1 > T2 must be set. Here, T1 is the time from when the detection signal READ _ ACT becomes "1" until the transmission permission signal RDATA _ EN becomes "1" (valid), and T2 is the time required for the clock change.

That is, if the determination execution cycle of the detection signal READ _ ACT is N, the determination of the detection signal READ _ ACT needs to be performed at a timing when the following expression (1) is satisfied.

SCLK period X (8-N) > CLK _ REG period X2 … (1)

Here, since the command is 8 bits, the maximum value of N is 8.

If the relationship between the frequency of the clock SCLK of the SPI master 7 and the frequency of the clock CLK _ REG of the ADC1 is, for example, SCLK: CLK _ REG of 1: 10, even if the determination of the detection signal READ _ ACT is performed after all the commands (8 bits) from the SPI master 7 are received, the AD conversion result can be transmitted to the SPI master 7 without imposing any particular restrictions on the SPI master 7.

Fig. 7 shows an operation when the frequency of the clock CLK _ REG is sufficiently increased in the conventional AD conversion result reading circuit. In the example of fig. 7, after all of the 8-bit commands of C7 to C0 are READ, the detection signal READ _ ACT is set to "1". In this manner, if the clock CLK _ REG is sufficiently fast, it becomes unnecessary to pre-READ the detection signal READ _ ACT to 1. However, since the clock CLK _ REG becomes high speed, there is a problem that power consumption increases.

On the other hand, when the relationship between the frequencies of SCLK and CLK _ REG is SCLK: CLK _ REG of 2: 1 as in the present embodiment, considering the time T2 required for the clock change, the determination of the detection signal READ _ ACT after simply receiving all of the 8 bits of the command cannot catch up with the transmission timing of the conversion result. Therefore, in the present embodiment, the detection signal READ _ ACT is determined before all of the 8-bit commands are received. As in the present embodiment, when the maximum frequency of the clock SCLK is 2 times the frequency of the clock CLK _ REG, it is necessary to satisfy equation (1) so that N < 4 is satisfied. Therefore, in the present embodiment, N is 3. This is the reason why the determination is made in the high-order 3 bits of the command in step S2 in fig. 2.

Since the detection signal READ _ ACT is determined before all of the 8-bit commands are received, when the transmission permission signal RDATA _ EN becomes "1" (active), the internal register value change prohibition signal READ _ ACT _ SYNC is always "1" (active), and therefore, the output RESULT _ LATCH of the register 2 for AD conversion does not change at the transmission timing of the AD conversion RESULT (t 3, t4 in the example of fig. 3). I.e. no metastability occurs.

With the above configuration, in the present embodiment, since the result of AD conversion can be transmitted to the SPI host 7 without imposing any particular restriction on the SPI host 7, the time-series design load of the designer can be reduced, and the performance required of the SPI host 7(CPU) can be alleviated.

In the present embodiment, by making the output RESULT _ LATCH of the AD conversion RESULT register 2 never change at the timing when the transmission permission signal RDATA _ EN becomes "1", the AD conversion RESULT can be prevented from becoming an indefinite value, and the AD conversion RESULT can be protected without increasing the frequency of the clock CLK _ REG of the ADC 1.

In the present embodiment, the determination in step S2 is performed using a plurality of high-order bits, specifically, using a 3-order bit, but the present invention is not limited thereto, and the determination in step S2 may be performed using only the highest-order bit.

[ second embodiment ]

Next, a second embodiment of the present invention will be explained.

The AD conversion result reading circuit of the second embodiment uses an AD conversion result register 3 in addition to the AD conversion result register 2 used in the first embodiment. More specifically, the AD conversion result reading circuit according to the second embodiment further includes, in addition to the first AD conversion result register 2, a second AD conversion result register 3, the second AD conversion result register 3 introducing the AD conversion result of the ADC1 when the data preparation completion signal from the ADC1 is active and the internal register value change prohibition signal READ _ ACT _ SYNC is active, and the first AD conversion result register 2 introducing the output of the second AD conversion result register 3 when the internal register value change prohibition signal READ _ ACT _ SYNC is inactive.

In the present embodiment, the configuration of the AD conversion result reading circuit is the same as that of the first embodiment, and therefore the description will be given using the reference numerals in fig. 1. Fig. 8 is a timing chart for explaining the operation of each part of the AD conversion result reading circuit according to the present embodiment.

The operations of the read detection circuit 4, the clock modification circuit 5, and the data transmission circuit 6 are as described in the first embodiment.

As described in the first embodiment, when the data ready signal DRDY output from the ADC1 falls from "1" (invalid) to "0" (valid) and the internal register value change disable signal READ _ ACT _ SYNC is "0" (invalid), the AD conversion RESULT register 2 introduces the AD conversion RESULT of the ADC 1. As a RESULT, the AD conversion RESULT is updated by the output RESULT _ LATCH of the register 2.

However, in the second embodiment, when the data ready signal DRDY falls from "1" to "0", the internal register value change disable signal READ _ ACT _ SYNC is already "1" (enabled), and therefore the first AD conversion RESULT register 2 cannot introduce the AD conversion RESULT of the ADC 1. Thus, the update of the output RESULT _ LATCH of the first AD conversion RESULT register 2 becomes impossible. That is, in the first and second embodiments, the section in which the internal register value change inhibition signal READ _ ACT _ SYNC becomes "1" (active) is the internal register value change inhibition section.

Therefore, the second AD conversion result register 3 is used in the second embodiment. That is, when the data ready signal DRDY output from the ADC1 falls from "1" (invalid) to "0" (valid) and the internal register value change disable signal READ _ ACT _ SYNC is "1" (valid), the second AD conversion RESULT register 3 introduces the AD conversion RESULT of the ADC 1. As a RESULT, the second AD conversion RESULT is updated with the output RESULT _ BUF of the register 3. From the example of fig. 8, it is understood that the RESULT _ BUF is updated to "new" indicating the newly imported conversion RESULT.

When the internal register value change disable signal READ _ ACT _ SYNC changes from "1" (active) to "0" (inactive), the first AD conversion RESULT register 2 leads to the output RESULT _ BUF of the second AD conversion RESULT register 3 (time t 7). Thus, the first AD conversion RESULT is updated with the output RESULT _ LATCH of the register 2. In the example of fig. 8, it is understood that RESULT _ LATCH is updated from "old" indicating an old conversion RESULT to "new" indicating a newly introduced conversion RESULT.

The other structure is as described in the first embodiment.

In the first embodiment, when the internal register value change inhibit signal READ _ ACT _ SYNC has become "1" when the data preparation completion signal DRDY output from the ADC1 falls from "1" to "0", the first AD conversion result register 2 cannot introduce the AD conversion result of the ADC1, and therefore there is a possibility that the AD conversion result is missed. In contrast, in the second embodiment, by providing the second AD conversion result register 3, when the AD conversion result cannot be introduced into the first AD conversion result register 2, the second AD conversion result register 3 introduces the AD conversion result, and therefore, the occurrence of missing of the AD conversion result can be avoided.

[ third embodiment ]

Next, a third embodiment of the present invention will be explained. Fig. 9 is a block diagram showing a configuration of an AD conversion result reading circuit according to the third embodiment. In fig. 9, the same reference numerals are given to the same configurations as those of the AD conversion result reading circuits of the first and second embodiments shown in fig. 1.

The AD conversion result reading circuit of the third embodiment includes: an AD conversion result register 2 and an AD conversion result register 3; a read detection circuit 4 a; a clock change circuit 5; a data transmission circuit 6 a; an identification data register 8 and an identification data register 9.

More specifically, the AD conversion result reading circuit according to the third embodiment further includes, in addition to the configuration of the AD conversion result reading circuit according to the first embodiment or the second embodiment, a first identification data register 8, in which identification data associated with the AD conversion result is introduced from the ADC1 when the data preparation completion signal DRDY from the ADC1 is active and the internal register value change prohibition signal READ _ ACT _ SYNC is "0" (inactive), and the data transmission circuit 6a READs the AD conversion result from the first AD conversion result register 2 and transmits it to the external device and READs the identification data from the first identification data register 8 and transmits it to the external device when the transmission permission signal RDATA _ EN is "1" (active).

The AD conversion result reading circuit according to the third embodiment further includes a second identification data register 9, and the second identification data register 9 may introduce identification data when the data preparation completion signal DRDY from the ADC1 is active and the internal register value change inhibition signal READ _ ACT _ SYNC is "1" (active), or the first identification data register 8 may introduce the output of the second identification data register 9 when the internal register value change inhibition signal READ _ ACT _ SYNC is "0" (inactive).

In the third embodiment, the ADC1 outputs the identification data DID associated with the AD conversion RESULT in addition to the AD conversion RESULT.

After the transmission of the 24-bit AD conversion result, the read detection circuit 4a issues a one-pulse transmission permission signal RDATA _ EN to transmit, for example, 8-bit identification data DID (step S7 in fig. 2). The data transmission circuit 6a reads the identification data DID from the identification data register 8 and serially transmits the identification data DID to the SPI host 7 in response to the transmission permission signal RDATA _ EN (step S8 in fig. 2).

In this way, in the third embodiment, the processing of step S7 and step S8 in fig. 2 is repeatedly executed until the transmission of the total 32-bit data is completed by adding the 8-bit identification data DID to the 24-bit AD conversion result. In the example of fig. 3 and 8, after the 24-bit data of D0 to D23 is transmitted, for example, 8-bit identification data DID is transmitted. The other operations of the read detection circuit 4a are the same as those of the read detection circuit 4 in the first and second embodiments.

Next, the operation of the identification data register 8 and the identification data register 9 will be described.

When the data ready signal DRDY output from the ADC1 falls from "1" (invalid) to "0" (valid) and the internal register value change disable signal READ _ ACT _ SYNC is "0" (invalid), the identification data register 8 imports the identification data DID output from the ADC 1. In this way, the output DID _ LATCH of the identification data register 8 is updated.

However, like the AD conversion result register 2, when the data ready signal DRDY output from the ADC1 falls from "1" to "0", the identification data register 8 cannot introduce the identification data DID if the internal register value change disable signal READ _ ACT _ SYNC has become "1" (active).

On the other hand, when the data ready signal DRDY output from the ADC1 falls from "1" to "0" and the internal register value change disable signal READ _ ACT _ SYNC is "1", the identification data register 9 receives the identification data DID from the ADC 1. Thus, the identification data is updated with the output DID _ BUF of the register 9.

When the internal register value change inhibiting signal READ _ ACT _ SYNC changes from "1" to "0", the identification data register 8 inputs the output DID _ BUF of the identification data register 9.

In this manner, the identification data register 8 performs the same operation as the AD conversion result register 2 on the identification data DID, and the identification data register 9 performs the same operation as the second AD conversion result register 3.

Next, the identification data DID will be described in detail. As the generation method of the identification data DID, for example, the following four methods can be exemplified.

The first example is a method in which data based on the number of times of execution of AD conversion processing is set as the identification data DID. For example, the identification data is data indicating the number of times of execution of the AD conversion process of the ADC 1. Specifically, the number of times of execution of the AD conversion process may be counted in the ADC1, and the count value may be set as the identification data DID. In this manner, by recording the number of times of execution of the AD conversion processing as the identification data DID, it is possible to identify the AD conversion result of the AD conversion processing executed at a certain timing and the AD conversion result of the AD conversion processing executed at a timing before and after it.

The second example is a method in which data based on the execution timing of the AD conversion process, for example, data indicating the timing at which the AD conversion process is executed by the ADC1 is used as the identification data DID. Specifically, the ADC1 may set the execution time (time stamp) of the AD conversion process as the identification data DID.

As specific methods using the execution timing of the AD conversion process, for example, the following two methods can be exemplified. One is a method of setting the real-time clock inside or outside the ADC 1. Another method is to provide a counter inside or outside the ADC1, for example, which is set to time 0 when the power is turned on and is incremented at regular intervals, instead of the real-time clock.

According to either of the two methods, it is possible to identify the AD conversion result of the AD conversion process performed at a certain timing and the AD conversion results of the AD conversion processes performed at timings before and after it. Further, according to the method using the real-time clock, it is possible to record the exact time at which the AD conversion process is performed. On the other hand, according to the method not using the real-time clock, an increase in the circuit scale can be suppressed.

The third example is a method of setting 1-bit data whose logic level is inverted every time AD conversion processing is performed as identification data DID. That is, the identification data DID is 1-bit data whose logic level is inverted every time the AD conversion process is performed using the ADC 1. According to the method, it is possible to identify the AD conversion result of the AD conversion process performed at a certain timing and the AD conversion results of the AD conversion processes performed at timings before and after it. In addition, since the identification data DID is set to 1 bit, necessary hardware resources can be reduced, and an increase in circuit scale can be suppressed.

The fourth example is a method in which data based on the count value of a free run counter (free run counter) is used as the identification data DID. For example, pulses that are continuously input regardless of the execution process of the AD conversion process may be counted by an 8-bit free-running counter, and the count value may be set as the identification data DID. Accordingly, a counter having a large bit width is not required, and thus an increase in the circuit scale can be suppressed. The data stored as the identification data DID may be not the count value (numerical value) of the free running counter itself, but may be an alphabet (alphabet) (character code) having a known order, such as a to Z, for example.

As described above, according to the third embodiment, since the identification data is given to each AD conversion result and the identification data are output as a set (set), it is possible to determine whether or not the continuity of the obtained AD conversion result is maintained on the SPI master 7 side that receives the AD conversion result.

Further, according to the third embodiment, the first identification data register 8 is provided, and the data transmission circuit 6a reads out the identification data from the first identification data register 8 and transmits the identification data to the external device when the transmission permission signal RDATA _ EN from the read detection circuit 4a is valid, whereby the external device can determine whether or not there is duplication of the AD conversion result or omission of the AD conversion result.

Further, by providing the second identification data register 9, occurrence of missing of identification data can be avoided.

For example, by comparing the identification data corresponding to the obtained AD conversion result with the identification data corresponding to the AD conversion result obtained immediately before the same, it is also possible to determine on the SPI master 7 side whether or not there is a repetition of the AD conversion result of the AD conversion cycle or missing of the AD conversion result, that is, whether or not the continuity of the obtained AD conversion result is maintained.

In the third embodiment, the case where both the AD conversion result register 2 and the AD conversion result register 3 are used has been described, but only the AD conversion result register 2 may be used as described in the first embodiment. As described above, although there is a possibility that the result of AD conversion is missed in the first embodiment, the SPI master 7 can determine the presence or absence of such missed result according to the second and third embodiments.

Industrial applicability

The present invention can be applied to a technique of reading out an AD conversion result regardless of the conversion cycle of the AD converter.

Claims

1. An analog-to-digital conversion result readout circuit, characterized by comprising:

a detection circuit that validates a detection signal synchronized with a clock of an external device when a high-order bit of a command from the external device as a transmission destination of an analog-to-digital conversion result of the analog-to-digital converter is received and it is determined that the command is a read command, and validates a transmission permission signal when the command from the external device is completely received and it is determined that the command is the read command;

a clock changing circuit that outputs an internal register value change inhibiting signal synchronized with a clock of the analog-to-digital converter in accordance with the detection signal;

a first analog-to-digital conversion result register that imports the analog-to-digital conversion result of the analog-to-digital converter when a data preparation completion signal from the analog-to-digital converter is valid and the internal register value change prohibition signal is invalid; and

and a data transmission circuit configured to read out the analog-to-digital conversion result from the first analog-to-digital conversion result register and transmit the analog-to-digital conversion result to the external device when the transmission permission signal is asserted.

2. The analog-to-digital conversion result readout circuit according to claim 1, wherein in the analog-to-digital conversion result readout circuit,

further comprising: a second analog-to-digital conversion result register for importing the analog-to-digital conversion result of the analog-to-digital converter when the data preparation completion signal from the analog-to-digital converter is valid and the internal register value change prohibition signal is valid, and

the first analog-to-digital conversion result register imports an output of the second analog-to-digital conversion result register when the internal register value change prohibition signal becomes invalid.

3. The analog-to-digital conversion result readout circuit according to claim 1 or 2, wherein in the analog-to-digital conversion result readout circuit,

further comprising: a first identification data register for importing identification data associated with the analog-to-digital conversion result from the analog-to-digital converter when a data preparation completion signal from the analog-to-digital converter is valid and the internal register value change prohibition signal is invalid

The data transmission circuit reads out the analog-to-digital conversion result from the first analog-to-digital conversion result register and transmits the analog-to-digital conversion result to the external device, and reads out the identification data from the first identification data register and transmits the identification data to the external device when the transmission permission signal is asserted.

4. The analog-to-digital conversion result readout circuit according to claim 3, wherein in the analog-to-digital conversion result readout circuit,

further comprising: a second identification data register for importing the identification data when the data preparation completion signal from the analog-to-digital converter is valid and the internal register value change prohibition signal is valid, and

the first identification data register is configured to introduce an output of the second identification data register when the internal register value change disable signal is disabled.

5. The analog-to-digital conversion result readout circuit according to claim 1 or 2, wherein in the analog-to-digital conversion result readout circuit,

the detection circuit invalidates the detection signal when the command from the external device is completely received and it is determined that the command is not the read command after the detection signal is validated.

6. The analog-to-digital conversion result readout circuit according to claim 3, wherein in the analog-to-digital conversion result readout circuit,

the identification data is data indicating the number of times of execution of analog-to-digital conversion processing by the analog-to-digital converter.

7. The analog-to-digital conversion result readout circuit according to claim 3, wherein in the analog-to-digital conversion result readout circuit,

the identification data is data indicating a timing at which the analog-to-digital conversion process is performed by the analog-to-digital converter.

8. The analog-to-digital conversion result readout circuit according to claim 3, wherein in the analog-to-digital conversion result readout circuit,

the identification data is 1-bit data whose logic level is inverted each time the analog-to-digital conversion process is performed with the analog-to-digital converter.

9. The analog-to-digital conversion result readout circuit according to claim 3, wherein in the analog-to-digital conversion result readout circuit,

the identification data is data based on a count value of a free-running counter.