CN108780385A - AD result reading circuits - Google Patents
AD result reading circuits Download PDFInfo
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- CN108780385A CN108780385A CN201780014289.4A CN201780014289A CN108780385A CN 108780385 A CN108780385 A CN 108780385A CN 201780014289 A CN201780014289 A CN 201780014289A CN 108780385 A CN108780385 A CN 108780385A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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Abstract
The present invention provides a kind of AD conversion result reading circuit：Read detection circuit (4), when the high-order position and while being determined as read-out command that receive the order from serial peripheral interface host (7) keep detection signal READ_ACT effective, make transmission enabling signal RDATA_EN effective when receiving order whole and being determined as read-out command；Clock change circuit (5) exports internal register value change disable signal READ_ACT_SYNC according to signal READ_ACT；AD conversion result with register (2), when the data preparation from AD converter (1) finish signal DRDY effectively, signal READ_ACT_SYNC it is invalid when, import AD conversion result；And AD conversion result is sent to serial peripheral interface host (7) by data transmission circuit (6) when signal RDATA_EN is effective.In accordance with the invention it is possible to mitigate the timing Design burden of designer.Moreover, can mitigate to the performance required by serial peripheral interface host (7).
Description
Technical field
The present invention relates to one kind to turn from the AD of modulus (Analog-to-Digital, AD) converter reading AD conversion result
Change result reading circuit.
Background technology
In existing general delta sigma-type AD converter, when passing through serial peripheral interface (Serial Peripheral
Interface, SPI) from central processing unit (Central Processing Unit, CPU) etc. read AD conversion result when, must
The DRDY signals of transition status must be indicated with monitoring and convert the phase finished until next after the decline for detecting DRDY signals
Between read AD conversion result mode design SPI hosts (with reference to non-patent literature 1, non-patent literature 2).
The reason of this restriction is arranged be, if after detecting the decline of DRDY signals due to other processing SPI master
The sequential time delay that the transformation result of machine is read, the then update of next AD conversion result and the reading from SPI hosts can rush
It is prominent, become underrange so as to cause read-out AD conversion result.In turn, in AD converter and be not ready to AD conversion result at
The method for carrying out judgement confirmation for underrange.Therefore, the delay that sequential is never allowed when reading AD conversion result, constitutes conduct
The designer of the CPU of the SPI hosts of external device (ED) must carry out extremely stringent time management.
Existing technical literature
Non-patent literature
Non-patent literature 1：" 24 A/D converter ADS1248 towards temperature sensor ", Japanese Texas Instrument (Texas
Instruments) limited liability company, 2011,<http：//www.tij.co.jp/jp/lit/ds/symlink/
ads1248.pdf>
Non-patent literature 2：" 20 μ s stablize 24 ∑-A ADC AD7176-2 of (settling), 250kSPS ", simulation
Device (Analog Devices) limited liability company, 2012,<http：//www.analog.com/media/jp/
technical-documentation/data-sheets/AD7176-2_jp.pdf>
Invention content
Problem to be solved by the invention
As described above, previous, the designer that design reads the external device (ED)s such as the SPI hosts of AD conversion result must carry out sternly
The time management of lattice.Therefore, for designer, timing Design burden is big.Moreover, processing capacity must be selected in external device (ED)
There is the CPU of nargin.
The present invention is to form in order to solve the problem, it is therefore intended that mitigates the timing Design burden of designer.Moreover, mesh
Be provide it is a kind of can mitigate to constitute external device (ED) CPU required by performance AD conversion result reading circuit.
Technical means to solve problem
The AD conversion result reading circuit of the present invention is characterized in that：Detection circuit is used as AD when receiving to come from
The high-order position of the order of the external device (ED) of the sending destination of the AD conversion result of converter and while being determined as read-out command makes inspection
It is effective to survey signal, makes transmission enabling signal when receiving the order whole from the external device (ED) and being determined as read-out command
Effectively；Clock change circuit turns to export with the AD according to the detection signal synchronous with the clock of the external device (ED)
The internal register value that the clock of parallel operation synchronizes changes disable signal；First AD conversion result register, when from the AD
The data preparation of converter finishes signal effectively and when internal register value change disable signal is invalid, imports the AD
The AD conversion result of converter；And data transmission circuit, when the transmission enabling signal is effective, from the first AD conversion knot
Fruit register reads AD conversion result and is sent to the external device (ED).
The effect of invention
According to the present invention, by the way that detection circuit, clock change circuit, the first AD conversion result register and data are arranged
Transmission circuit can not give external device (ED) and AD conversion result restriction is especially sent to external device (ED), therefore can subtract
The timing Design burden of light designer.Moreover, the performance required by the CPU to composition external device (ED) can be mitigated.
Description of the drawings
Fig. 1 is the block diagram of the structure for the AD conversion result reading circuit for indicating the first embodiment of the present invention.
Fig. 2 is reading (READ) detection circuit to the AD conversion result reading circuit of the first embodiment of the present invention
Act the flow chart illustrated.
Fig. 3 is illustrated to the action in each portion of the AD conversion result reading circuit of the first embodiment of the present invention
Sequence diagram.
Fig. 4 is the structure of the clock change circuit for the AD conversion result reading circuit for indicating the first embodiment of the present invention
The block diagram of example.
Fig. 5 is the sequence diagram to being used to prevent the sequential relationship of metastable (metastable) state from illustrating.
Fig. 6 is to the sequence diagram for preventing the sequential relationship of metastable state from illustrating.
Fig. 7 is dynamic when indicating to improve the clock frequency of AD converter side in existing AD conversion result reading circuit
The sequence diagram of work.
Fig. 8 is illustrated to the action in each portion of the AD conversion result reading circuit of second embodiment of the present invention
Sequence diagram.
Fig. 9 is the block diagram of the structure for the AD conversion result reading circuit for indicating third embodiment of the present invention.
Specific implementation mode
[first embodiment]
Hereinafter, being explained with reference to embodiments of the present invention.
Fig. 1 is the block diagram of the structure for the AD conversion result reading circuit for indicating the first embodiment of the present invention.This implementation
The AD conversion result reading circuit of mode includes：AD conversion result register 2, AD conversion result register 3, it is interim respectively
Store the AD conversion result of AD converter (Analog-to-Digital converter, hereinafter, ADC) 1；Read detection circuit
4, when the high-order position for receiving the order from the SPI hosts 7 as external device (ED) and while being determined as read-out command, makes inspection
It is effective to survey signal, so that transmission enabling signal is had when receiving the order whole from SPI hosts 7 and being determined as read-out command
Effect；Clock change circuit 5, according to the detection signal synchronous with the clock of SPI hosts 7 come export with the clock of ADC1 synchronize in
Portion's register value changes disable signal；And data transmission circuit 6, when send enabling signal it is effective when, from AD conversion result with posting
Storage 2 reads AD conversion result and is sent to SPI hosts 7.
In addition, the AD conversion result reading circuit of first embodiment has two AD conversion result registers 2, AD turns
Change result register 3, but any one be set in the present invention, two AD conversion results of setting with register not necessarily
Constitutive requirements.
Next, for the action of AD conversion result reading circuit, turned first to only used an AD using Fig. 2, Fig. 3
Result is changed to be illustrated with the example of the action of register 2.Fig. 2 is the flow illustrated to the action for reading detection circuit 4
Figure, Fig. 3 is the sequence diagram illustrated to the action in each portion of AD conversion result reading circuit.
In present embodiment, the clock of ADC 1 is set as CLK_REG, the clock of the SPI hosts 7 comprising CPU is set as
SCLK.In the structure of AD conversion result reading circuit shown in FIG. 1, AD conversion result register 2, the deposit of AD conversion result
Device 3 and clock change circuit 5 and CLK_REG are synchronously carried out action, read detection circuit 4, clock change circuit 5 and data hair
Power transmission road 6 and SCLK is synchronously carried out action.
In Fig. 3, CS indicates that chip selects (chip select) signal, MOSI (it is main go out from into (Master Out Slave
In)) and MISO (main into from go out (Master In Slave Out)) indicates the signal wires of SPI hosts 7, when SCLK_INV is indicated
The reverse signal of clock SCLK, READ_ACT indicate that the detection signal of read-out command, RDATA_EN indicate the transmission of AD conversion result
Enabling signal, READ_ACT_SYNC indicate that internal register value changes disable signal, and DRDY indicates that the data preparation of ADC 1 is complete
Finish signal, RESULT indicates the AD conversion exported from ADC 1 as a result, the deposit of AD conversion result is stored in RESULT_BUF expressions
AD conversion in device 3 is as a result, RESULT_LATCH indicates the AD conversion result being stored in AD conversion result register 2.
First, it if sending order from the SPI hosts 7 comprising CPU via signal wire MOSI, reads detection circuit 4 and is connecing
The time point (the step S1 of Fig. 2) for receiving the high-order 3 of order, judge the order high-order 3 whether with RDATA* orders
High-order 3, i.e. the read-out command of AD conversion result high-order 3 consistent (the step S2 of Fig. 2).In the example of Fig. 3, C7~C5
For the high-order 3 of order, and judged at the time point of moment t1.The reasons why being judged with high-order 3 will later
Narration.
Under 3 unanimous circumstances of high-order with read-out command of high-order 3 of the order from SPI hosts 7 (in step S2
To be (Y)), it reads detection circuit 4 and is set as signal READ_ACT is detected " 1 " (effective) (the step S3 of Fig. 2).
In turn, if read detection circuit 4 receives the low order 5 of order to which the order for receiving 8 is complete from SPI hosts 7
Portion (the step S4 of Fig. 2), then judge described 8 order whether with RDATA* orders, the i.e. read-out command one of AD conversion result
It causes (the step s5 of Fig. 2).In the example of Fig. 3, C4~C0 is the low order 5 of order.
In 8 orders from SPI hosts 7 and (being Y in step S5) under read-out command unanimous circumstances, detection is read
Circuit 4 remains " 1 " (the step S6 of Fig. 2) by signal READ_ACT is detected, and sends out the transmission enabling signal of a pulse
RDATA_EN。
If sending out the transmission enabling signal RDATA_EN of a pulse, data transmission circuit 6 is from AD conversion result with posting
Storage 2 reads 8 AD conversion results (the step S7 of Fig. 2), and using described 8 AD conversion results as transmission data via
Signal wire MISO serial (serial) is sent to SPI hosts 7 (the step S8 of Fig. 2).In the example of Fig. 3, according to the hair of moment t3
Send enabling signal RDATA_EN that 8 of D0~D7 AD conversion results are sent to SPI hosts 7 as transmission data.
Next, reading the transmission of the data of the judgement of detection circuit 4 quantity corresponding with order, such as AD conversion result
Transmission whether finish (the step S9 of Fig. 2), in the case where not sent (the judgement result of step S9 is "No") return step
Rapid S7 and the transmission enabling signal RDATA_EN for sending out a pulse again.If reading the hair that detection circuit 4 sends out a pulse
Enabling signal RDATA_EN is sent, then data transmission circuit 6 further reads 8 AD conversion from AD conversion result with register 2
As a result parallel series is sent to SPI hosts 7 (the step S8 of Fig. 2).In the example of Fig. 3, according to the transmission enabling signal of moment t4
8 AD conversion results of D8~D15 are sent to SPI hosts 7 by RDATA_EN as transmission data.
In this way, execute the processing of step S7, step S8 repeatedly, until the data of quantity corresponding with order transmission,
I.e. until being sent of AD conversion result.In present embodiment, it will be sent according to the read-out command from SPI hosts 7
AD conversion result is set as 24.Thus, transmission enabling signal RDATA_EN three times is sent out, is sending 24 of D0~D23
The judgement result at the time point of data, step S9 becomes " Y " (moment t5).
If data are sent and the judgement result of step S9 becomes " Y ", signal will be detected by reading detection circuit 4
READ_ACT is set as " 0 " (invalid) (the step S10 of Fig. 2).
In addition, reading detection circuit 4 will detect after signal READ_ACT is set as " 1 " (effective), receiving from external
Detection signal READ_ACT, can also be set as " 0 " (invalid) by the order whole of device and when being determined as not read-out command.Its
The reason is that, in the judgement of step S2, even if from the high-order 3 of the high-order 3 and read-out command of the order of SPI hosts 7
Unanimously, it is also possible to carry out misinterpretation.Thus, in the high-order 3 of the high-order of the order from SPI hosts 73 and read-out command
It is consistent and will be after detection signal READ_ACT is set as " 1 " (effective) (the step S3 of Fig. 2), the order to 8 in step s 5
It is all being analyzed the result is that (the step of Fig. 2 in the case that 8 orders from SPI hosts 7 and read-out command are inconsistent
It is in S5 " N "), detection signal READ_ACT is set as " 0 ", and cancel the judgement result made in step S2, step S3.
Next, the structure synchronously acted with the clock CLK_REG of ADC 1 with reference to Fig. 3 Duis illustrates.
First, if being notified the data preparation exported from ADC 1 and finishing signal DRDY and fall to " 0 " from " 1 " (invalid) (has
Effect) and the data preparation of ADC 1 finished, then AD conversion result register 2 show internal register value at this time change prohibit
Read-out command is not detected for " 0 " (invalid) in stop signal READ_ACT_SYNC, therefore imports the AD conversion knot from ADC 1
Fruit RESULT.As described above, AD conversion result RESULT is 24.The AD conversion result RESULT imported is stored in AD conversion
As a result it uses in register 2, the output RESULT_LATCH of AD conversion result register 2 is updated.In the example of Fig. 3,
RESULT_LATCH shows that " old " from the old transformation result of expression is updated to " new " of the transformation result for indicating newly to import.
On the other hand, clock change circuit 5 is generated according to the detection signal READ_ACT exported from reading detection circuit 4
The internal register value change disable signal READ_ACT_SYNC synchronous with the clock CLK_REG of ADC 1.
Fig. 4 is the block diagram for the configuration example for indicating clock change circuit 5.Clock change circuit 5 includes two triggers
(flip-flop) 50, trigger 51.It is connect as shown in figure 4, trigger 51 is cascaded (cascade) with trigger 50, described two
A trigger 50, trigger 51 are driven by the clock CLK_REG of ADC 1.
As shown in figure 4, the clock change processing for 1 signal carries out two commonly using with the clock of receiving side
The method that grade receives.In the case where having used this method, internal register value changes READ_ACT_SYNC pairs of disable signal
At most postpone 2 times of the time in the period of CLK_REG for detecting signal READ_ACT.In the example of Fig. 3, examined in moment t1
After survey signal READ_ACT becomes " 1 " (effective), become in moment t2 internal register value change disable signal READ_ACT_SYNC
At " 1 " (effective).Moreover, after moment t5 detection signal READ_ACT becomes " 0 " (invalid), in moment t6 internal register value
Change disable signal READ_ACT_SYNC becomes " 0 " (invalid).Time difference and the moment t5 of the moment t1 and moment t2 with
The time difference of moment t6 is the delay caused by clock change circuit 5 shown in Fig. 4 respectively.
Assuming that SPI hosts 7 do not consider the change-over period of ADC 1 and in the case of have read transformation result, data sometimes
It is destroyed and correct data can not be read.The reasons why as data by destroying, the reason is that, the clock of SPI hosts 7
The relationship of the clock CLK_REG of SCLK and ADC 1 be it is asynchronous, therefore, when carrying out the transmission of data based on different clock, if
The rising edge of described two clocks is accidentally close, then become to be unsatisfactory for trigger establishes sequential/holding sequential (setup/
hold timing).The phenomenon is referred to as " metastable ".About metastable, such as in document《" special column：Asynchronous clock and authentication
Method -2 ", Altima (Altima) limited liability company,<http：//www.altima.jp/products/software/
mentor/fv/column/cdc-2.html>》In be illustrated.
Fig. 5 and Fig. 6 is the sequence diagram to preventing the sequential that is metastable and changing clock from illustrating.Fig. 5 indicates clock
The case where change time shortens (the case where clock CLK_REG rises after detection signal READ_ACT just rises), when Fig. 6 is indicated
Clock changes time elongated situation (the case where detection signal READ_ACT rises after clock CLK_REG just rises).
It is metastable in order to prevent, it needs to become internal register value before the sequential for sending AD conversion result to SPI hosts 7
More disable signal READ_ACT_SYNC is set as " 1 " (effective), and in the transmission process of AD conversion result register value do not send out
The mode for changing is controlled.That is, T1 > T2 must be set as in Fig. 5 and Fig. 6.Here, T1 is from detection signal READ_ACT
Become " 1 " rise until send enabling signal RDATA_EN become " 1 " (effective) until time, T2 is that clock change is required
Time.
If that is, cycle is implemented in the judgement for detecting signal READ_ACT is set as N, need to set up in formula below (1)
Sequential is detected the judgement of signal READ_ACT.
Period × 2 ... (1) of the period of SCLK × (8-N) > CLK_REG
Here, since order is 8, the maximum value of N is 8.
If the clock sclk of SPI hosts 7 and the relationship of the frequency of the clock CLK_REG of ADC 1 are, for example, SCLK：CLK_
REG=1：10, even if then having carried out detection signal READ_ACT after receiving the order (8) all from SPI hosts 7
Judgement, SPI hosts 7 can not also be given especially restriction to SPI hosts 7 send AD conversion result.
It is dynamic when Fig. 7 indicates to substantially increase the frequency of clock CLK_REG in existing AD conversion result reading circuit
Make.In the example of described Fig. 7, after having read 8 order wholes of C7~C0, detection signal READ_ACT is set as " 1 ".
Like this, if fully accelerating clock CLK_REG, become to pre-read and be taken as 1 detection signal READ_ACT.But by
Become high speed in clock CLK_REG, therefore has the problem of power consumption increase.
On the other hand, it is SCLK: CLK_REG=in the relationship of the frequency of SCLK and CLK_REG as present embodiment
In the case of 2: 1, if considering the required time T2 of clock change, 8 wholes of order are received merely and are detected later
The judgement of signal READ_ACT can be unable to catch up with the transmission timing of transformation result.Therefore, in present embodiment, 8 lives are being received
The judgement of signal READ_ACT is first detected before enabling all.As present embodiment, if by the maximum frequency of clock sclk
Rate is set as 2 times of the frequency of clock CLK_REG, then according to formula (1), needs that N < 4 is made to set up.Thus, in present embodiment, if
For N=3.It is the reasons why high-order 3 in the step s2 of Fig. 2 with order is judged above.
The judgement of signal READ_ACT is first detected before the order whole for receiving 8, as a result, when transmission license letter
When number RDATA_EN becomes " 1 " (effective), internal register value change disable signal READ_ACT_SYNC, which must become " 1 ", (to be had
Effect), therefore, in the transmission timing (being t3, t4 in the example of Fig. 3) of AD conversion result, the output of AD conversion result register 2
RESULT_LATCH will not change.That is, will not occur metastable.
According to the above structure, in present embodiment, especially restriction can not be given to SPI hosts 7 by the knot of AD conversion
Fruit is sent to SPI hosts 7, therefore can mitigate the timing Design burden of designer, so as to mitigate to SPI hosts 7 (CPU)
Required performance.
Moreover, in present embodiment, in the sequential that transmission enabling signal RDATA_EN becomes " 1 ", AD conversion result is made to use
The output RESULT_LATCH of register 2 never changes, thereby, it is possible to prevent the result of AD conversion from becoming underrange, from
And the frequency of the clock CLK_REG of ADC 1 can not be improved and protect the result of AD conversion.
In addition, in present embodiment, with higher-order multi-bit, specifically with 3 judgements for having carried out step S2 of high-order, but simultaneously
It is without being limited thereto, moreover it is possible to there is the case where judgement of step S2 is only carried out with highest component level.
[second embodiment]
Next, being illustrated to second embodiment of the present invention.
The AD conversion result reading circuit of second embodiment is used except the AD conversion result used in first embodiment
Other than register 2, and then use AD conversion result register 3.More specifically, the AD conversion result of second embodiment is read
Go out circuit to be characterized in that, in addition to the first AD conversion result is with register 2, and then has the second AD conversion result register
3, the second AD conversion result finishes signal effectively and internal register value with register 3 in the data preparation from ADC 1
When change disable signal READ_ACT_SYNC is effective, the AD conversion of ADC 1 is imported as a result, the first AD conversion result register 2
When internal register value change disable signal READ_ACT_SYNC becomes invalid, the second AD conversion result register 3 is imported
Output.
In present embodiment, the structure of AD conversion result reading circuit is identical with first embodiment, therefore also uses Fig. 1
Symbol illustrate.Fig. 8 be to the action in each portion of the AD conversion result reading circuit of present embodiment illustrate when
Sequence figure.
It is described in reading detection circuit 4, the action of clock change circuit 5 and data transmission circuit 6 such as first embodiment
As bright.
As illustrated in first embodiment, if the data preparation exported from ADC 1 finishes signal DRDY from " 1 "
It is " 0 " (invalid) that (invalid), which falls to " 0 " (effective) and internal register value change disable signal READ_ACT_SYNC, then AD
Transformation result imports the AD conversion result RESULT of ADC 1 with register 2.As a result, output of the AD conversion result with register 2
RESULT_LATCH is updated.
But in second embodiment, when data preparation, which finishes signal DRDY, falls to " 0 " from " 1 ", internal register
Value change disable signal READ_ACT_SYNC has changed into " 1 " (effective), and therefore, the first AD conversion result register 2 can not
Import the AD conversion result RESULT of ADC 1.Thus, the output RESULT_LATCH's of the first AD conversion result register 2
Update becomes can not possibly.That is, in first embodiment, second embodiment, internal register value changes disable signal READ_
The section that ACT_SYNC becomes " 1 " (effective) is that section is forbidden in the change of internal register value.
Therefore, the second AD conversion result register 3 is used in this second embodiment.If that is, the number exported from ADC 1
According to ready signal DRDY " 0 " (effective) and internal register value change disable signal READ_ are fallen to from " 1 " (invalid)
ACT_SYNC is " 1 " (effective), then the second AD conversion result imports the AD conversion result RESULT of ADC 1 with register 3.It is tied
The output RESULT_BUF of fruit, the second AD conversion result register 3 is updated.According to the example of Fig. 8, it is known that RESULT_
BUF is updated to " new " for the transformation result for indicating newly to import.
If internal register value change disable signal READ_ACT_SYNC becomes " 0 " (invalid) from " 1 " (effective), the
One AD conversion result imports the output RESULT_BUF (moment t7) of the second AD conversion result register 3 with register 2.This
The output RESULT_LATCH of sample, the first AD conversion result register 2 is updated.In the example of Fig. 8, it is known that RESULT_
LATCH is updated to " new " for the transformation result for indicating newly to import from " old " of the old transformation result of expression.
Other structures are as illustrated in first embodiment.
In first embodiment, finished in the data preparation exported from ADC 1 interior when signal DRDY falls to " 0 " from " 1 "
In the case that portion register value change disable signal READ_ACT_SYNC has changed into " 1 ", the first AD conversion result register
2 can not import the AD conversion of ADC 1 as a result, being taken it is therefore possible to which the leakage of AD conversion result occurs.In contrast, the second embodiment party
In formula, by the way that the second AD conversion result register 3 is arranged, AD conversion can not be imported in the first AD conversion result register 2
As a result in the case of, the second AD conversion result register 3 has imported AD conversion as a result, therefore, it is possible to avoid AD conversion result
The generation that takes of leakage.
[third embodiment]
Next third embodiment of the present invention is illustrated.Fig. 9 is the AD conversion knot for indicating third embodiment
The block diagram of the structure of fruit reading circuit.In Fig. 9, pair with first embodiment shown in FIG. 1 and the AD conversion of second embodiment
As a result the identical structure of reading circuit assigns same symbol.
The AD conversion result reading circuit of third embodiment includes：AD conversion result register 2, AD conversion result are used
Register 3；Read detection circuit 4a；Clock change circuit 5；Data transmission circuit 6a；Identify data register 8, identification number
According to register 9.
More specifically, the AD conversion result reading circuit of third embodiment removes first embodiment or the second embodiment party
Other than the structure of the AD conversion result reading circuit of formula, and then has the first identification data register 8, the first identification number
According to register 8 signal DRDY is finished in the data preparation from ADC 1 effectively and internal register value change disable signal
When READ_ACT_SYNC is " 0 " (invalid), identification data associated with AD conversion result are imported from ADC 1, data send electricity
Road 6a reads AD conversion knot when it is " 1 " (effective) to send enabling signal RDATA_EN, from the first AD conversion result register 2
Fruit is simultaneously sent to external device (ED), and reads identification Data Concurrent with register 8 from the first identification data and send to external device (ED).
Moreover, the AD conversion result reading circuit of third embodiment has the second identification data register 9, institute in turn
It states the second identification data and finishes signal DRDY effectively and the change of internal register value in the data preparation from ADC 1 with register 9
When more disable signal READ_ACT_SYNC is " 1 " (effective), identification data are imported, the first identification data register 8 can also
When internal register value change disable signal READ_ACT_SYNC becomes " 0 " (invalid), the second identification data deposit is imported
The output of device 9.
In third embodiment, ADC 1 is in addition to AD conversion result RESULT, also output and the AD conversion result
The associated identification data DID of RESULT.
Moreover, detection circuit 4a is read after having sent 24 AD conversion results, in order to send such as 8 identification numbers
The transmission enabling signal RDATA_EN (the step S7 of Fig. 2) of a pulse is sent out according to DID.Data transmission circuit 6a is according to transmission
Enabling signal RDATA_EN, from identification data with register 8 read identification data DID parallel series be sent to SPI hosts 7 (Fig. 2's
Step S8).
In this way, in third embodiment, the processing of the step S7 and step S8 of Fig. 2 are executed repeatedly, until 24 AD turn
Result is changed along with 8 identification data DID, until i.e. 32 data of total are sent.The example of Fig. 3, Fig. 8 are come
It says, after having sent 24 data of D0~D23, sends such as 8 identification data DID.Read other of detection circuit 4a
Action is identical as the reading detection circuit 4 in first embodiment and second embodiment.
Next, being illustrated with the action of register 9 to identification data register 8, identification data.
If the data preparation exported from ADC 1 finishes signal DRDY and falls to " 0 " (effective) and inside from " 1 " (invalid)
It is " 0 " (invalid) that register value, which changes disable signal READ_ACT_SYNC, then it is defeated from ADC 1 to identify that data register 8 is imported
The identification data DID gone out.In this way, the output DID_LATCH of identification data register 8 is updated.
But it is same with register 2 as AD conversion result, identification data are accurate in the data exported from ADC1 with register 8
It is standby when finishing signal DRDY and falling to " 0 " from " 1 ", become in internal register value change disable signal READ_ACT_SYNC
In the case of at " 1 " (effective), identification data DID can not be imported.
On the other hand, if the data preparation exported from ADC 1 finishes signal DRDY and falls to " 0 " and internal deposit from " 1 "
It is " 1 " that device value, which changes disable signal READ_ACT_SYNC, then identifies that data register 9 imports the identification data from ADC 1
DID.In this way, the output DID_BUF of identification data register 9 is updated.
Become from " 1 " moreover, identification data change disable signal READ_ACT_SYNC with register 8 in internal register value
When at " 0 ", the output DID_BUF of identification data register 9 is imported.
Like this, identification data carry out identification data DID with register 8 identical with AD conversion result register 2
Action, identification data carry out action identical with the second AD conversion result register 3 with register 9.
Next, identification data DID is described in detail.As the generation method of identification data DID, such as can illustrate
Following four.
First case is the method that the data of the execution number handled based on AD conversion are set as identification data DID.For example, knowing
Other data are the data of the execution number for the AD conversion processing for indicating ADC 1.Specifically, at 1 inside counting AD conversion of ADC
The count value is simultaneously set as identification data DID by the execution number of reason.Like this, the execution handled by recording AD conversion
Number can identify AD conversion result that the AD conversion executed in a certain sequential is handled and before and after it as identification data DID
Sequential execute AD conversion processing AD conversion result.
Second case is the data at the execution moment that will be handled based on AD conversion, for example indicates to execute AD conversion using ADC 1
The method that data at the time of processing are set as identification data DID.Execution moment that specifically, ADC 1 handles AD conversion (when
Stamp) it is set as identification data DID.
As the specific method at the execution moment for using AD conversion processing, such as can illustrate following two.One is in ADC
The method of 1 internal or external setting real-time clock.Another kind is for example to be arranged to connect power supply inside or outside ADC 1
When the method that is set as the moment 0 and carries out incremental counter every some cycles to replace real-time clock.
According to any one of described two methods, AD turns of the AD conversion processing executed in a certain sequential can be identified
Change the AD conversion result for the AD conversion processing that result and the sequential before and after it execute.In turn, real-time clock is used according to described
Method, be able to record execute AD conversion processing exact time.On the other hand, according to the side without using real-time clock
Method is capable of the increase of suppression circuit scale.
Third example is that 1 data that logic level inverts whenever executing AD conversion processing are set as identification data
The method of DID.That is, identification data DID is logic level inverts whenever executing AD conversion processing using ADC 11
Data.According to the method, the AD conversion result of the AD conversion executed in a certain sequential processing can be identified and before and after it
Sequential execute AD conversion processing AD conversion result.Moreover, because identification data DID is set as 1, necessity can be reduced
Hardware resource, so as to the increase of suppression circuit scale.
4th is to be set as identifying by the data of the count value based on free-running operation counter (free run counter)
The method of data DID.For example, it is also possible to which the free-running operation counter by 8 executes processing to count with what AD conversion was handled
The pulse independently continuously inputted, and the count value is set as identification data DID.Accordingly, the big counting of bit width is not needed
Device, therefore it is capable of the increase of suppression circuit scale.In addition, the data stored as identification data DID may not be freedom
The count value (numerical value) itself for running counter, may be, for example, alphabet known to the sequence of A~Z or the like (alphabet)
(character code).
More than, according to third embodiment, identification data are assigned to each AD conversion result, and by AD conversion result and know
Other data complete (set) export, and are taken therefore, it is possible to judge whether to maintain in 7 side of SPI hosts for receiving AD conversion result
The continuity of the AD conversion result obtained.
Moreover, according to third embodiment, setting the first identification data register 8, and data transmission circuit 6a is coming
When effective from the transmission enabling signal RDATA_EN for reading detection circuit 4a, read and identified with register 8 from the first identification data
Data Concurrent is sent to external device (ED), and thereby, it is possible to the repetition acquirement of AD conversion result or AD conversion knot are judged in external device (ED) side
The leakage of fruit the presence or absence of takes.
In turn, by setting the second identification data register 9, the generation that the leakage of identification data can be avoided to take.
For example, by comparing the identification data for corresponding to acquired AD conversion result and corresponding to immediately in institute before it
The identification data of the AD conversion result of acquirement, equally can 7 side of SPI hosts judge the AD conversion period AD conversion result weight
It is multiple to obtain or the presence or absence of the leakage of AD conversion result takes, i.e., if the continuity of the AD conversion result acquired by maintaining.
In addition, in third embodiment, to using both AD conversion result register 2, AD conversion result register 3
The case where be illustrated, but AD conversion result register can also be used only as illustrated in first embodiment
2.As described above, in first embodiment, it is possible to which the leakage that AD conversion result occurs takes, but according to second embodiment and third
Embodiment can judge that this leakage takes in 7 side of SPI hosts.
Industrial availability
The present invention can be applied to not consider the change-over period of AD converter and the technology that reads AD conversion result.
The explanation of symbol
1：AD converter
2,3：AD conversion result register
4,4a：Read detection circuit
5：Clock change circuit
6,6a：Data transmission circuit
7：SPI hosts
8,9：Identify data register
50,51：Trigger
Claims (9)
1. a kind of AD conversion result reading circuit, it is characterised in that including：
Detection circuit, when the order for the external device (ED) for receiving the sending destination from the AD conversion result as AD converter
High-order position and be determined as that the order keeps the detection signal synchronous with the clock of the external device (ED) effective when being read-out command,
When receive the order whole from the external device (ED) and be determined as it is described order be the read-out command when make transmission
Enabling signal is effective；
Clock change circuit exports the internal register value synchronous with the clock of the AD converter according to the detection signal
Change disable signal；
First AD conversion result register, when the data preparation from the AD converter finish signal effectively and it is described in
When portion's register value change disable signal is invalid, the AD conversion result of the AD converter is imported；And
Data transmission circuit reads institute when the transmission enabling signal is effective from the first AD conversion result register
It states AD conversion result and is sent to the external device (ED).
2. AD conversion result reading circuit according to claim 1, which is characterized in that the AD conversion result reading circuit
In,
And then include：Second AD conversion result register, when the data preparation from the AD converter finish signal effectively,
And internal register value change disable signal it is effective when, import the AD conversion of the AD converter as a result, and
The first AD conversion result register imports institute when internal register value change disable signal becomes invalid
State the output of the second AD conversion result register.
3. AD conversion result reading circuit according to claim 1 or 2, which is characterized in that the AD conversion result is read
In circuit,
And then include：First identification data register, when the data preparation from the AD converter finish signal effectively and
When internal register value change disable signal is invalid, imported from the AD converter associated with the AD conversion result
Identify data, and
The data transmission circuit is read from the first AD conversion result with register when the transmission enabling signal is effective
The AD conversion result is simultaneously sent to the external device (ED), and reads the identification from the first identification data register
Data Concurrent is sent to the external device (ED).
4. AD conversion result reading circuit according to claim 3, which is characterized in that the AD conversion result reading circuit
In,
And then include：Second identification data register, when the data preparation from the AD converter finish signal effectively and
When internal register value change disable signal is effective, the identification data are imported, and
The first identification data register is when internal register value change disable signal becomes invalid, described in importing
The output of second identification data register.
5. AD conversion result reading circuit according to any one of claim 1 to 4, which is characterized in that the AD conversion
As a result in reading circuit,
The detection circuit is whole when receiving the order from the external device (ED) after keeping the detection signal effective
And when being determined as the not read-out command, make the detection invalidating signal.
6. AD conversion result reading circuit according to any one of claim 1 to 5, which is characterized in that the AD conversion
As a result in reading circuit,
The identification data are the data of the execution number for the AD conversion processing for indicating the AD converter.
7. AD conversion result reading circuit according to any one of claim 1 to 5, which is characterized in that the AD conversion
As a result in reading circuit,
The identification data are to indicate to execute data at the time of AD conversion is handled using the AD converter.
8. AD conversion result reading circuit according to any one of claim 1 to 5, which is characterized in that the AD conversion
As a result in reading circuit,
The identification data are logic level inverts whenever executing AD conversion processing using the AD converter 1
Data.
9. AD conversion result reading circuit according to any one of claim 1 to 5, which is characterized in that the AD conversion
As a result in reading circuit,
The identification data are the data of the count value based on free-running operation counter.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016040667A JP6499602B2 (en) | 2016-03-03 | 2016-03-03 | AD conversion result reading circuit |
| JP2016-040667 | 2016-03-03 | ||
| PCT/JP2017/007642 WO2017150491A1 (en) | 2016-03-03 | 2017-02-28 | A-d conversion result readout circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108780385A true CN108780385A (en) | 2018-11-09 |
| CN108780385B CN108780385B (en) | 2021-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780014289.4A Active CN108780385B (en) | 2016-03-03 | 2017-02-28 | Analog-to-digital conversion result reading circuit |
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| Country | Link |
|---|---|
| JP (1) | JP6499602B2 (en) |
| KR (1) | KR102035768B1 (en) |
| CN (1) | CN108780385B (en) |
| WO (1) | WO2017150491A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040114670A1 (en) * | 2002-12-13 | 2004-06-17 | International Business Machines Corporation | System and method for transmitting data and additional information simultaneously within a wire based communication system |
| CN1868155A (en) * | 2003-08-13 | 2006-11-22 | 英特尔公司 | Universal adaptive synchronization scheme for distributed audio-video capture on heterogeneous computing platforms |
| US20070035433A1 (en) * | 2005-06-30 | 2007-02-15 | Sigmatel, Inc. | System and method for scheduling access to an analog-to-digital converter and a microprocessor |
| CN102314402A (en) * | 2011-07-29 | 2012-01-11 | 中国地震灾害防御中心 | Digital strong motion seismograph and multipath data acquisition interface thereof |
| JP2014132418A (en) * | 2013-01-07 | 2014-07-17 | Renesas Electronics Corp | Semiconductor device and command control method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4661718B2 (en) * | 2006-07-25 | 2011-03-30 | 株式会社デンソー | A / D converter |
| JP2016040647A (en) * | 2014-08-12 | 2016-03-24 | アズビル株式会社 | Analog/digital conversion circuit |
-
2016
- 2016-03-03 JP JP2016040667A patent/JP6499602B2/en active Active
-
2017
- 2017-02-28 KR KR1020187024599A patent/KR102035768B1/en active IP Right Grant
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- 2017-02-28 WO PCT/JP2017/007642 patent/WO2017150491A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040114670A1 (en) * | 2002-12-13 | 2004-06-17 | International Business Machines Corporation | System and method for transmitting data and additional information simultaneously within a wire based communication system |
| CN1868155A (en) * | 2003-08-13 | 2006-11-22 | 英特尔公司 | Universal adaptive synchronization scheme for distributed audio-video capture on heterogeneous computing platforms |
| US20070035433A1 (en) * | 2005-06-30 | 2007-02-15 | Sigmatel, Inc. | System and method for scheduling access to an analog-to-digital converter and a microprocessor |
| CN102314402A (en) * | 2011-07-29 | 2012-01-11 | 中国地震灾害防御中心 | Digital strong motion seismograph and multipath data acquisition interface thereof |
| JP2014132418A (en) * | 2013-01-07 | 2014-07-17 | Renesas Electronics Corp | Semiconductor device and command control method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108780385B (en) | 2021-08-17 |
| KR20180108723A (en) | 2018-10-04 |
| JP2017157060A (en) | 2017-09-07 |
| JP6499602B2 (en) | 2019-04-10 |
| WO2017150491A1 (en) | 2017-09-08 |
| KR102035768B1 (en) | 2019-10-24 |
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