TW421792B - Built-in self-test circuit of memory device - Google Patents

Abstract

This invention is about built-in self-test (BIST) circuit of memory device. For providing full-speed test, the operation speed of BIST circuit must match the testing speed of memory. Conventionally, a finite state machine is used for the test procedure generated by a set of predefined test evolution. If only using this finite state machine, the bottleneck of function performance will occur. For eliminating this bottleneck, we propose high-speed technique based on prediction logic. By using a prediction logic, certain specific signals of the clock threshold routes can be calculated before a clock cycle. By disposing flip-flop in these signals to break these threshold routes, the clock cycle time is reduced. Our synthetic results indicate that the proposed technique can be used to reduce the clock cycle time up to 30% and a 400 MHz design using 0.35 mu m CMOS cell program base is then introduced.

Description

Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 421792 A7 4430twf.doc / 008 β V. Description of the invention (() The present invention relates to a test hardware for a memory, and in particular to a built-in Test circuit 'This built-in self-test circuit is embedded on the same chip as this memory system. During the manufacturing process of the memory, the process is caused by dust particles, scratches, and pinholes on the oxide layer of the chip or the screen. . Error, often easy to affect the memory of the billion, resulting in improper open or short circuit. At present, many methods or hardware have been developed to test the normal operation of the memory. However, as the integrated circuit technology changes with each day Memory functions are also becoming more and more complicated. Therefore, the time required to test the memory functions is relatively increased, and its test circuit is relatively complicated. In order to solve the above problems, the built-in self-test of the memory has been developed (Built -in self-test; BIST) technology. When performing the test of the built-in self-test technology of the memory, a deduction is converted into a finger , Data and address sequence, and applied to the memory. Traditionally, this conversion process is usually implemented using a finite state machine. In order to perform full speed testing, the BIST circuit operates like a memory during the test Quick. One of the disadvantages of this method is that the finite state machine will be modified into a specific set of test modes. The complexity of these side-view modes depends on the test interpretation. When the complexity of the test interpretation increases, this method cannot Applicable 'because finite state machines become large and slow in each clock cycle during testing, so that they cannot generate a test mode. Some BIST circuits, which are generally known as programmable or configurable BIST circuits, can Refer to US Patent No. 5,173,906, "Built-in Self-Test of Integrated Circuits", disclosed by Dreibelbis et al., 1992. 3 (谙 Please read the notes on the back before filling this page) Order-r ,. This paper Applicable to Chinese National Standards (CNS > A4 specification (210X297 male)) 42Π92 Α7 4430twf.doc / 008 B7 Central Ministry of Economic Affairs Printed by the Consumer Bureau of the Prospective Bureau. 5. Description of the invention (1) Another type of circuit has been disclosed that uses microcoded sequences defined by the contents of read-only memory to create test patterns. Issued No. 5,224,101. In U.S. Patent No. 5,301,156, "Configurable Self-Test of Embedded Random Access Memory", Talley et al. Disclosed a circuit with a series path that passes through the bits of the circuit. Address, instruction and data part to input a test or control mode and output the result, and each scan takes several clock cycles. The invention provides a circuit and method for testing memory, especially for Test memory components. This circuit includes a test pattern generator, a built-in self-test output buffer, a delay buffer, and a comparator. The test pattern generator further includes three modules; a finite state machine to generate data and test patterns; a bit generator to perform address calculations; and a prediction logic to use the bits from the previous cycle Address information to predict the address of the next clock cycle. The invention uses a periodic path interruption technique. The flip-flop is configured on the original critical path of the mode generator, and the original critical path is cut into several steps. Therefore, the clock cycle time of the pattern generator depends on the longest clock cycle time among these segments. However, when these flip-flops are placed behind the original critical path, a delay occurs. In order to correct the delay of the clock cycle caused by adding the flip-flops, in the present invention, a prediction logic is used, which is arranged between the two flip-flops. Therefore, the time cycle time of the mode generator can be effectively reduced, and the delay caused by the flip-flop is also solved. Brief description of the drawings-4 This paper size is applicable to the Chinese National Standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back before filling this page), and install.-Order ♦ Staff of the Central Bureau of Standards, Ministry of Economic Affairs Printed by a consumer cooperative 42Π92 A7 4430twf.doc / 00S 37 V. Description of the Invention (々) In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following exemplifies preferred embodiments and cooperates with all The drawings are described in detail as follows: Figure 1 shows a block diagram of a built-in self-test circuit for testing memory components; Figures 2 (a) to 2 (c) show built-in Schematic diagram of the evolution of a pattern generator in a self-test circuit; Figure 2 (a) is a simple pattern generator; Figure 2 (b) is a pattern generator after retiming; and Figure 2 (c) FIG. 3 is a high-speed pattern generator; FIG. 3 is a state change diagram of a step operation of a prediction logic; and FIG. 4 is a register transfer stage of a prediction logic. Description of the graphical symbols: 10, 20, 30: Address register Example When testing a memory component, the test operation is usually written in a high-level programming language. Consider a memory element pair-wise test that includes rows A and C. The step-by-step operation includes four steps. In the first step, '0' is written to each memory cell. The second step is to perform a read-write-read operation on the entire memory array in a positive manner, that is, from the first memory cell in the first row to the last memory cell in the last row. In each memory cell, the requested read (0) -write (1) -read (1) operation is performed. This read-write-read operation can show the potential dynamics of the memory cell. 5 The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page. ) 3 Xu A7 421792 4430twf.doc / 008 B7 V. Description of the Invention (仏) (Please read the notes on the back before filling this page) Defects. The third step goes from the last memory cell, passes through all the memory cells, and walks back to the first memory cell, and in each memory cell, reads out (1) -writes (〇)-reads out (〇) operating. The fourth step is to check whether the memory of each memory cell is still zero after the first three steps are performed. This step operation can be compiled into a high-level language program. Here is an example. {/ * — Step 1: write 0 to each cell… * / foreach_row (i ~ 0; i <R; i ++) {foreach_col (j ^ 0; j <C; j ++) {Write 0 to cell (i, j) }} — Step 2: change each cell from 0 to 1 in a forward maimer… * / foreach_row (i = 0; i <R; i ++) {foreach_col (j = 0; j <C;

Read 0 from cell (i3 j)

Write 1 to cell (i, j);

Read 1 from cell (i, j)} Printed by Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs step 3: change each cell from 1 to 0 in a backward manner --- * / foreach—row (i = 7? -L ; i > = 0; i-) {foreach_col (j = (Cl); j >〇; j—

Read 1 fromcell (ij)

Write 0 to cell (ij);

Read 0 from cell (i, j)} 6 This paper ruler applies Chinese National Standard (CNS) A4 (21 297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 421792 4430twf.doc / 008 V. Description of the invention (s) /*...step 4: read 0 to each cell… V foreach_row (i = 0; i < / ?; i ++) {foreach_col (j = 0; j <C; j ++) {Read 0 to cell ( i, j)} Built-in self-test circuit The present invention discloses a built-in self-test circuit. As shown in Figure 1, the built-in self-test circuit includes a pattern generator, a built-in self-test circuit (BIST) output buffer (BOB), a delay buffer, and a comparator. . The pattern generator is a finite state machine that can generate a sequence of test patterns related to the above-mentioned test operations. bob is a buffer located between the BIST circuit and the memory element, such as a static random access memory (SRAM), to eliminate the potential characteristics degradation caused by the BIST circuit. The delay buffer is a first-in, first-out register, located between the pattern generator and the comparator. The main purpose is to calculate the expected response to a memory read instruction. The delay clock period depends on the delay time of the memory READ operation. The comparator is a combinational logic that compares the output response after the memory test with the expected response to determine whether the memory function and operation are normal. The expected response is provided by the delay buffer. Among the four components of the BIST circuit, the wedge generator is the component that mainly determines the clock cycle time. Interrupt techniques for timing critical paths are described below. Figures 2 (a) to 2 (c) show the inner paper size shown in Figure 1 of the present invention. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the back (Please fill in this page again)

421T92 A7 4430twf.doc / 〇〇8 gy Fifth, the invention description (6) is placed in the fj test circuit, an evolution diagram of a pattern generator. Fig. 2 (a) shows the structure of a simple pattern generator. As mentioned earlier, the pattern generator is responsible for generating test patterns, where each test pattern includes data, instructions, and addresses. The pattern generator can thus be divided into two modules, that is, a finite state machine, marked with, and a bit generator, marked with ⑼. As shown in the figure, the module generates the command part and data part of the test mode, and an address command, which is marked with the Comm address address command system to drive the module. "It is responsible for generating each test mode. Address part. In this embodiment, there are nine address instructions for conforming to various different test operations. The nine address instructions include NO_CHANGE, INIT_ADDRESS, LAST_ADDRESS, NEXT CELL, PREVIOUS CELL, Y NEXT CELL, — · _ — a Y_PREVIOUS_CELL 'CROSS — CELL' and RECALL ° According to each address instruction, the module « The address register 10 is updated every clock cycle. In this architecture, it can be seen that the timing critical path starts from the output of the address register 10, passes through the combination part of the module user «, and finally ends at the input of the address register 10. In addition, the pattern generator also includes the original state register for the finite state machine, which is marked with the print from the Central Standards Bureau of the Ministry of Economic Affairs of the Bayer Consumer Cooperative (please read the precautions on the back before filling out this page) pg_state. Retiming transformation is proposed as an effective timing optimization device. However, this is not applicable by design because the threshold path actually forms a loop. Figure 2 (b) shows an example of retiming transformation. The retiming address register 10 moves backwards past the module ⑼. In this type of retiming, the timing critical path will be slightly changed, but the clock cycle time is still 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 male f A7 B7 421T92

4430t \ vf.doc / 00S V. Description of the invention (1) It mainly depends on the sum of the propagation delays of the combined parts through AND. The motivation of the technology of the present invention is to use a register between the modules and between them to interrupt the cycle path. This idea leads to a new architecture as shown in Figure 2 (c). In addition to the two combination modules PGjV w and _4_g⑼, there are four registers and another combination logic in the new architecture. These four registers include the original state register pgjiaie; the original cell address register 10; the register, which represents the address instruction generated from the corpse; and the register heart, which represents the time when the performance is single. One cell address of the pulse cycle delay. The delay is due to the register that was added to the signal Mdrea. This newly added combination module, called prediction logic, is a very important part of this technology. The purpose is to predict the address of the next clock cycle based on the address information of the previous clock cycle. Accordingly, the timing improvement form is equivalent to the original form. Assume that in the first six clock cycles, the cell addresses of the original pattern generator are Al, A2, A3, A4, A5, and A6. Please note that these addresses do not have to be continuous. The signal quantities of the three monitoring points in the high-speed form, the register, the output of the prediction logic, and the register are listed in Table 1. 9 This paper size applies to China Tujia Standard (CNS > A4 size (210X297mm) (Please read the precautions on the back before filling out this page)-Order-ri \ Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives 42Π92 A7 4430twf.doc / 008 B7 V. Description of the invention (1) Clock cycle 1 2 3 4 5 6 Original address A1 Α2 A3 Α4 Α5 Α6 Speed-delayed address_ Α1 Α2 A3 Α4 Α5 Predicted address — A3 Α4 Α5 Α6 Α7 Address Α2 A3 Α4 Α5 Α6 Table 1 (Please read the precautions on the back before filling this page)-Equipment · For example, in the second clock cycle, the current address is A2, and the prediction logic is The input is a delayed A1. Based on the functional description of the prediction logic described earlier, its output should be the address of the next clock cycle, which is A3. This address will be input by the other module PGjw before it is input. The register is delayed, so the address input to / is still the current address A2, which is the same as in the original form of the pattern generator. In this example, the prediction logic needs A1 to predict A3. This can be achieved Because of the test operation The following sequence of address changes is defined in advance. The following shows how the prediction logic is performed. The execution method of more complex test deductions can also be derived in a similar way. In order to simplify the description without losing generality 'Assume that the memory array is a one-dimensional array with N memory cells. The state transition diagram of the half-step operation is shown in Figure 4', where the variable a marked on the transistor represents the cell address. Except In addition to the START and END states, there are five states in the picture, namely S1, S2, S3, S4, and S5. Each paper size of 10 papers applies the Chinese National Standard (CNS) A4 specification (21〇 > < 297 male thin)

、 1T Printed bag of the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs d 21 92 4430twf.doc / 008 V. Description of the invention (sentence) Each state generates a unique test instruction With data as indicated in each cycle. The RTL code of the predictive logic is shown in Figure 4. In summary, the present invention provides a built-in self-test circuit for testing a memory element. The most important part of the clock cycle timing is the mode generator. The pattern generator includes a finite-state machine corpse GJm, a smoke address generator, a predictive logic, and a set of three flip-flops, that is, a 'primary cell address register and a single address instruction register. And a de / noise for the delayed single-clock cycle cell address. In this method, the timing critical path will be broken into three paragraphs, Xjert 'and prediction logic. In this method, the clock cycle time is determined by the path between, meaning, and prediction logic. Compared with the loop of the simple mode generator, the clock cycle time is effectively reduced. Although there is a waiting time due to the increased configuration of the registers, the signals of these registers are pre-calculated by the prediction logic for a clock period. Synthetic results The present invention is implemented as a register transfer level (RTL) code. It is simulated with a functional model of the memory element during the test to establish the credibility of its functional modification. The synthesis tool, design compilation, is used to convert the RTL code into a net list, and uses the 0.35 wmCMOS technology library for logic optimization. The static timing analysis tool, that is, set time, shows that the clock cycle time is below 2.Sns. A timing-driven feature of the place and route tool, Apo 110, is used to generate the place. Based on these results, we can therefore make the following conclusions: The BIST architecture proposed by the present invention has a very large paper size that is applicable to Chinese national standards (CNS > A4 specification (210X297 mm), -β (Please read the precautions on the back first) (Fill in this page again)

421792 A7 4430twf.doc / 008 V. Description of the invention (γ) The large potential can be run at a speed of 400MΗζ, which is about 30% faster than the simple implementation without proper technology. After considering this specification and practicing the invention disclosed therein ', those skilled in the art will find other possible embodiments of the invention. Herein, this description and its embodiments are only for illustration purposes. 'Any person skilled in the art can make various modifications without departing from the spirit and scope of the present invention'. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application scope. (Please read the precautions on the back before filling in this page.) Order Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, This paper size it shawl (CNS) M brewing (21〇 > < 1 ^ chu)

Claims (1)

Printed by 421792 Bismuth C8 4430t \ vf.doc / 00S D8 in the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6. Application scope \ i. A built-in self-test circuit for a memory element, including: a pattern generator, more Including: a finite state machine for generating an instruction part and a data part of a test mode; a bit generator for generating an address part of the test mode; a prediction logic for A bit address of the previous clock cycle predicts the address of a clock cycle after the previous clock cycle; an output buffer is used as a buffer between the built-in self-test circuit and the memory element A delay buffer to delay an expected memory response; and a comparator to compare an output response of the memory element with the expected memory response provided by the delay buffer to determine the memory Whether the function of the component is normal. 2. The built-in self-test circuit of a memory element as described in item 1 of the scope of patent application, wherein the memory element includes a static random access memory. 3. The built-in self-test circuit of a memory element as described in item 1 of the scope of the patent application, wherein the test mode is generated based on a memory instruction sequence defined by the memory element. '4. The built-in self-test circuit of a memory element as described in item 1 of the scope of the patent application, wherein the register is embedded between the finite state machine, the address generator, and the prediction logic. 5. — A pattern generator for the built-in self-testing of a memory element ____________0! (Please read the precautions on the back before filling this page) The paper bearing standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 (Mm) 8 8 8 8 ABCD 421792 4430twf.doc / 00S VI. Patent application test circuit, the pattern generator includes: a finite state machine, used to generate an instruction part and a data part of a test mode; A bit generator is used to generate an address portion of the test mode; and a prediction logic is used to predict a clock period after a previous clock period based on a bit address of a previous clock period. Address. 6. The pattern generator described in item 5 of the scope of patent application, further comprising: a one-bit instruction register configured in the finite state machine; a delayed address register configured in the address generator And the prediction logic; and an original address generator configured between the prediction logic and the finite state machine. (Please read the precautions on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 14 This paper size applies to China National Standards (CNS) A4 (210X297 mm)