CN107399714A - A kind of silicon chip and the method for sapphire sheet Direct Bonding - Google Patents
A kind of silicon chip and the method for sapphire sheet Direct Bonding Download PDFInfo
- Publication number
- CN107399714A CN107399714A CN201710667043.9A CN201710667043A CN107399714A CN 107399714 A CN107399714 A CN 107399714A CN 201710667043 A CN201710667043 A CN 201710667043A CN 107399714 A CN107399714 A CN 107399714A
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- CN
- China
- Prior art keywords
- silicon chip
- sapphire sheet
- bonding
- stress relief
- relief grooves
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
A kind of method that the present invention discloses silicon chip and sapphire sheet Direct Bonding, comprises the following steps：1) silicon chip and sapphire sheet after polishing, one side or two-sided etching stress relief grooves in the silicon chip are prepared；2) to having the face of stress relief grooves to carry out plasma-activated processing on the silicon chip, plasma-activated processing is carried out to the one side of the sapphire sheet；3) fitting relative with the face in the sapphire sheet Jing Guo plasma-activated processing of the face on the silicon chip Jing Guo plasma-activated processing is bonded in advance；4) silicon chip after pre- bonding and sapphire sheet are made annealing treatment, silicon chip and sapphire sheet is bonded completely.The present invention etches stress relief grooves on the silicon chip, in the case where annealing temperature is higher, can discharge thermal stress Relatively centralized at stress relief grooves, silicon chip is set to be ftractureed along stress relief grooves, so as to prevent the random fragmentation of silicon chip, bonding quality is improved, is easy to make electronic device on silicon chip after bonding.
Description
Technical field
The present invention relates to a kind of silicon chip and the method for sapphire sheet Direct Bonding.
Background technology
In MEMS（Micro-Electro-Mechanical System）Processing technology in, it will usually using silicon chip key
Conjunction technology, it is exactly one of common wafer bonding technology that silicon chip is bonded with sapphire sheet, after the completion of silicon chip is bonded with sapphire sheet,
Different electronic devices is made on silicon chip again（Such as pressure sensor）.Prior art is direct in progress silicon chip and sapphire sheet
, it is necessary to which silicon chip and sapphire sheet are made annealing treatment during bonding, annealing temperature is higher, being bonded between silicon chip and sapphire sheet
Quality is better.However, because silicon and sapphire linear expansion coefficient gap are larger, caused thermal stress is larger in annealing process, moves back
Fiery temperature is higher, and thermal stress is bigger.When annealing temperature is more than 250 DEG C, it is random that sufficiently large thermal stress easilys lead to silicon chip
Then fragmentation, greatly reduce the product qualified rate of bonding.And when annealing temperature is less than 250 DEG C, bonding quality is relatively low, it is impossible to reaches
To the making demand of many electronic devices.Therefore, it is necessary to a kind of new method is provided to solve the above problems.
The content of the invention
Silicon chip and annealing temperature during sapphire sheet Direct Bonding can be improved it is an object of the invention to provide a kind of, together
When ensure bonding quality silicon chip and sapphire sheet Direct Bonding method.
To achieve these goals, the technical solution adopted in the present invention is as follows：
A kind of silicon chip and the method for sapphire sheet Direct Bonding, comprise the following steps：
1) silicon chip after polishing and the sapphire sheet after polishing, one side or two-sided etching stress release in the silicon chip are prepared
Groove, the stress relief grooves include at least one the first cell bodies and at least one the second cell bodies, any one first cell body
Intersect with any one second cell body；
2) to having the face of stress relief grooves to carry out plasma-activated processing on the silicon chip, to the one side of the sapphire sheet
Carry out plasma-activated processing；
3) plasma-activated place will be passed through on the face on the silicon chip Jing Guo plasma-activated processing and the sapphire sheet
The relative fitting in the face of reason is bonded in advance；
4) silicon chip after pre- bonding and sapphire sheet are made annealing treatment, silicon chip and sapphire sheet is bonded completely, during annealing
Keeping temperature be 250-450 DEG C, retention time during annealing is 5-12 hours.
Preferably, all first cell bodies are parallel to each other, and all second cell bodies are parallel to each other, first cell body
Vertical second cell body.
Preferably, the distance between every two neighboring described first cell body is not all equal, per two neighboring described second
The distance between cell body is not all equal.
Preferably, in step 3）In, include pressurization and heat treatment during bonding in advance.
Compared with prior art, silicon chip of the present invention and the beneficial effect of the method for sapphire sheet Direct Bonding are：This hair
It is bright to etch stress relief grooves on the silicon chip, in the case where annealing temperature is higher, thermal stress can be made in stress relief grooves
Locate Relatively centralized release, silicon chip is ftractureed along stress relief grooves, so as to prevent the random fragmentation of silicon chip, improve bonding matter
Amount, is easy to make electronic device on silicon chip after bonding.
Brief description of the drawings
Fig. 1 is the structural representation after silicon chip of the present invention is bonded in advance with sapphire sheet；
Fig. 2 is the structural representation of silicon chip of the present invention.
Each mark is as follows in figure：1st, silicon chip；101st, stress relief grooves；2nd, sapphire sheet.
Embodiment
The present invention is further described below with reference to specific embodiment.
Embodiment one：
A kind of silicon chip 1 and the method for the Direct Bonding of sapphire sheet 2, comprise the following steps：
1) silicon chip 1 after polishing and the sapphire sheet 2 after polishing, one side or two-sided etching stress in the silicon chip 1 are prepared
Release groove 101, the stress relief grooves 101 include at least one the first cell bodies and at least one the second cell bodies, any one institute
The first cell body is stated with any one second cell body to intersect；
2) to having the face of stress relief grooves 101 to carry out plasma-activated processing on the silicon chip 1, to the sapphire sheet 2
One side carry out plasma-activated processing；
3) it is the face on the silicon chip 1 Jing Guo plasma-activated processing is plasma-activated with passing through in the sapphire sheet 2
The relative fitting in the face of processing is bonded in advance；
4) silicon chip 1 after pre- bonding and sapphire sheet 2 are made annealing treatment, silicon chip 1 and sapphire sheet 2 is bonded completely, move back
Keeping temperature when fiery is 250 DEG C, and retention time during annealing is 5 hours.
Embodiment two：
A kind of silicon chip 1 and the method for the Direct Bonding of sapphire sheet 2, comprise the following steps：
1) silicon chip 1 after polishing and the sapphire sheet 2 after polishing, one side or two-sided etching stress in the silicon chip 1 are prepared
Release groove 101, the stress relief grooves 101 include at least one the first cell bodies and at least one the second cell bodies, any one institute
The first cell body is stated with any one second cell body to intersect；
2) to having the face of stress relief grooves 101 to carry out plasma-activated processing on the silicon chip 1, to the sapphire sheet 2
One side carry out plasma-activated processing；
3) it is the face on the silicon chip 1 Jing Guo plasma-activated processing is plasma-activated with passing through in the sapphire sheet 2
The relative fitting in the face of processing is bonded in advance；
4) silicon chip 1 after pre- bonding and sapphire sheet 2 are made annealing treatment, silicon chip 1 and sapphire sheet 2 is bonded completely, move back
Keeping temperature when fiery is 450 DEG C, and retention time during annealing is 12 hours.
Embodiment three：
A kind of silicon chip 1 and the method for the Direct Bonding of sapphire sheet 2, comprise the following steps：
1) silicon chip 1 after polishing and the sapphire sheet 2 after polishing, one side or two-sided etching stress in the silicon chip 1 are prepared
Release groove 101, the stress relief grooves 101 include at least one the first cell bodies and at least one the second cell bodies, any one institute
The first cell body is stated with any one second cell body to intersect；
2) to having the face of stress relief grooves 101 to carry out plasma-activated processing on the silicon chip 1, to the sapphire sheet 2
One side carry out plasma-activated processing；
3) it is the face on the silicon chip 1 Jing Guo plasma-activated processing is plasma-activated with passing through in the sapphire sheet 2
The relative fitting in the face of processing is bonded in advance；
4) silicon chip 1 after pre- bonding and sapphire sheet 2 are made annealing treatment, silicon chip 1 and sapphire sheet 2 is bonded completely, move back
Keeping temperature when fiery is 400 DEG C, and retention time during annealing is 11 hours.
When one piece of silicon chip 1 needs to be bonded one piece of sapphire sheet 2, in step 1）In, in the list of the silicon chip 1
Facet etch stress relief grooves 101；When one piece of silicon chip 1 needs to be bonded two pieces of sapphire sheets 2, in step 1）In,
The two-sided etching stress relief grooves 101 of the silicon chip 1, in step 3）In, the positive and negative of the silicon chip 1 respectively with one piece of sapphire
Piece 2 is bonded in advance.
In addition, the present invention includes pressurization and heat treatment, Neng Gouti when being bonded in advance to silicon chip 1 and sapphire sheet 2
High pre- bonding effect.After silicon chip 1 is bonded completely with sapphire sheet 2, silicon chip 1 is opened along first cell body and the second cell body
Split, the silicon chip 1 is separated into some silicon chips for being used to make different electronic devices and added by first cell body and the second cell body
Work block, need on different silicon chip processing blocks the electronic device species that makes different, size is not also all identical, therefore, per adjacent
The distance between two described first cell bodies are not all equal, inwhole phases the distance between per two neighboring described second cell body
Deng.
In specific application, all first cell bodies are parallel to each other, and all second cell bodies are parallel to each other, and described
Vertical second cell body of one cell body.This structure design can make in the case of ensureing that each piece of silicon chip processing block is complete
Thermal stress relatively evenly discharges.
In summary, the present invention etches stress relief grooves 101 on the silicon chip 1, in the case where annealing temperature is higher,
It can discharge thermal stress Relatively centralized at stress relief grooves 101, silicon chip 1 is ftractureed along stress relief grooves 101, so as to anti-
Only 1 random fragmentation of silicon chip, bonding quality is improved in the case of ensureing that each piece of silicon chip processing block is complete, is easy at each piece
Electronic device is made on silicon chip processing block.
Schematically the present invention and embodiments thereof are described above, this describes no restricted, institute in accompanying drawing
What is shown is also one of embodiments of the present invention, and actual structure is not limited thereto.So if common skill of this area
Art personnel are enlightened by it, without departing from the spirit of the invention, without designing and the technical scheme for creativeness
Similar frame mode and embodiment, protection scope of the present invention all should be belonged to.
Claims (4)
1. a kind of silicon chip and the method for sapphire sheet Direct Bonding, it is characterised in that comprise the following steps：
1) silicon chip after polishing and the sapphire sheet after polishing, one side or two-sided etching stress release in the silicon chip are prepared
Groove, the stress relief grooves include at least one the first cell bodies and at least one the second cell bodies, any one first cell body
Intersect with any one second cell body；
2) to having the face of stress relief grooves to carry out plasma-activated processing on the silicon chip, to the one side of the sapphire sheet
Carry out plasma-activated processing；
3) plasma-activated place will be passed through on the face on the silicon chip Jing Guo plasma-activated processing and the sapphire sheet
The relative fitting in the face of reason is bonded in advance；
4) silicon chip after pre- bonding and sapphire sheet are made annealing treatment, silicon chip and sapphire sheet is bonded completely, during annealing
Keeping temperature be 250-450 DEG C, retention time during annealing is 5-12 hours.
2. silicon chip as claimed in claim 1 and the method for sapphire sheet Direct Bonding, it is characterised in that all first grooves
Body is parallel to each other, and all second cell bodies are parallel to each other, vertical second cell body of first cell body.
3. silicon chip as claimed in claim 2 and the method for sapphire sheet Direct Bonding, it is characterised in that per two neighboring described
The distance between first cell body is not all equal, and the distance between every two neighboring described second cell body is not all equal.
4. silicon chip as claimed in claim 1 and the method for sapphire sheet Direct Bonding, it is characterised in that in step 3）In, in advance
Include pressurization and heat treatment during bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710667043.9A CN107399714A (en) | 2017-08-07 | 2017-08-07 | A kind of silicon chip and the method for sapphire sheet Direct Bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710667043.9A CN107399714A (en) | 2017-08-07 | 2017-08-07 | A kind of silicon chip and the method for sapphire sheet Direct Bonding |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107399714A true CN107399714A (en) | 2017-11-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710667043.9A Pending CN107399714A (en) | 2017-08-07 | 2017-08-07 | A kind of silicon chip and the method for sapphire sheet Direct Bonding |
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| CN (1) | CN107399714A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109678107A (en) * | 2018-12-03 | 2019-04-26 | 华中科技大学 | A kind of bonding monocrystalline silicon and sapphire method |
| CN115028141A (en) * | 2022-08-11 | 2022-09-09 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Sapphire wafer direct bonding method of sapphire pressure sensitive structure |
-
2017
- 2017-08-07 CN CN201710667043.9A patent/CN107399714A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109678107A (en) * | 2018-12-03 | 2019-04-26 | 华中科技大学 | A kind of bonding monocrystalline silicon and sapphire method |
| CN115028141A (en) * | 2022-08-11 | 2022-09-09 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Sapphire wafer direct bonding method of sapphire pressure sensitive structure |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20171128 |
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| WD01 | Invention patent application deemed withdrawn after publication |