CN107395167B

CN107395167B - Broadband adjustable real-time delay line circuit

Info

Publication number: CN107395167B
Application number: CN201710559717.3A
Authority: CN
Inventors: 李文渊; 陈阳; 王晏清
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2017-07-10
Filing date: 2017-07-10
Publication date: 2020-07-31
Anticipated expiration: 2037-07-10
Also published as: CN107395167A

Abstract

The invention discloses a broadband adjustable real-time delay line circuit which comprises a plurality of cascaded coarse delay structures, wherein each coarse delay structure comprises a pair of passive delay units and an active path amplifier, each passive delay unit consists of an inductor and a capacitor, and the active path amplifier is bridged between the output ends of the pair of passive delay units and is used as a control switch to control the delay time of the delay line circuit. Selecting a corresponding active amplifier through a switch to be conducted, changing a signal transmission path, and carrying out coarse adjustment on time delay; the fine adjustment of the time delay is carried out by adjusting the bias circuit of the active path amplifier, and the continuous change of the time delay of the fine adjustment and the coarse adjustment is realized. The circuit has the advantages of wide bandwidth, continuously adjustable delay, wide delay variation range, low power consumption and the like.

Description

Broadband adjustable real-time delay line circuit

Technical Field

The invention relates to a delay line circuit, in particular to a broadband adjustable real-time delay line circuit.

Background

With the increasing demand of wireless communication systems for signal transmission rate, the multi-antenna broadband beam forming technology becomes more and more important, and the real-time delay line circuit has become a key module that affects the signal receiving range and data transmission throughput. The delay resolution, the delay range, the working bandwidth of the signal and other indexes of the delay line circuit determine the signal receiving range, the maximum transmission rate and the signal-to-noise ratio. Therefore, high delay resolution, wide delay variation range and wide operating bandwidth are key to improving the transmission quality of wireless communication systems.

At present, delay line circuits are generally implemented in the form of optical devices, Micro-Electro-Mechanical systems (MEMS), electronic devices, and the like. When an optical device or an MEMS is adopted, the technology is complex, the realization cost is high, and the large-scale integration application is not easy. Compared with the two modes, the delay line circuit is realized by using a semiconductor integrated circuit method, has the advantages of small volume, low cost, easiness in monolithic integration and the like, and is widely concerned in the field of wireless communication. However, under the condition of adopting active device integration, the circuit performance is often influenced by external environment changes, the anti-interference capability is poor, and the delay deviation is large. To solve this problem, the delay is usually calibrated by using a feedback loop, but this adds extra power consumption. Meanwhile, the active devices tend to bring higher impedance and cause lower poles, thereby limiting the effective bandwidth of circuit operation. Meanwhile, the delay time of an active circuit is generally inversely proportional to the working bandwidth of the circuit, and in order to realize a large delay time range, the pole of the circuit is small, so that the bandwidth is limited. The bandwidth of the active delay line circuit is small, the delay time is long, so that the delay resolution is reduced, and the amount and the angle of processed information are limited. In summary, how to improve the delay resolution, the delay operation bandwidth, the stability of the circuit performance, and reduce the power consumption of the circuit is a technical problem to be solved urgently at present.

Disclosure of Invention

The purpose of the invention is as follows: based on the defects, the invention provides a broadband adjustable real-time delay line circuit, which can realize continuous adjustment of delay and a large delay range, and has the advantages of strong anti-jamming capability, low power consumption and easy realization.

The technical scheme is as follows: the broadband adjustable real-time delay line circuit comprises a plurality of cascaded coarse delay structures, each coarse delay structure comprises a pair of passive delay units and an active path amplifier, the active path amplifier is bridged between output ends of the pair of passive delay units, the active path amplifiers of the coarse delay structures always keep one active path amplifier working under the control of a switch, and other active path amplifiers do not work. The passive delay unit is composed of an inductor and a capacitor. The active path amplifier comprises a first amplifying tube M1, a second transistor M2 and a third transistor M3, wherein the drain of the first amplifying tube M1 is connected with the source of the third transistor M3, the source of the first amplifying tube M1 is connected with the drain of the second transistor M2, the source of the second transistor M2 is grounded, the gate of the first amplifying tube M1 serves as the input end of the active path amplifier, and the drain of the third transistor M3 serves as the output end of the active path amplifier. The coarse control voltage is applied to the grid electrode of the third transistor M3, and the high potential and the low potential of the coarse control voltage are used for controlling the on or off of the active path amplifier to realize coarse delay adjustment; the fine control voltage is applied to the gate of the second transistor M2, and the fine delay adjustment is achieved by adjusting the magnitude of the fine control voltage to change the delay time of the active path amplifier.

Has the advantages that: the invention adopts the passive inductance and capacitance as the time delay unit, and the time delay is roughly adjusted by selecting the switch control signal path. The delay fine adjustment is carried out on the bias current of the active path amplifier in combination, so that the relative delay of the delay line can be continuously changed, the combination of coarse adjustment and fine adjustment is realized, the delay resolution is improved, and the delay change range is enlarged. The broadband adjustable real-time delay line circuit provided by the invention has the advantages of broadband, continuous delay adjustment, good delay stability, large delay range, lower power consumption, low noise and easiness in implementation.

Drawings

FIG. 1 is an overall schematic diagram of the wideband adjustable real-time delay line circuit of the present invention;

FIG. 2 is a schematic diagram of an LC delay unit according to the present invention;

fig. 3 is a schematic diagram of the structure of the active path amplifier circuit of the present invention.

Detailed Description

The technical scheme of the invention is further explained by combining the attached drawings.

As shown in fig. 1, the broadband adjustable real-time delay line circuit of the present invention is mainly composed of cascaded N-stage coarse delay structures, each coarse delay structure includes a pair of passive delay units and an active path amplifier, the active path amplifier is bridged between the two passive delay units, and the specific structure is as follows: the input end Si and the output end So of the active path amplifier are respectively connected with the output end Do of a passive delay unit to form a primary coarse delay structure; the input end of the next-stage coarse delay structure is connected with the input end Si of the last-stage active path amplifier, and the output end of the next-stage coarse delay structure is connected with the output end So of the last-stage active path amplifier. And setting the delay time of each passive delay unit as T and the delay time of the path selection amplifier as Ta, wherein the delay time of each stage of coarse delay structure is 2T + Ta. In each state, the path amplifier of one stage of the coarse delay structure works through the control switch, other path amplifiers do not work, and signals are transmitted from the conducted path. When the first-stage coarse delay structure works, other coarse delay structures do not work, a signal passes through a first-stage path amplifier S1, and the delay time of the delay line circuit is 2T + Ta; when the second-stage path selection amplifier is switched on, other coarse delay structures are switched off, and the delay time of the delay line circuit is 4T + Ta, so that the relative delay difference of two adjacent stages of coarse delay structures is 2T, and the relative delay of the delay line circuit formed by the N stages of coarse delay structures can change from 0 to 2(N-1) T by the time of step 2T.

As shown in FIG. 2, the passive delay unit of the invention is composed of a pair of passive L type inductance and capacitance, from the process point of view, the passive device is composed of metal and insulating medium, the value of the passive device is determined by physical dimension, the change of electron hole mobility can not affect the size of the inductance and capacitance, therefore, the change of process, power supply and temperature has little effect on the inductance and capacitance, thus having little effect on the delay time of the circuit, high stability, high bandwidth and low noise due to larger size and low impedance, and the device can work without power supply, low power consumption

Meanwhile, the selection of the inductance capacitance value needs to consider impedance matching according to a formula

The characteristic impedance should be matched to 50 ohms. In order to maintain impedance consistency, the impedances of the input end, the output end, the interstage node and the load end of the delay line in the delay line circuit need to be matched to 50 ohms, and the signals are guaranteed to have flat group delay, low return loss and good integrity.

As shown in fig. 3, the active path amplifier circuit of the present invention is a single-ended input single-ended output structure, and is formed by connecting a first amplifying transistor M1, a voltage-controlled second transistor M2, and a switch-controlled third transistor M3 in series. The circuit can be used as a switch circuit to select a signal transmission path on one hand, and can adjust the delay time of the circuit by finely adjusting the control voltage on the other hand. Specifically, the drain of the first amplifying transistor M1 is connected to the source of the third transistor M3, the source of M1 is connected to the drain of M2, and serves as an adjustable bias current source, the source of M2 is grounded, the gate of M1 is the input terminal Si of the active path amplifier, and the drain of M3 is the output terminal So of the active path amplifier. The coarse control voltage Vc is applied to the grid of M3, when Vc is connected with high potential, the path switch is conducted, and the signal passes through the path amplifier; on the contrary, when Vc is connected with a low potential, the path switch is disconnected, and the signal does not pass through the path amplifier, so that the purpose of selecting a signal transmission path can be realized, and the delay coarse adjustment is carried out. The fine adjustment control voltage Vctrl is applied to the grid of M2, the bias current of the circuit is controlled, the delay time of the active path amplifier is continuously changed from Ta to Tb by adjusting Vctrl, the change range of the delay time is Tb-Ta, and in order to ensure the continuity of the delay change, the change range needs to be more than 2T.

By finely adjusting the delay time of the path amplifier, the coarse delay resolution of the delay line circuit can be compensated, fine delay adjustment is realized, and the delay time of the real-time delay line circuit is continuously changed from 0 to 2(N-1) T.

Claims

1. A broadband adjustable real-time delay line circuit is characterized by comprising a plurality of cascaded coarse delay structures, each coarse delay structure comprises a pair of passive delay units and an active path amplifier, the active path amplifier is connected between output ends of the pair of passive delay units in a bridging mode, the active path amplifiers of the coarse delay structures always keep one of the active path amplifiers in operation under the control of a switch, the other active path amplifiers do not work, the active path amplifiers comprise a first amplifying transistor (M1), a second transistor (M2) and a third transistor (M3), wherein the drain electrode of the first amplifying transistor (M1) is connected with the source electrode of the third transistor (M3), the source electrode of the first amplifying transistor (M1) is connected with the drain electrode of the second transistor (M2), the source electrode of the second transistor (M2) is grounded, and the grid electrode of the first amplifying transistor (M1) is used as the input end of the active path amplifier, the drain electrode of the third transistor (M3) is used as the output end of the active path amplifier; the grid electrode of the third transistor (M3) is connected with a coarse control voltage, and the path switch of the active path amplifier is controlled to be turned on or turned off by changing the potential of the coarse control voltage; the gate of the second transistor (M2) is connected with a fine adjustment control voltage, and the delay time of the active path amplifier is changed by changing the size of the fine adjustment control voltage.

2. The wideband adjustable real-time delay line circuit of claim 1, wherein the passive delay elements are comprised of inductors and capacitors.