CN107394006B - A kind of N-type double-side cell preparation method - Google Patents
A kind of N-type double-side cell preparation method Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 116
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 116
- 239000010703 silicon Substances 0.000 claims abstract description 116
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910004304 SiNy Inorganic materials 0.000 claims abstract description 32
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 26
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 26
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 26
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 26
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 26
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 26
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052796 boron Inorganic materials 0.000 claims abstract description 23
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 11
- 239000011574 phosphorus Substances 0.000 claims abstract description 11
- 238000001020 plasma etching Methods 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims abstract description 11
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052593 corundum Inorganic materials 0.000 claims abstract description 10
- 229910001845 yogo sapphire Inorganic materials 0.000 claims abstract description 10
- 239000011521 glass Substances 0.000 claims abstract description 9
- 238000010079 rubber tapping Methods 0.000 claims abstract description 8
- 238000007650 screen-printing Methods 0.000 claims abstract description 8
- 230000006735 deficit Effects 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 7
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 claims abstract 2
- 239000005297 pyrex Substances 0.000 claims abstract 2
- 238000002310 reflectometry Methods 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 150000001875 compounds Chemical class 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 235000008216 herbs Nutrition 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- 210000002268 wool Anatomy 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005713 exacerbation Effects 0.000 description 1
- 230000001795 light effect Effects 0.000 description 1
- 208000020442 loss of weight Diseases 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0684—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells double emitter cells, e.g. bifacial solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The present invention provides a kind of N-type double-side cell preparation methods, comprising: two-sided reactive ion etching is carried out to the N-type silicon chip by damage processing, to prepare nanometer suede on surface；After passing through SiOx-SiNy mask process to the back side of N-type silicon chip, boron diffusion is carried out to front；Then after HF solution removes back side SiOx-SiNy mask layer, then to positive SiOx-SiNy exposure mask；SiO is overleaf carried out later2Layer growth；With SiO2Layer is used as mask layer, carries out an aperture processing under main grid to form N++ window, handles removal aperture residual impairment through weak lye；Single side phosphorus diffusion is carried out at the back side of N-type silicon chip, forms N++ layers in tapping, other regions form N+ layers；HF processing is carried out after carrying out edge isolation to N-type silicon chip, removes positive SiOx-SiNy exposure mask, Pyrex and the phosphorosilicate glass at the back side, then clean through RCA；By the front and back of N-type silicon chip respectively through Al2O3/ SiNx and overlayer passivation, are sintered after silk-screen printing.The present invention can be improved Uoc, Isc, FF, and then improve the incident photon-to-electron conversion efficiency of battery front side.
Description
Technical field
The present invention relates to technical field of solar batteries, more particularly to a kind of N-type double-side cell preparation method.
Background technique
Further obvious with greenhouse effects, ecological environment is more and more valued by people.Solar energy industry is as clear
One of festival energy industry, development at full speed at this stage, wherein being most widely used with silicon based cells, thus its efficiency
Promote the concern for being also constantly subjected to people.P-type crystal silicon battery has many advantages, such as low in cost, technical maturity at present, has occupied
Market dominant contribution, but since p-type cell piece has the characteristics that photo attenuation, matrix service life be not high, in efficient aspect still bottle
Neck is larger.
Compared to P-type wafer, N-type silicon chip relatively has minority carrier life time height, high, the higher minority diffusion length to metal tolerance
The advantages that, excellent substrate performance has been to be concerned by more and more people, so that the application of N-type double-side cell is also increasingly wider
It is general.N-type cell has the characteristics that generating electricity on two sides, dim light respond, minority carrier life time is high, temperature coefficient is low and without photo attenuation, this
It is that p-type crystal silicon battery cannot compare a bit.
But in existing N-type double-sided solar battery preparation process, since the back side etches removal BSG (borosilicate glass through HF/HNO3
Glass), cause back side suede structure imperfect, cause sunken light effect poor, and after grid line printing, since passivation layer is by broken
Bad, passivation quality reduces, and the compound exacerbation in the back side influences Uoc (open-circuit voltage), Isc (short circuit current) and FF (fill factor), most
The positive incident photon-to-electron conversion efficiency of double-side cell is influenced eventually, using the front lighting of the N-type double-sided solar battery of prior art preparation
Electrotransformation efficiency is 20.3%.
Summary of the invention
In view of the above situation, it is necessary to a kind of N-type double-side cell preparation method be provided, Uoc, Isc, FF are improved, to improve
Battery front side incident photon-to-electron conversion efficiency.
A kind of N-type double-side cell preparation method, comprising:
Damage processing is carried out to the surface of N-type silicon chip；
Two-sided reactive ion etching is carried out to the N-type silicon chip, to prepare nanometer suede on the surface of the N-type silicon chip；
After passing through SiOx-SiNy mask process to the back side of the N-type silicon chip, boron is carried out to the front of the N-type silicon chip
Diffusion；
To the N-type silicon chip after HF solution removes back side SiOx-SiNy mask layer, front is carried out to the N-type silicon chip
SiOx-SiNy exposure mask；
SiO is carried out at the back side of the N-type silicon chip2Layer growth；
With the SiO2Layer is used as mask layer, and an aperture processing is carried out under main grid to form N++ window, at weak lye
Reason removal aperture residual impairment；
Single side phosphorus diffusion is carried out at the back side of the N-type silicon chip, forms N++ layers in the tapping, other regions form N
+ layer；
HF processing is carried out after carrying out edge isolation to the N-type silicon chip, removes positive SiOx-SiNy exposure mask, borosilicate glass
Glass and the phosphorosilicate glass at the back side, then cleaned through RCA, remove residual impurity；
By the front and back of the N-type silicon chip respectively through Al2O3/ SiNx and overlayer passivation, are burnt after silk-screen printing
Knot.
The N-type double-side cell preparation method provided according to the present invention uses reactive ion making herbs into wool (RIE) to N-type silicon chip, tool
There are uniform positive back side nanometer suede structure and excellent sunken optical property, increases transmission range of the light in silicon wafer, it is defeated to improve Isc
Out, the back side uses SiO2Exposure mask and the slot treatment under main grid form SE (selective emitter) structure, i.e., after phosphorus diffusion
Slot area forms N++ layers, other regions form N+ layers, on the one hand can reduce the contact resistance of electrode and silicon substrate, improves
FF, on the other hand reducing main grid, nearby few son is compound, to increase Uoc, improves passivation quality, finally can be improved battery front side
Incident photon-to-electron conversion efficiency.
In addition, above-mentioned N-type double-side cell preparation method according to the present invention, can also have following additional technology special
Sign:
Further, described that two-sided reactive ion etching is carried out to the N-type silicon chip, on the surface of the N-type silicon chip
In the step of preparing nanometer suede, the reflectivity of the N-type silicon chip is controlled in 3%-6%.
Further, after the back side to the N-type silicon chip passes through SiOx-SiNy mask process, to the N-type silicon chip
Front carry out boron diffusion the step of in, boron diffusion temperature be 900-990 DEG C, sheet resistance control in 80~100 Ω/Squar..
Further, the back side in the N-type silicon chip carries out SiO2In the step of layer growth, the SiO2The thickness of layer
Degree control is in 5-15nm.
Further, the back side in the N-type silicon chip carries out single side phosphorus diffusion, forms N++ layers in the tapping,
In the step of other regions form N+ layers, the N+ layers of sheet resistance is 80-110 Ω/Squar., and the N++ layers of sheet resistance is 40-70
Ω/Squar.。
Further, the front and back by the N-type silicon chip is respectively through Al2O3/ SiNx and overlayer passivation, organizine
In the step of being sintered after wire mark brush, front surface A l2O3With a thickness of 3-20nm, positive SiNx with a thickness of 70-100nm, reflection
Rate is 2-5%, back side SiO2The laminated thickness of/SiNx is 75-90nm, reflectivity 2-5%.
Further, described that two-sided reactive ion etching is carried out to the N-type silicon chip, on the surface of the N-type silicon chip
In the step of preparing nanometer suede, the reflectivity for controlling the N-type silicon chip is 5%.
Further, after the back side to the N-type silicon chip passes through SiOx-SiNy mask process, to the N-type silicon chip
Front carry out boron diffusion the step of in, boron diffusion temperature be 950 DEG C, sheet resistance control in 85~95 Ω/Squar..
Further, the back side in the N-type silicon chip carries out SiO2In the step of layer growth, the SiO is controlled2Layer
With a thickness of 10nm.
Further, the front and back by the N-type silicon chip is respectively through Al2O3/ SiNx and overlayer passivation, organizine
In the step of being sintered after wire mark brush, front surface A l2O3With a thickness of 10nm, positive SiNx with a thickness of 85nm, reflectivity is
3%, back side SiO2The laminated thickness of/SiNx is 80nm, reflectivity 4%.
Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the N-type double-side cell of embodiment of the present invention preparation.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing
Give several embodiments of the invention.But the invention can be realized in many different forms, however it is not limited to this paper institute
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the listed item of pass.
Embodiments of the present invention provide a kind of N-type double-side cell preparation method, comprising:
S11 carries out damage processing to the surface of N-type silicon chip；
Wherein, damage processing method can use conventional means, such as N-type silicon chip is handled through KOH solution, control silicon wafer
Loss of weight is 0.6-0.7g.
S12 carries out two-sided reactive ion etching to the N-type silicon chip, to prepare nanometer suede on the surface of the N-type silicon chip
Face；
S13, to the back side of the N-type silicon chip by after SiOx-SiNy mask process, to the front of the N-type silicon chip into
The diffusion of row boron；
S14 carries out the N-type silicon chip to the N-type silicon chip after HF solution removes back side SiOx-SiNy mask layer
Positive SiOx-SiNy exposure mask；
S15 carries out SiO at the back side of the N-type silicon chip2Layer growth；
S16, with the SiO2Layer is used as mask layer, and an aperture processing is carried out under main grid to form N++ window, through weak base
Liquid processing removal aperture residual impairment；
S17, carries out single side phosphorus diffusion at the back side of the N-type silicon chip, forms N++ layers in the tapping, other regions
Form N+ layers, wherein specific structure please refers to Fig. 1；
S18 carries out HF processing after carrying out edge isolation to the N-type silicon chip, removes positive SiOx-SiNy exposure mask, boron
Silica glass and the phosphorosilicate glass at the back side, then cleaned through RCA, remove residual impurity；
S19, by the front and back of the N-type silicon chip respectively through Al2O3/ SiNx and overlayer passivation, it is laggard through silk-screen printing
Row sintering.
In embodiment of the present invention, in step S12, the reflectivity of the N-type silicon chip is controlled in 3%-6%.
In step S13, boron diffusion temperature is 900-990 DEG C, and sheet resistance is controlled in 80~100 Ω/Squar..
In step S15, the SiO2The thickness control of layer is in 5-15nm.
In step S17, the N+ layers of sheet resistance be 80-110 Ω/Squar., the N++ layer sheet resistance for 40-70 Ω/
Squar.。
In step S19, front surface A l2O3With a thickness of 3-20nm, positive SiNx with a thickness of 70-100nm, reflectivity 2-
5%, back side SiO2The laminated thickness of/SiNx is 75-90nm, reflectivity 2-5%.
Finally according to the structure of the N-type double-side cell of above embodiment preparation as shown in Figure 1, providing according to the present invention
N-type double-side cell preparation method uses reactive ion making herbs into wool (RIE) to N-type silicon chip, has uniform positive back side nanometer suede knot
Structure and excellent sunken optical property increase transmission range of the light in silicon wafer, improve Isc output, and the back side uses SiO2Exposure mask and
Slot treatment under main grid forms SE (selective emitter) structure after phosphorus diffusion, i.e. slot area forms N++ layers, other
Region forms N+ layers, on the one hand can reduce the contact resistance of electrode and silicon substrate, improves FF, on the other hand reduces near main grid
Few son is compound, to increase Uoc, improves passivation quality, finally can be improved the incident photon-to-electron conversion efficiency of battery front side.
Divide multiple embodiments that the embodiment of the present invention is further detailed below.The embodiment of the present invention be not limited to
Under specific embodiment.Within the scope of the unchanged main rights, implementation can appropriate be changed.
Embodiment one
A kind of N-type double-side cell preparation method, comprising:
S21 carries out damage processing to the surface of N-type silicon chip；
S22 carries out two-sided reactive ion etching to the N-type silicon chip, to prepare nanometer suede on the surface of the N-type silicon chip
Face, wherein control the reflectivity of the N-type silicon chip 5%；
S23, to the back side of the N-type silicon chip by after SiOx-SiNy mask process, to the front of the N-type silicon chip into
Row boron diffusion, wherein boron diffusion temperature is 950 DEG C, and sheet resistance is controlled in 85~95 Ω/Squar.；
S24 carries out the N-type silicon chip to the N-type silicon chip after HF solution removes back side SiOx-SiNy mask layer
Positive SiOx-SiNy exposure mask；
S25 carries out SiO at the back side of the N-type silicon chip2Layer growth, wherein the SiO2The thickness control of layer is in 10nm；
S26, with the SiO2Layer is used as mask layer, and an aperture processing is carried out under main grid to form N++ window, through weak base
Liquid processing removal aperture residual impairment；
S27, carries out single side phosphorus diffusion at the back side of the N-type silicon chip, forms N++ layers in the tapping, other regions
Form N+ layers, wherein the N+ layers of sheet resistance is 95 Ω/Squar., and the N++ layers of sheet resistance is 55 Ω/Squar.；
S28 carries out HF processing after carrying out edge isolation to the N-type silicon chip, removes positive SiOx-SiNy exposure mask, boron
Silica glass and the phosphorosilicate glass at the back side, then cleaned through RCA, remove residual impurity；
S29, by the front and back of the N-type silicon chip respectively through Al2O3/ SiNx and overlayer passivation, it is laggard through silk-screen printing
Row sintering, wherein front surface A l2O3With a thickness of 10nm, positive SiNx with a thickness of 85nm, reflectivity 3%, back side SiO2/
The laminated thickness of SiNx is 80nm, reflectivity 4%.
The front optoelectronic transformation efficiency for the N-type double-side cell that the present embodiment is prepared is 20.52.
Embodiment two
A kind of N-type double-side cell preparation method, comprising:
S31 carries out damage processing to the surface of N-type silicon chip；
S32 carries out two-sided reactive ion etching to the N-type silicon chip, to prepare nanometer suede on the surface of the N-type silicon chip
Face, wherein control the reflectivity of the N-type silicon chip 3%；
S33, to the back side of the N-type silicon chip by after SiOx-SiNy mask process, to the front of the N-type silicon chip into
Row boron diffusion, wherein boron diffusion temperature is 900 DEG C, and sheet resistance is controlled in 80 Ω/Squar.；
S34 carries out the N-type silicon chip to the N-type silicon chip after HF solution removes back side SiOx-SiNy mask layer
Positive SiOx-SiNy exposure mask；
S35 carries out SiO at the back side of the N-type silicon chip2Layer growth, wherein the SiO2The thickness control of layer is in 5nm；
S36, with the SiO2Layer is used as mask layer, and an aperture processing is carried out under main grid to form N++ window, through weak base
Liquid processing removal aperture residual impairment；
S37, carries out single side phosphorus diffusion at the back side of the N-type silicon chip, forms N++ layers in the tapping, other regions
Form N+ layers, wherein the N+ layers of sheet resistance is 80 Ω/Squar., and the N++ layers of sheet resistance is 40 Ω/Squar.；
S38 carries out HF processing after carrying out edge isolation to the N-type silicon chip, removes positive SiOx-SiNy exposure mask, boron
Silica glass and the phosphorosilicate glass at the back side, then cleaned through RCA, remove residual impurity；
S39, by the front and back of the N-type silicon chip respectively through Al2O3/ SiNx and overlayer passivation, it is laggard through silk-screen printing
Row sintering, wherein front surface A l2O3With a thickness of 3nm, positive SiNx with a thickness of 70nm, reflectivity 2%, back side SiO2/
The laminated thickness of SiNx is 75nm, reflectivity 2%.
The front optoelectronic transformation efficiency for the N-type double-side cell that the present embodiment is prepared is 20.51.
Embodiment three
A kind of N-type double-side cell preparation method, comprising:
S41 carries out damage processing to the surface of N-type silicon chip；
S42 carries out two-sided reactive ion etching to the N-type silicon chip, to prepare nanometer suede on the surface of the N-type silicon chip
Face, wherein control the reflectivity of the N-type silicon chip 6%；
S43, to the back side of the N-type silicon chip by after SiOx-SiNy mask process, to the front of the N-type silicon chip into
Row boron diffusion, wherein boron diffusion temperature is 990 DEG C, and sheet resistance is controlled in 100 Ω/Squar.；
S44 carries out the N-type silicon chip to the N-type silicon chip after HF solution removes back side SiOx-SiNy mask layer
Positive SiOx-SiNy exposure mask；
S45 carries out SiO at the back side of the N-type silicon chip2Layer growth, wherein the SiO2The thickness control of layer is in 15nm；
S46, with the SiO2Layer is used as mask layer, and an aperture processing is carried out under main grid to form N++ window, through weak base
Liquid processing removal aperture residual impairment；
S47, carries out single side phosphorus diffusion at the back side of the N-type silicon chip, forms N++ layers in the tapping, other regions
Form N+ layers, wherein the N+ layers of sheet resistance is 110 Ω/Squar., and the N++ layers of sheet resistance is 70 Ω/Squar.；
S48 carries out HF processing after carrying out edge isolation to the N-type silicon chip, removes positive SiOx-SiNy exposure mask, boron
Silica glass and the phosphorosilicate glass at the back side, then cleaned through RCA, remove residual impurity；
S49, by the front and back of the N-type silicon chip respectively through Al2O3/ SiNx and overlayer passivation, it is laggard through silk-screen printing
Row sintering, wherein front surface A l2O3With a thickness of 20nm, positive SiNx with a thickness of 100nm, reflectivity 5%, back side SiO2/
The laminated thickness of SiNx is 90nm, reflectivity 5%.
The front optoelectronic transformation efficiency for the N-type double-side cell that the present embodiment is prepared is 20.52.
Table 1
Table 1 compared the front photoelectric conversion for the battery prepared using the method for above three embodiments and the prior art
Rate, it is apparent that the front lighting of the N-type double-side cell finally prepared using the method for three embodiments of the invention from table
Compared with the prior art electrotransformation rate improves 0.2% or more, obvious for double-sided solar battery performance boost, this is because this
Invention is mentioned to N-type silicon chip using reactive ion making herbs into wool, can increase transmission range of the light in silicon wafer, improves Isc output, the back side
Using SiO2Exposure mask and the slot treatment under main grid form SE structure after phosphorus diffusion, on the one hand can reduce electrode and silicon
The contact resistance of matrix, improves FF, and on the other hand reducing main grid, nearby few son is compound, to increase Uoc, improves passivation quality,
Finally improve the positive incident photon-to-electron conversion efficiency of battery.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (6)
1. a kind of N-type double-side cell preparation method characterized by comprising
Damage processing is carried out to the surface of N-type silicon chip；
Two-sided reactive ion etching is carried out to the N-type silicon chip, to prepare nanometer suede on the surface of the N-type silicon chip；
Front progress boron diffusion after SiOx-SiNy mask process, to the N-type silicon chip is passed through to the back side of the N-type silicon chip；
To the N-type silicon chip after HF solution removes back side SiOx-SiNy mask layer, front SiOx- is carried out to the N-type silicon chip
SiNy exposure mask；
SiO is carried out at the back side of the N-type silicon chip2Layer growth, the SiO2The thickness control of layer is in 5-15nm；
With the SiO2Layer is used as mask layer, carries out an aperture processing under main grid to form N++ window, handles and go through weak lye
Except aperture residual impairment；
Single side phosphorus diffusion is carried out at the back side of the N-type silicon chip, forms N++ layers in the tapping, other regions form N+ layers,
Wherein, the N+ layers of sheet resistance is 80-110 Ω/Squar., and the N++ layers of sheet resistance is 40-70 Ω/Squar.；
To the N-type silicon chip carry out edge isolation after carry out HF processing, remove positive SiOx-SiNy exposure mask, Pyrex and
The phosphorosilicate glass at the back side, then cleaned through RCA, remove residual impurity；
By the front and back of the N-type silicon chip respectively through Al2O3/ SiNx and overlayer passivation, are sintered after silk-screen printing,
Front surface A l2O3With a thickness of 3-20nm, positive SiNx with a thickness of 70-100nm, reflectivity 2-5%, back side SiO2/ SiNx's
Laminated thickness is 75-90nm, reflectivity 2-5%.
2. N-type double-side cell preparation method according to claim 1, which is characterized in that described to be carried out to the N-type silicon chip
Two-sided reactive ion etching, to control the N-type silicon chip in the step of surface of the N-type silicon chip prepares nanometer suede
Reflectivity is in 3%-6%.
3. N-type double-side cell preparation method according to claim 1, which is characterized in that the back to the N-type silicon chip
After face passes through SiOx-SiNy mask process, in positive the step of carrying out boron diffusion of the N-type silicon chip, boron diffusion temperature is
900-990 DEG C, sheet resistance is controlled in 80~100 Ω/Squar..
4. N-type double-side cell preparation method according to claim 2, which is characterized in that described to be carried out to the N-type silicon chip
Two-sided reactive ion etching, to control the N-type silicon chip in the step of surface of the N-type silicon chip prepares nanometer suede
Reflectivity is 5%.
5. N-type double-side cell preparation method according to claim 3, which is characterized in that the back to the N-type silicon chip
After face passes through SiOx-SiNy mask process, in positive the step of carrying out boron diffusion of the N-type silicon chip, boron diffusion temperature is
950 DEG C, sheet resistance is controlled in 85~95 Ω/Squar..
6. N-type double-side cell preparation method according to claim 5, which is characterized in that it is described by the N-type silicon chip just
Face and the back side are respectively through Al2O3/ SiNx and overlayer passivation, in the step of being sintered after silk-screen printing, front surface A l2O3Thickness
Degree be 10nm, positive SiNx with a thickness of 85nm, reflectivity 3%, back side SiO2The laminated thickness of/SiNx is 80nm, reflection
Rate is 4%.
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| CN109671806A (en) * | 2018-12-26 | 2019-04-23 | 浙江晶科能源有限公司 | A kind of preparation method of N-type double-side cell |
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