CN107393824A - A kind of semiconductor field effect transistor and preparation method thereof - Google Patents
A kind of semiconductor field effect transistor and preparation method thereof Download PDFInfo
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- CN107393824A CN107393824A CN201610322620.6A CN201610322620A CN107393824A CN 107393824 A CN107393824 A CN 107393824A CN 201610322620 A CN201610322620 A CN 201610322620A CN 107393824 A CN107393824 A CN 107393824A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 111
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 101
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 90
- 229920005591 polysilicon Polymers 0.000 claims abstract description 90
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 63
- 239000010703 silicon Substances 0.000 claims abstract description 63
- 230000005669 field effect Effects 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000000407 epitaxy Methods 0.000 claims description 27
- 239000003989 dielectric material Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000002829 reductive effect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000005611 electricity Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention provides a kind of semiconductor field effect transistor and preparation method thereof, the preparation method of the semiconductor field effect transistor, including：The first silicon oxide layer is formed in the groove of silicon chip；The first polysilicon layer is covered on first silicon oxide layer, and first polysilicon layer fills up the groove；First silicon oxide layer and first polysilicon layer are performed etching, retain the first silicon oxide layer and the first polysilicon layer of predetermined depth；The second silicon oxide layer is formed in the outer surface of groove and groove；The second polysilicon layer is filled in the groove of second silicon oxide layer parcel；Filled media and metal on silicon chip, form semiconductor field effect transistor.The semiconductor field effect transistor made through the above way, the switching loss of semiconductor field effect transistor is reduced, improves operating efficiency.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical field, more particularly to a kind of semiconductor field is brilliant
Body pipe and preparation method thereof.
Background technology
Drain-source the two poles of the earth of vertical DMOS field-effect transistor (VDMOS) exist respectively
The both sides of device, electric current is vertically circulated in device inside, add current density, improve rated current,
The conducting resistance of unit area is also smaller, is a kind of very extensive power device of purposes.VDMOS's is most heavy
The performance parameter wanted is exactly working loss, and working loss can be divided into conduction loss, and cut-off loss and switch damage
Consume three parts.Wherein conduction loss is determined by conducting resistance, and cut-off loss is by reverse leakage electrode current size shadow
Ring, switching loss refers to the loss that parasitic capacitance discharge and recharge is brought during devices switch.In order to meet power
Device adapts to the requirement of frequency applications, reduces the switching loss of power device, improves the operating efficiency tool of device
There is important meaning.
The switching loss size of power device is determined that parasitic capacitance can be divided into grid source electricity by parasitic capacitance size
Hold, gate leakage capacitance and source drain capacitance three parts.Wherein, gate leakage capacitance influences maximum on the switching loss of device,
Gate leakage capacitance can be divided into oxidation layer capacitance and depletion-layer capacitance two parts, and oxidation layer capacitance is by gate oxide thickness shadow
Ring, depletion-layer capacitance is had a great influence by technique and device architecture.Conventional VDMOS device architecture such as Fig. 1
It is shown.
In Fig. 1, the upper strata of silicon substrate 1 covering N-type epitaxy layer 2, covered with p-type in N-type epitaxy layer 2
Region 3, groove is etched with p type island region domain 3, the bottom surface of groove is located at N-type epitaxy layer 2 and p type island region domain 3
The bottom of contact, one layer of silica 4 is provided with the inwall of groove, polysilicon 5, groove are filled with groove
Top is covered with dielectric material 6, and dielectric material 6 and the top of p type island region domain 3 are covered with metal material 7.It is such a
The VDMOS of structure can form larger gate leakage capacitance in N-type epitaxy layer 2, and then cause VDMOS
Switching loss it is larger.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of semiconductor field effect transistor and preparation method thereof,
To solve the switching loss of existing VDMOS device, the problem of operating efficiency is not high.
In order to solve the above-mentioned technical problem, the embodiment of the present invention provides a kind of system of semiconductor field effect transistor
Make method, including：
The first silicon oxide layer is formed in the groove of silicon chip；
Cover the first polysilicon layer on first silicon oxide layer, and first polysilicon layer fill up it is described
Groove；
First silicon oxide layer and first polysilicon layer are performed etching, retain the first of predetermined depth
Silicon oxide layer and the first polysilicon layer；
The second silicon oxide layer is formed in the outer surface of groove and groove；
The second polysilicon layer is filled in the groove of second silicon oxide layer parcel；
Filled media and metal on silicon chip, form semiconductor field effect transistor.
Further, the thickness of first silicon oxide layer is 0.1 micron to 1 micron.
Further, described the step of forming the first silicon oxide layer in the groove of silicon chip, is specially：
Using photoresist as mask, performed etching on silicon chip, form groove, the bottom position of the groove
In the N-type epitaxy layer of the silicon chip；
Thermal oxide is carried out, the first silicon oxide layer is generated in the side wall of the groove and bottom.
Further, the lithographic method performed etching on silicon chip includes：Dry etching and/or wet etching.
Further, first silicon oxide layer is covered in the outer surface of the groove.
Further, it is described that first silicon oxide layer and first polysilicon layer are performed etching, retain
The step of first silicon oxide layer of predetermined depth and the first polysilicon layer is specially：
The first silicon oxide layer in the groove in the p-type epitaxial layer of silicon chip and the are removed using dry etching
One polysilicon layer, retain the first silicon oxide layer and the first polysilicon layer in the groove being located in N-type epitaxy layer.
Further, the thickness of second silicon oxide layer is 0.01 micron to 0.1 micron.
Further, it is described to be specially the step of the outer surface of groove and groove forms the second silicon oxide layer：
Formed in the trench cover first silicon oxide layer and the first polysilicon layer the second silicon oxide layer,
And it is also formed with the second silicon oxide layer in the side wall of the groove and outer surface.
Further, the step that the second polysilicon layer is filled in the groove of second silicon oxide layer parcel
It is rapid to be specially：
The second polysilicon layer, and institute are covered on the second silicon oxide layer of the outer surface of the groove and side wall
State the second polysilicon layer and fill up whole groove；
Etching removes the second polysilicon layer positioned at the outer surface of groove.
Further, the filled media on silicon chip and metal, the step of semiconductor field effect transistor is formed
It is rapid to be specially：
The filling of Filled Dielectrics and etching and metal is carried out on silicon chip, obtains semiconductor field effect transistor.
The embodiment of the present invention provides a kind of semiconductor field effect transistor, including：
Silicon chip, the silicon chip include：Silicon substrate, the N-type epitaxy layer being covered in above silicon substrate and covering
P-type epitaxial layer above N-type epitaxy layer；
At least one groove is provided with the silicon chip, and the openend of the groove is located at p-type epitaxial layer table
Face, the bottom of the groove are located in N-type epitaxy layer；
The first silicon oxide layer in the side wall and bottom of the groove being covered in the N-type epitaxy layer；
The first polysilicon layer being covered on first silicon oxide layer, and first polysilicon layer is by the N
Groove in type epitaxial layer fills up；
The second silicon oxide layer being covered on first silicon oxide layer and first polysilicon layer, and it is described
Second silicon oxide layer is covered in the side wall of the groove in the p-type epitaxial layer；
The second polysilicon layer being covered on second silicon oxide layer, and second polysilicon layer is by the P
Groove in type epitaxial layer fills up；
The dielectric material being covered on second polysilicon layer and second silicon oxide layer；And
The metal material being covered on the p-type epitaxial layer and the dielectric material.
Further, the thickness of first silicon oxide layer is 0.1 micron to 1 micron.
Further, the thickness of second silicon oxide layer is 0.01 micron to 0.1 micron.
The beneficial effects of the invention are as follows：
Such scheme, by forming orthogonal polysilicon layer respectively in the groove of silicon chip so that be located at
Polysilicon layer in the groove of different parts on silicon chip is mutually not attached to, and that makes in this way partly leads
Body field-effect transistor, when a certain partial polysilicon layer in groove is powered, the polysilicon at other positions
Electric capacity is not present on layer, reduces gate leakage capacitance so as to reduce, reduces semiconductor field effect transistor
Switching loss, improve operating efficiency.
Brief description of the drawings
Fig. 1 represents conventional VDMOS device architecture schematic diagram；
Fig. 2 represents the schematic flow sheet of the preparation method of the embodiment of the present invention；
Fig. 3 represents execution of step 11, the structural representation of the silicon chip of formation；
Fig. 4 represents execution of step 12, the structural representation of the silicon chip of formation；
Fig. 5 represents execution of step 20, the structural representation of the silicon chip of formation；
Fig. 6 represents execution of step 30, the structural representation of the silicon chip of formation；
Fig. 7 represents execution of step 40, the structural representation of the silicon chip of formation；
Fig. 8 represents execution of step 50, the structural representation of the silicon chip of formation；
Fig. 9 represents execution of step 60, the structural representation of the VDMOS device of formation.
Embodiment
It is below in conjunction with accompanying drawing and specifically real to make the object, technical solutions and advantages of the present invention clearer
Applying example, the present invention will be described in detail.
The problem of present invention is directed to the switching loss of existing VDMOS device, and operating efficiency is not high, there is provided
A kind of semiconductor field effect transistor and preparation method thereof.
As shown in Fig. 2 the preparation method of the semiconductor field effect transistor of the embodiment of the present invention, including：
Step 10, the first silicon oxide layer is formed in the groove of silicon chip；
Step 20, the first polysilicon layer, and first polysilicon layer are covered on first silicon oxide layer
Fill up the groove；
Step 30, first silicon oxide layer and first polysilicon layer are performed etching, retained default deep
The first silicon oxide layer and the first polysilicon layer of degree；
Step 40, the second silicon oxide layer is formed in the outer surface of groove and groove；
Step 50, the second polysilicon layer is filled in the groove of second silicon oxide layer parcel；
Step 60, filled media and metal on silicon chip, semiconductor field effect transistor is formed.
It should be noted that semiconductor field effect transistor described in the embodiment of the present invention generally refers to
VDMOS, polysilicon layer in the groove on silicon chip it can be seen from above-mentioned step 20 and step 50 by
Two parts form, i.e. the first polysilicon layer and the second polysilicon layer, and the first polysilicon layer and the second polysilicon
Layer is isolated by the second silicon oxide layer so that the current potential on the first polysilicon layer and the second polysilicon layer is mutual
Do not influence, when being powered to the second polysilicon layer, current potential will not be carried on the first polysilicon layer, so as to reduce
Gate leakage capacitance on the silicon chip near channel bottom, and then reduce VDMOS switching loss,
Improve operating efficiency.
Alternatively, as shown in Figure 3 and Figure 4, the step 10 specific implementation when, including：
Step 11, using photoresist as mask, performed etching on silicon chip, form groove 140, it is described
The bottom of groove 140 is located in the N-type epitaxy layer 120 of the silicon chip；
It should be noted that above-mentioned perform etching on silicon chip, used lithographic method includes：Dry method is carved
Erosion and/or wet etching；And the shape and size of the groove 140 can be set according to being actually needed
Put, be not specifically limited in the present invention.
After the completion of step 11, the concrete structure of silicon chip on silicon substrate 110 as shown in figure 3, wherein, cover
There is N-type epitaxy layer 120, the top of N-type epitaxy layer 120 is covered with p-type epitaxial layer 130, groove 140
Openend be located at the upper surface of p-type epitaxial layer 130, and the bottom of groove 140 is located at N-type epitaxy layer 120
In.It should be noted that being provided with multiple grooves 140 on the silicon chip, (show only in Fig. 3 can on silicon chip
2 grooves 140 seen).
Step 12, thermal oxide is carried out, the first silicon oxide layer is generated in the side wall of the groove 140 and bottom
150。
After the completion of step 12, the concrete structure of silicon chip is as shown in figure 4, it should be noted that first oxygen
SiClx layer 150 is not placed only in side wall and the bottom of groove 140, while is also covered in the groove 140
Outer surface (i.e. the upper surface of p-type epitaxial layer 130 is again covered with the first silicon oxide layer 150).Also need to
Bright, the thickness of first silicon oxide layer 150 in the embodiment of the present invention is 0.1 micron to 1 micron,
The thickness of silicon oxide layer in the existing VDMOS of thickness ratio of first silicon oxide layer 150 groove is big.
It is the filling and covering for carrying out the first polysilicon layer after the completion of the covering of the first silicon oxide layer 150,
Fig. 5 is fills and covered the structural representation of the silicon chip after the first polysilicon layer 160, as shown in Figure 5,
First polysilicon layer 160 fills up whole groove 140, meanwhile, the first oxygen positioned at the outer surface of groove 140
The first polysilicon layer 160 is again covered with SiClx layer 150.
, it is necessary to carry out the first silicon oxide layer 150 and the first polycrystalline after the first polysilicon layer 160 has been filled
The ground of silicon layer 160 removes, and further, the step 30 includes in specific implementation：
The first silicon oxide layer in the groove in the p-type epitaxial layer 130 of silicon chip is removed using dry etching
150 and first polysilicon layer 160, retain the first silicon oxide layer in the groove being located in N-type epitaxy layer 120
150 and first polysilicon layer 160.
After execution of step 30, the concrete structure of silicon chip is as shown in fig. 6, it will be appreciated from fig. 6 that be only located at
The first silicon oxide layer 150 and the first polysilicon layer 160 having are retained in groove 140 in N-type epitaxy layer 120,
Any material is not filled by the groove in p-type epitaxial layer 130.
Further, as shown in fig. 7, the step 40 is in specific implementation, including：
Formed in the groove 140 and cover the polysilicon layer 160 of the first silicon oxide layer 150 and first
Second silicon oxide layer 170 and it is also formed with the second silicon oxide layer in the side wall of the groove 140 and outer surface
170。
It should be noted that the thickness of second silicon oxide layer 170 is generally less than the first silicon oxide layer 150
Thickness, in actual applications, generally set second silicon oxide layer 170 thickness be 0.01 micron to 0.1
Micron.
It is the filling of the second polysilicon layer 180, such as Fig. 8 institutes after the second silicon oxide layer 170 has been covered
Show, the step 50 specific implementation when, including：
Step 51, is covered on the second silicon oxide layer 170 of the outer surface of the groove 140 and side wall
Two polysilicon layers 180, and second polysilicon layer 180 fills up whole groove；
Step 52, etching removes the second polysilicon layer 180 positioned at the outer surface of groove 140.
After the completion of step 52, the concrete structure of silicon chip is as shown in Figure 8.
It is the filling and encapsulation to silicon chip after using above-mentioned steps, groove 140 is filled up, to be formed
VDMOS, the specific implementation of the step 60 are：
The filling of Filled Dielectrics and etching and metal is carried out on silicon chip, obtains semiconductor field effect transistor.
It should be noted that the step 60 can use existing routine techniques to realize, in the present embodiment no longer
It is specifically described, after the completion of step 60, obtained VDMOS concrete structure is as shown in Figure 9.
It should be noted that above-mentioned preparation method, can increase high-temperature annealing step between arbitrary steps, this
High-temperature annealing step does not interfere with the performance of the device of making.
Further, as shown in figure 9, the embodiment of the present invention also provides a kind of semiconductor field effect transistor,
Including：
Silicon chip, the silicon chip include：Silicon substrate 110, the N-type epitaxy layer for being covered in the top of silicon substrate 110
120 and it is covered in the p-type epitaxial layer 130 of the top of N-type epitaxy layer 120；
At least one groove 140 is provided with the silicon chip, and the openend of the groove 140 is located at outside p-type
Prolong the surface of layer 130, the bottom of the groove 140 is located in N-type epitaxy layer 120；
The first silicon oxide layer in the side wall and bottom of the groove 140 being covered in the N-type epitaxy layer 120
150；
The first polysilicon layer 160 being covered on first silicon oxide layer 150, and first polysilicon layer
160 fill up the groove 140 in the N-type epitaxy layer 120；
The second silicon oxide layer being covered on first silicon oxide layer 150 and first polysilicon layer 160
170, and second silicon oxide layer 170 is covered in the side wall of the groove 140 in the p-type epitaxial layer 130
On；
The second polysilicon layer 180 being covered on second silicon oxide layer 170, and second polysilicon layer
180 fill up the groove 140 in the p-type epitaxial layer 130；
The dielectric material 190 being covered on second polysilicon layer 180 and second silicon oxide layer 170；
And
The metal material 200 being covered on the p-type epitaxial layer 130 and the dielectric material 190.
Further, the thickness of first silicon oxide layer 150 is 0.1 micron to 1 micron.
Further, the thickness of second silicon oxide layer 170 is 0.01 micron to 0.1 micron.
It should be noted that the VDMOS provided of the present embodiment preparation method, technique is simple, easily
In realization；Because the polysilicon layer in groove is separated by silicon dioxide layer, therefore when outside p-type
When prolonging the polysilicon layer (i.e. the second polysilicon layer 180) on layer 130 and being powered, do not interfere with positioned at N
Polysilicon layer (i.e. the first polysilicon layer 160) in type epitaxial layer 120, i.e., when the second polysilicon layer 180 is logical
When electricity produces current potential, current potential will not be produced on the first polysilicon layer 160, is entered outside without extra increase N-type
Prolong the gate leakage capacitance in layer 120；Meanwhile because adding the thickness of the first silicon oxide layer 150 so that be located at
Gate leakage capacitance 1, gate leakage capacitance 2 and grid leak caused by the side wall of groove and the first silicon oxide layer 150 of bottom
Electric capacity 3 can reduce that (principle of foundation is that the thickness of gate leakage capacitance and silicon oxide layer is inversely proportional, i.e. silica
The thickness of layer is bigger, and the gate leakage capacitance of formation is smaller), the grid leak electricity in VDMOS is reduced in this way
Hold, and then reduce the switching loss of VDMOS device, improve the operating efficiency of VDMOS device.
Above-described is the preferred embodiment of the present invention, it should be pointed out that for the ordinary people of the art
For member, some improvements and modifications can also be made under the premise of principle of the present invention is not departed from, these
Improvements and modifications are also within the scope of the present invention.
Claims (13)
- A kind of 1. preparation method of semiconductor field effect transistor, it is characterised in that including：The first silicon oxide layer is formed in the groove of silicon chip；Cover the first polysilicon layer on first silicon oxide layer, and first polysilicon layer fill up it is described Groove；First silicon oxide layer and first polysilicon layer are performed etching, retain the first of predetermined depth Silicon oxide layer and the first polysilicon layer；The second silicon oxide layer is formed in the outer surface of groove and groove；The second polysilicon layer is filled in the groove of second silicon oxide layer parcel；Filled media and metal on silicon chip, form semiconductor field effect transistor.
- 2. preparation method according to claim 1, it is characterised in that the thickness of first silicon oxide layer Spend for 0.1 micron to 1 micron.
- 3. preparation method according to claim 1, it is characterised in that the shape in the groove of silicon chip It is specially into the step of the first silicon oxide layer：Using photoresist as mask, performed etching on silicon chip, form groove, the bottom position of the groove In the N-type epitaxy layer of the silicon chip；Thermal oxide is carried out, the first silicon oxide layer is generated in the side wall of the groove and bottom.
- 4. preparation method according to claim 3, it is characterised in that the quarter performed etching on silicon chip Etching method includes：Dry etching and/or wet etching.
- 5. preparation method according to claim 3, it is characterised in that the first silicon oxide layer covering In the outer surface of the groove.
- 6. preparation method according to claim 1, it is characterised in that described to first silica Layer and first polysilicon layer perform etching, and retain the first silicon oxide layer and the first polysilicon of predetermined depth Layer the step of be specially：The first silicon oxide layer in the groove in the p-type epitaxial layer of silicon chip and the are removed using dry etching One polysilicon layer, retain the first silicon oxide layer and the first polysilicon layer in the groove being located in N-type epitaxy layer.
- 7. preparation method according to claim 1, it is characterised in that the thickness of second silicon oxide layer Spend for 0.01 micron to 0.1 micron.
- 8. preparation method according to claim 1, it is characterised in that described in groove and groove Outer surface formed the second silicon oxide layer the step of be specially：Formed in the trench cover first silicon oxide layer and the first polysilicon layer the second silicon oxide layer, And it is also formed with the second silicon oxide layer in the side wall of the groove and outer surface.
- 9. preparation method according to claim 1, it is characterised in that described in second silica The step of filling the second polysilicon layer, is specially in the groove of layer parcel：The second polysilicon layer, and institute are covered on the second silicon oxide layer of the outer surface of the groove and side wall State the second polysilicon layer and fill up whole groove；Etching removes the second polysilicon layer positioned at the outer surface of groove.
- 10. preparation method according to claim 1, it is characterised in that described filled on silicon chip is situated between Matter and metal, formed semiconductor field effect transistor the step of be specially：The filling of Filled Dielectrics and etching and metal is carried out on silicon chip, obtains semiconductor field effect transistor.
- A kind of 11. semiconductor field effect transistor, it is characterised in that including：Silicon chip, the silicon chip include：Silicon substrate, the N-type epitaxy layer being covered in above silicon substrate and covering P-type epitaxial layer above N-type epitaxy layer；At least one groove is provided with the silicon chip, and the openend of the groove is located at p-type epitaxial layer table Face, the bottom of the groove are located in N-type epitaxy layer；The first silicon oxide layer in the side wall and bottom of the groove being covered in the N-type epitaxy layer；The first polysilicon layer being covered on first silicon oxide layer, and first polysilicon layer is by the N Groove in type epitaxial layer fills up；The second silicon oxide layer being covered on first silicon oxide layer and first polysilicon layer, and it is described Second silicon oxide layer is covered in the side wall of the groove in the p-type epitaxial layer；The second polysilicon layer being covered on second silicon oxide layer, and second polysilicon layer is by the P Groove in type epitaxial layer fills up；The dielectric material being covered on second polysilicon layer and second silicon oxide layer；AndThe metal material being covered on the p-type epitaxial layer and the dielectric material.
- 12. semiconductor field effect transistor according to claim 11, it is characterised in that described first The thickness of silicon oxide layer is 0.1 micron to 1 micron.
- 13. semiconductor field effect transistor according to claim 11, it is characterised in that described second The thickness of silicon oxide layer is 0.01 micron to 0.1 micron.
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| CN201610322620.6A CN107393824A (en) | 2016-05-16 | 2016-05-16 | A kind of semiconductor field effect transistor and preparation method thereof |
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| CN201610322620.6A CN107393824A (en) | 2016-05-16 | 2016-05-16 | A kind of semiconductor field effect transistor and preparation method thereof |
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| CN201610322620.6A Pending CN107393824A (en) | 2016-05-16 | 2016-05-16 | A kind of semiconductor field effect transistor and preparation method thereof |
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| US20060157779A1 (en) * | 2005-01-20 | 2006-07-20 | Tsuyoshi Kachi | Semiconductor device and manufacturing method of the same |
| CN103489913A (en) * | 2012-06-13 | 2014-01-01 | 株式会社东芝 | Semiconductor device and method for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20060157779A1 (en) * | 2005-01-20 | 2006-07-20 | Tsuyoshi Kachi | Semiconductor device and manufacturing method of the same |
| CN103489913A (en) * | 2012-06-13 | 2014-01-01 | 株式会社东芝 | Semiconductor device and method for manufacturing same |
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