CN107362448B - A kind of automatic wake-up circuit applied to pacemaker internal radio communication circuit - Google Patents
A kind of automatic wake-up circuit applied to pacemaker internal radio communication circuit Download PDFInfo
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- CN107362448B CN107362448B CN201710488903.2A CN201710488903A CN107362448B CN 107362448 B CN107362448 B CN 107362448B CN 201710488903 A CN201710488903 A CN 201710488903A CN 107362448 B CN107362448 B CN 107362448B
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/372—Arrangements in connection with the implantation of stimulators
- A61N1/37211—Means for communicating with stimulators
- A61N1/37217—Means for communicating with stimulators characterised by the communication link, e.g. acoustic or tactile
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/362—Heart stimulators
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/372—Arrangements in connection with the implantation of stimulators
- A61N1/37211—Means for communicating with stimulators
- A61N1/37252—Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/372—Arrangements in connection with the implantation of stimulators
- A61N1/37211—Means for communicating with stimulators
- A61N1/37252—Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data
- A61N1/37276—Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data characterised by means for reducing power consumption during telemetry
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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Abstract
The present invention relates to a kind of automatic wake-up circuits applied to pacemaker internal radio communication circuit.Vitro program controlled instrument and intracorporeal heart pacemaker are carried out data transmission in a manner of carrier free baseband digital signal by the coupling of inductance coil, close function of the intracorporeal heart pacemaker telecommunication circuit other than arousal function when without program control instrument and the transmission of pacemaker data.When waking up, the working method of intracorporeal heart pacemaker telecommunication circuit arousal function is discontinuous work, 32ms is opened in 1s, when vitro program controlled instrument needs to carry out data interaction with intracorporeal heart pacemaker, intracorporeal heart pacemaker telecommunication circuit is waken up by continuously transmitting specific wake-up pulse group, telecommunication circuit is opened if successfully waking up and is converted to continuous operation mode.Intracorporeal heart pacemaker telecommunication circuit is opened so as to control by vitro program controlled instrument, its operating mode is converted, interference signal can also be prevented to the false wake-up of telecommunication circuit.
Description
Technical field
The invention belongs to integrated circuit fields, and in particular to a kind of applied to pacemaker internal radio communication circuit
Automatic wake-up circuit.
Background technique
Modern pacemaker nearly all has the function of two-way communication, i.e., will be not after pacemaker implantation human body
The wireless information interaction completed in the case where performing an operation with extraneous program control instrument is operated on, this process needs pacemaker to have corresponding nothing
Line telecommunication circuit.Pacemaker is powered by single non-exchange battery, generally requires work for 10 years even more long, in power consumption
Requirement it is extremely harsh, and pacemaker work most times in be not with program control instrument carry out data interaction
Demand, therefore modern pacemaker requires when without data exchange, communication close circuit reduces the operation function of pacemaker
Consumption, telecommunication circuit wakes up in which cannot be disturbed signal error when without data exchange, when needing to carry out data exchange, journey
Control instrument will guarantee correctly wakes up communications circuitry.The main method of wakes up communications circuitry is controlled using outside plus magnetic field at present
Intracorporal dry-reed tube switch is made to open and close intra-body communication circuit.This method needs additional tongue tube device, and
Volume externally-applied magnetic field is wanted, integrated level is low and process is complicated, while can open telecommunication circuit, false wakeups rate by any external magnetic field
It is high.For telecommunication circuit, a high integration, can send the wake-up that signal is correctly waken up by program control instrument at low-power consumption
Circuit is essential.
Summary of the invention
It is an object of the invention to overcome above-mentioned disadvantage existing in the prior art, provide a kind of applied to pacemaker
The automatic wake-up circuit of internal radio communication circuit has the advantages that low in energy consumption, fully integrated, false wakeups rate is low, and entire mistake
Journey does not need manual intervention, easy to operate, while circuit structure is simple, and the inessential working time is short, low in energy consumption, can effectively mention
High pacemaker power consumption management efficiency saves pacemaker battery energy, reduces cost, improves pacemaker working performance.
To achieve the above object, the invention adopts the following technical scheme:
A kind of automatic wake-up circuit applied to pacemaker internal radio communication circuit, including the detection of the first rising edge
Circuit, Divide-by-3 circuit determine window generation circuit and wake up decision circuit, and the judgement window generation circuit includes rising
Along counting circuit, the second rising edge detection circuit and rising edge to judgement window terminating distance decision circuit；The inspection of first rising edge
The input terminal of slowdown monitoring circuit is connected to the input terminal P2 of wake-up circuit, and output end connection determines the enable end of window generation circuit and upper
It rises along the enable end of counting circuit；The input terminal of Divide-by-3 circuit is connected to input clock signal CLK port P3, output end connection
To the input terminal for determining window generation circuit；The input terminal of rising edge counting circuit is connected to the input terminal P2 of wake-up circuit, on
Rise along the high level output end of counting circuit be connected to the second rising edge detection circuit enable end and rising edge to judgement window
The input terminal of terminating distance decision circuit, low level output end are connected to the first rising edge detection circuit；The detection of second rising edge
Circuit input end is connected to the input terminal P2 of wake-up circuit, and output end is connected to the enable end for waking up decision circuit；Rising edge arrives
Determine that the output end of window terminating distance decision circuit is connected to the enable end for waking up decision circuit；Wake up the input of decision circuit
End is connected to the output end for determining window generation circuit, and output end is connected to the output end P4 of wake-up circuit；The wake-up electricity
The output end for the hysteresis comparator that the input terminal P2 on road is connected to telecommunication circuit and wake-up circuit shares, the output of wake-up circuit
End P4 is connected to the input terminal of pacemaker MCU；Scheme control port P5 is connected to the output of telecommunication circuit logic control element
End.
The first rising edge detection circuit includes d type flip flop D1；The D input terminal of d type flip flop D1 and supply voltage phase
Connection, CK input terminal is connected with wake-up circuit input port, Q output and d type flip flop D2, d type flip flop D3, d type flip flop D4,
D type flip flop D5, d type flip flop D6, d type flip flop D7, d type flip flop D8 reseting port RB be connected, QB output end and d type flip flop
The CK input terminal of D17 is connected, and reseting port RB is connected with two inputs with the output port of door I3.
The Divide-by-3 circuit includes d type flip flop D11 and d type flip flop D12, the D input port of d type flip flop D11 with from
Body QB output port, the CK input port of d type flip flop D12 and one of two inputs or the input port of door I1 are connected, and CK is defeated
Inbound port is connected with two inputs with the output port of door I4, the output port and D of the input of reseting port RB and two or door I1
The reseting port RB of trigger D12 is connected；The D input port of d type flip flop D12 and itself QB output port and two inputs or
One of the input port of door I1 is connected.
The judgement window generation circuit includes: d type flip flop D2, d type flip flop D3, d type flip flop D4 and d type flip flop D5；D
The D input terminal of trigger D2 is connected with the QB output end of itself and the CK input terminal of d type flip flop D3, the CK of d type flip flop D2
Input terminal is connected with the Q output of d type flip flop D12；The D input terminal of d type flip flop D3 and the QB output end of itself and D trigger
The CK input terminal of device D4 is connected；The CK of the D input terminal of d type flip flop D4 and the QB output end of itself and d type flip flop D5 is inputted
End is connected；One of the D input terminal of d type flip flop D5 and itself QB output end and two inputs and input port of door I3 are connected
It connects.
The rising edge counting circuit includes d type flip flop D6, d type flip flop D7 and d type flip flop D8, and the D of d type flip flop D6 is defeated
Enter end to be connected with the QB output end of itself and the CK input terminal of d type flip flop D7, CK input terminal and wake-up circuit input port
P2 is connected；The D input terminal of d type flip flop D7 is connected with itself QB output end, the CK input terminal of Q output and d type flip flop D8
It is connected；The Q output of d type flip flop D8 is connected with the CK input terminal of the RB reset terminal of d type flip flop D9 and d type flip flop D10.
The second rising edge detection circuit includes d type flip flop D9, the D input terminal and supply voltage VDD of d type flip flop D9
Port P1 is connected, and CK input terminal is connected with wake-up circuit input port P2, and QB output port inputs defeated with door I2 with two
One in inbound port is connected.
For the rising edge to determining that window terminating distance decision circuit includes: d type flip flop D10, the D of d type flip flop D10 is defeated
Enter end to be connected with supply voltage vdd terminal mouth P1, the D input port and d type flip flop D16 of RB reseting port and d type flip flop D16
QB output port be connected, Q output mouth and two inputs with one and d type flip flop D13 in the input port of door I2,
The RB reseting port of D14, D15, D16 are connected；The D input port of d type flip flop D13 and itself QB output port and D trigger
The CK input port of device D14 is connected, and CK input port is connected with two inputs with the output port of door I4；D type flip flop D14's
D input port is connected with the CK input port of itself QB output port and d type flip flop D15；The D input terminal of d type flip flop D15
Mouth is connected with the CK input port of itself QB output port and d type flip flop D16.
The wake-up decision circuit includes: two inputs and door I2, and two input and door I2 output port and d type flip flop D17
Reseting port RB is connected；The D input port of d type flip flop D17 is connected with supply voltage vdd terminal mouth P1, Q output mouth with call out
The circuit output port P4 that wakes up is connected.
The input clock signal CLK port P3 is connected with two inputs with one of the input port of door I4；Mode control
Port P5 processed and two inputs and one of the input port of door I3 and two are inputted to be connected with one of the input port of door I4.
The not connected port of all d type flip flops is to empty port, not line；All d type flip flops are that clock rises
Along triggering, low level reset d type flip flop.
The input clock signal is the crystal oscillator clock signal of frequency f=32786Hz.
Compared with prior art, the present invention has the following beneficial effects:
The present invention obtains accurate knowledge by the way that the simple digital circuit of structure is added after the hysteresis comparator of telecommunication circuit
The function of other program control instrument wake-up signal and wakes up communications circuitry.It is compared to existing technology, the present invention does not need to rise in heart
Fight device pcb board on be added additional dry-reed tube switch, open telecommunication circuit without volume externally-applied magnetic field in communication process, because
Magnetic field added by non-program control instrument is also not present by the possibility of telecommunication circuit false wake-up in this.By the detection mode of dual judgement window,
Wake-up condition is strictly limited within the scope of preset signals, almost avoiding non-program control instrument signal or interference signal will communicate
A possibility that circuit false wake-up.Vitro program controlled instrument and intracorporeal heart pacemaker pass through the coupling of inductance coil with carrier free base band
Digital signaling carries out data transmission, and closes intracorporeal heart pace-making when without program control instrument and the transmission of pacemaker data
Function of the device telecommunication circuit other than arousal function.When waking up, intracorporeal heart pacemaker telecommunication circuit arousal function
Working method is discontinuous work, i.e., 32ms is opened in 1s, when vitro program controlled instrument needs to be counted with intracorporeal heart pacemaker
When according to interaction, intracorporeal heart pacemaker telecommunication circuit is waken up by continuously transmitting specific wake-up pulse group, once at
Function wake-up then opens telecommunication circuit and is converted to continuous operation mode.Intracorporeal heart is opened so as to control by vitro program controlled instrument
Pacemaker telecommunication circuit converts its operating mode, and interference signal can also be prevented to the false wake-up of telecommunication circuit.Wake-up identified
Journey is to be automatically performed, and is not required to manual intervention, while circuit structure is simple, low to the power consumption consumption under wake-up states, is waken up successfully
It automatically controls telecommunication circuit and enters communication operation mode, and wake-up circuit is automatically closed, reopened again after to be communicated,
Effectively improve pacemaker power consumption management efficiency, saving pacemaker battery can be excessive, extends pacemaker service life, reduce at
This.
Detailed description of the invention
Fig. 1 is the wake-up schematic diagram of pacemaker internal radio communication circuit；
Fig. 2 is the wake-up circuit schematic diagram of pacemaker internal radio communication circuit；
Fig. 3 is the simulation result diagram (2.8v) of circuit shown in Fig. 2；
Fig. 4 is the simulation result diagram (1.8v) of circuit shown in Fig. 2；
Fig. 5 is the simulation result diagram (long pulsewidth) of circuit shown in Fig. 2；
Fig. 6 is the simulation result diagram (short pulse duration) of circuit shown in Fig. 2；
Fig. 7 is the simulation result diagram (high-frequency) of circuit shown in Fig. 2；
Fig. 8 is the simulation result diagram (low frequency) of circuit shown in Fig. 2.
Specific embodiment
With reference to the accompanying drawing, invention is further described in detail.
Referring to Fig. 1 and 2, a kind of automatic wake-up circuit applied to pacemaker internal radio communication circuit of the invention,
Including the first rising edge detection circuit, Divide-by-3 circuit, determine window generation circuit and wake up decision circuit, determines that window generates
Circuit includes rising edge counting circuit, the second rising edge detection circuit and rising edge to determining window terminating distance decision circuit；
The input terminal of first rising edge detection circuit is connected to the input terminal P2 of wake-up circuit, the output end of the first rising edge detection circuit
Connection determines the enable end of window generation circuit and the enable end of rising edge counting circuit, and the input terminal of Divide-by-3 circuit is connected to
Input clock signal CLK port P3, the output end of Divide-by-3 circuit are connected to the input terminal for determining window generation circuit；Rising edge
The input terminal of counting circuit is connected to the input terminal P2 of wake-up circuit, and the high level output end of rising edge counting circuit is connected to
Input terminal of the enable end and rising edge of two rising edge detection circuits to judgement window terminating distance decision circuit, low level output
End is connected to the first rising edge detection circuit, and the second rising edge detection circuit input terminal is connected to the input terminal P2 of wake-up circuit,
Second rising edge detection circuit output end is connected to the enable end for waking up decision circuit, and rising edge is sentenced to judgement window terminating distance
The output end for determining circuit is connected to the enable end for waking up decision circuit；The input for waking up decision circuit, which is connected to, determines that window generates
The output end of circuit, the output end for waking up decision circuit are connected to the output end P4 of wake-up circuit.The input terminal P2 of wake-up circuit
It is connected to telecommunication circuit and the output end of hysteresis comparator that wake-up circuit shares, the output end P4 of wake-up circuit is connected to the heart
The input terminal of dirty pacemaker MCU.Scheme control port P5 is connected to the output of telecommunication circuit logic control element.
Referring to fig. 2, the first rising edge detection circuit includes: that the D input terminal of d type flip flop D1 is connected with supply voltage, CK
Input terminal is connected with wake-up circuit input port, the reseting port of Q output and d type flip flop D2, D3, D4, D5, D6, D7, D8
RB is connected, and QB output end is connected with the CK input terminal of d type flip flop D17, the output of reseting port RB and two input and door I3
Port is connected.
Divide-by-3 circuit include: d type flip flop D11 D input port and itself QB output port, the CK of d type flip flop D12 it is defeated
Inbound port and one of two inputs or the input port of door I1 are connected, the output port of CK input port and two inputs and door I4
It is connected, reseting port RB is connected with two inputs or the output port of door I1 and the reseting port RB of d type flip flop D12；D touching
The D input port for sending out device D12 is connected with itself QB output port and one of two inputs or the input port of door I1.
Determine that window generation circuit includes: d type flip flop D1；The D input terminal of d type flip flop D2 and itself QB output end and
The CK input terminal of d type flip flop D3 is connected, and the CK input terminal of d type flip flop D2 is connected with the Q output of d type flip flop D12；D touching
The D input terminal of hair device D3 is connected with the QB output end of itself and the CK input terminal of d type flip flop D4；The D of d type flip flop D4 is inputted
End is connected with the QB output end of itself and the CK input terminal of d type flip flop D5；The D input terminal and itself QB of d type flip flop D5 is defeated
Outlet and two inputs are connected with one of the input port of door I3.
Rising edge counting circuit includes: the D input terminal and itself QB output end and d type flip flop D7 of d type flip flop D6
CK input terminal is connected, and CK input terminal is connected with wake-up circuit input port P2；The D input terminal and itself QB of d type flip flop D7
Output end is connected, and Q output is connected with the CK input terminal of d type flip flop D8；The Q output and d type flip flop D9 of d type flip flop D8
RB reset terminal and the CK input terminal of d type flip flop D10 be connected.
Second rising edge detection circuit includes: that the D input terminal of d type flip flop D9 is connected with supply voltage vdd terminal mouth P1, CK
Input terminal is connected with wake-up circuit input port P2, QB output port and two inputs and a phase in the input port of door I2
Connection.
Rising edge to determine window terminating distance decision circuit include: d type flip flop D10 D input terminal and supply voltage VDD
Port P1 is connected, and RB reseting port is connected with the QB output port of the D input port of d type flip flop D16 and d type flip flop D16
It connects, Q output mouth and two inputs and the RB of one in the input port of door I2 and d type flip flop D13, D14, D15, D16 are multiple
Bit port is connected；The CK input port of the D input port of d type flip flop D13 and itself QB output port and d type flip flop D14
It is connected, CK input port is connected with two inputs with the output port of door I4；The D input port and itself QB of d type flip flop D14
The CK input port of output port and d type flip flop D15 are connected；The D input port of d type flip flop D15 and itself QB output end
The CK input port of mouth and d type flip flop D16 are connected；D type flip flop D16.Waking up decision circuit includes: two inputs and door I2 defeated
Exit port is connected with d type flip flop D17 reseting port RB；The D input port of d type flip flop D17 and supply voltage vdd terminal mouth P1 phase
Connection, Q output mouth are connected with wake-up circuit output port P4.The input of input clock signal CLK port P3 and two and door I4
One of input port be connected.One of the input of scheme control port P5 and two and the input port of door I3 and two inputs and door
One of input port of I4 is connected.The not connected port of all d type flip flops is to empty port, not line.All D triggerings
D type flip flop that device is rising edge clock triggering, that low level resets.
It altogether include 17 d type flip flops, 4 logic gates with reference to Fig. 2.In this example, the rising that d type flip flop uses
Along triggering, low level reset d type flip flop, of course, it is possible to what the d type flip flop or high level that are triggered using failing edge were resetted
D type flip flop replaces the d type flip flop in this example.In this case, reverse phase is added before the d type flip flop port of opposite change
Device or the connection input signal negated corresponding with this example on the port of opposite change.Input clock letter in this example
Number CLK is the crystal oscillator clock signal of frequency f=32786Hz, and the design value of wake-up circuit input port institute connection signal is continuous
, single pulsewidth is 122 μ s, and the pulse train of 244 μ s is divided between two adjacent pulse rising edges and rising edge, corresponding ginseng
Examine the INPUT signal in Fig. 3.The clock signal that other frequencies can be used in the clock signal clk of input replaces.In such case
Under, the signal that the wake-up circuit input port for being designed to wake up is connected also does corresponding adjustment, and method of adjustment is three arteries and veins
The pulsewidth of punching and space between the multiple divided by the opposite variation of input clock signal frequency.
When program control instrument has communication requirement, coupled by coil in vivo every the continuous 3 pulses (pulsewidth 122 of 6ms transmission
μ s, rising edge and 244 μ s of rising edge interval between adjacent pulse).To under wake-up states wake-up circuit and hysteresis comparator simultaneously
Be not it is normally opened, open 32ms in 1s, hysteresis comparator and wake-up circuit it is in the open state under when, train of pulse will pass through
Filter circuit and hysteresis comparator are reduced into the identical train of pulse of frequency, that is, adjacent arteries and veins in the output end of hysteresis comparator
Time interval is still 244 μ s between punching, but the width of pulse is had fluctuation by communication distance.This train of pulse is wake-up circuit
The connected signal of input port.
To which under wake-up states, scheme control port P5 is high level, and after successfully waking up, scheme control port P5 becomes low
Level, at this time any input cannot be exported in wake-up circuit output port as a result, wake-up circuit does not also consume power consumption.
For Divide-by-3 circuit: what is loaded on input clock signal CLK is the crystal oscillator clock signal that frequency is 32786Hz,
By with door I4 enter by d type flip flop D11 and D12 and or the input terminal of Divide-by-3 circuit that forms of door I1, i.e. d type flip flop
The CK input port of D11.By the later clock signal of the Q output mouth output three frequency division of d type flip flop D12.
For the first rising edge detection circuit, determine window generation circuit: when the wake-up being connected with the first d type flip flop D1
After there is first rising edge on the P2 of input signal port, since the output port of two inputs and door I3 is high level, the first D touching
The output port Q of hair device D1 becomes high level from low level, and output port QB has high level to become low level.The Q output of D1
Mouth get higher after by the connection of the enable port to d type flip flop D2, D3, D4, D5, D6, D7, D8, this seven d type flip flops are complete
It opens in portion.It is started to work by the judgement window generation circuit that d type flip flop D1, D2, D3, D4, D5 are formed, input is to be triggered by D
The output signal for the Divide-by-3 circuit that the CK input port of device D2 introduces, output port are the Q output mouth of d type flip flop D1.
D type flip flop D2, D3, D4, D5 connect into eight frequency dividing circuits in this partial circuit, as determine window timer,
Timing time after by the QB output end of d type flip flop D5 with the connection of door I3, be then connected to the enable end of d type flip flop D1,
Carry out the output port Q row in d type flip flop D1 into a judgement window, determines that the width of window goes out due to waking up input signal port
Existing first rising edge is asynchronous with the clock signal after three frequency division, and for the range of a fluctuation, range is 640.5 μ s-732 μ
s。
For rising edge counting circuit: while determining window signal for high level, also enabling d type flip flop D6, D7, D8
Make its start-up operation.It is d type flip flop D6, D7, D8 by the enable port of d type flip flop D6, D7, D8 rising edge counting circuit formed
The enable port RB；Input port is wake-up circuit input port P2；Output port is the output port Q of d type flip flop D8.D6,
D7 and D8 connects into a counter, and counting number is 2, defeated after input port P2 two rising edges occurs after enabled
Exit port, i.e. the Q output mouth of d type flip flop D8 become high level from low level.
For the second rising edge detection circuit: the second rising edge detection circuit being made of d type flip flop D9, enable port is
The enable port RB of d type flip flop D9；Input is d type flip flop D9 input port CK, is connected to wake-up circuit input port P2；Output
For the QB output port of d type flip flop D9, it is connected to one of the input port of two inputs Yu door I2.The output of rising edge counting circuit
After becoming high level from low level, d type flip flop D9 is enabled opening, when the input port of d type flip flop D9 detects rising edge,
Exporting the port QB becomes low level from high level, if not detecting rising edge, output port QB keeps high level constant.
For rising edge to judgement window terminating distance decision circuit: being made of d type flip flop D10, D13, D14, D15, D16
Rising edge to determine window terminating distance decision circuit, enable port be d type flip flop D10 CK input port；Input port
For the CK input port of d type flip flop D13, it is connected to the output port of the I4 of two inputs and door, when scheme control port P5 is height
When level, input port, which is equal to, is connected to the port input clock signal CLK；Output port is the Q output of d type flip flop D10
Mouthful.When wake up input port signal there is third rising edge when, that is, rising edge counting circuit output by low level
When jump is high level, the output of d type flip flop D10 is also high level by low level jump, and the enable end of d type flip flop D10 connects
Be as timer connection d type flip flop D13, D14, D15, D16 output: the QB output end of d type flip flop D16.Thus it beats
It has opened another and has determined that window, this window level are the Q output voltage of d type flip flop D10.Window start is that third rising edge is opened
Begin, window width is 213.5 μ s-244 μ s.
For waking up decision circuit: the wake-up decision circuit being made of two inputs with door I2 and d type flip flop D17, input
For the CK input port of d type flip flop D17, export the Q output mouth for D17, enable port be two inputs with two of door I2 it is defeated
Inbound port.The working method for waking up decision circuit is that failing edge occur in the judgement window generated by judgement window generation circuit
When, i.e., judgement whether wake-up at the end of judgement window determines that depend on rising edge determines to judgement window terminating distance
The output of circuit and the second rising edge detection circuit is as a result, if rising edge is to determining window terminating distance decision circuit and second
The output result of rising edge detection circuit is all high level, then the output result for waking up decision circuit is high level, otherwise
For low level.
Fig. 3 is the simulation result diagram of circuit shown in Fig. 2.The figure be 2.8V in the case of simulation result, it can be seen that upper figure
Input signal INPUT shown in solid is the wake-up signal of standard, 122 μ s of pulsewidth, between adjacent rising edges between be divided into 244 μ s；
Wake-up signal WAKEUP shown in upper figure dotted line be shown in determine window terminate after wake up decision circuit successfully issue wake-up arteries and veins
Punching, function are correct.Following figure signal WINDOW_A shown in solid is to wake up decision circuit, it can be seen that is arrived in first rising edge
Shi Chenggong is opened, and is automatically closed within the scope of the window time of design.Signal WINDOW_B shown in following figure dotted line is in third
It rises and determines that window is shown along to judgement window terminating distance, risen on a third along window opening when arriving, in the window of design
It is automatically closed in time range, wake-up signal is reset into low level while closing, and determine window before this close
The window that mouth generation circuit generates has not degraded, therefore can successfully wake up.
Fig. 4 is the simulation result in the case of 1.8V minimum power supply voltage, it can be seen that it is identical with the logical consequence in Fig. 3,
Therefore function is equally correct.
Program control instrument issues the signal that pulsewidth is 122 μ s in real work situation, to the input signal end pulse of wake-up circuit
Width can fluctuate, and change between 25 μ s-130 μ s.Whether Fig. 5 and Fig. 6 is just simulated can also be normal under such limiting case
It wakes up.
Fig. 5 is that pwm input signal becomes 219 μ s, but adjacent rising edges interval is constant, is still 244 μ s, it can be seen that
It still can be with normal wakeup.
Fig. 6 is that pwm input signal becomes 25 μ s, and adjacent rising edges interval is constant, not yet 244 μ s, it can be seen that wakes up function
It can be still correct.
In the case of real work interference signal that may be present be frequency be much higher than or far below wake-up signal pulse
The signal of frequency.Spaced far between of adjacent pulse is much smaller than 100 μ s, and is almost difficult the shape after hysteresis comparator
Formula rising edge, high-intensitive pulse interference signal usual situation lower frequency are much larger than the pulse frequency of wake-up signal.It is therefore prevented that
The object signal of false wake-up is the noise signal pulse of high frequency and the interference source of low frequency.Fig. 7 and Fig. 8 simulates wake-up circuit in height
Working condition under the input of the interference signal of frequency and low frequency.
The case where Fig. 7 is divided into 200 μ s between input signal adjacent pulse rising edge, 100 μ s of pulse width, by can be in figure
See, signal WINDOW_A gives two judgement windows continuously generated here, due to occurring four in a judgement window
Secondary rising edge, therefore wake-up signal is not generated, the signal of more applied in short pulse intervals will not similarly generate wake-up signal.
The case where Fig. 8 is divided into 400 μ s between input signal adjacent pulse rising edge, 100 μ s of pulse width, by can be in figure
Find out, signal WINDOW_A gives two judgement windows continuously generated here, due to only occurring in a judgement window
Rising edge twice, therefore wake-up signal is not generated, the signal in longer pulse spacing will not similarly generate wake-up signal.
In conclusion the present invention can correctly identify program control instrument wake-up signal, to automatically control pacemaker internal wireless
The operating mode of telecommunication circuit, while preventing interference signal to the false wake-up of telecommunication circuit.Process is not required to manual intervention, operation letter
It is single, while circuit structure is simple, the inessential working time is short, and power consumption consumption is low, pacemaker power consumption management efficiency can be effectively improved,
Pacemaker battery energy is saved, cost is reduced.
Claims (7)
1. a kind of automatic wake-up circuit applied to pacemaker internal radio communication circuit, which is characterized in that including first
Rising edge detection circuit, Divide-by-3 circuit determine window generation circuit and wake up decision circuit, and the judgement window generates electricity
Road includes rising edge counting circuit, the second rising edge detection circuit and rising edge to determining window terminating distance decision circuit；The
The input terminal of one rising edge detection circuit is connected to the input terminal P2 of wake-up circuit, and output end connection determines window generation circuit
The enable end of enable end and rising edge counting circuit；The input terminal of Divide-by-3 circuit is connected to input clock signal CLK port P3,
Output end is connected to the input terminal for determining window generation circuit；The input terminal of rising edge counting circuit is connected to the defeated of wake-up circuit
Enter and hold P2, the high level output end of rising edge counting circuit is connected to the enable end of the second rising edge detection circuit and rising edge arrives
Determine the input terminal of window terminating distance decision circuit, low level output end is connected to the first rising edge detection circuit；On second
The input terminal P2 that wake-up circuit is connected to along detection circuit input terminal is risen, output end is connected to the enable end for waking up decision circuit；
Rising edge is connected to the enable end for waking up decision circuit to the output end for determining window terminating distance decision circuit；It wakes up and determines electricity
The input terminal on road is connected to the output end for determining window generation circuit, and output end is connected to the output end P4 of wake-up circuit；It is described
The input terminal P2 of wake-up circuit be connected to telecommunication circuit and the output end of hysteresis comparator that wake-up circuit shares, wake up electricity
The output end P4 on road is connected to the input terminal of pacemaker MCU；Scheme control port P5 is connected to telecommunication circuit logic control
Unit output end；
The first rising edge detection circuit includes d type flip flop D1；The D input terminal of d type flip flop D1 is connected with supply voltage,
CK input terminal is connected with wake-up circuit input port, and Q output and d type flip flop D2, d type flip flop D3, d type flip flop D4, D are triggered
Device D5, d type flip flop D6, d type flip flop D7, d type flip flop D8 reseting port RB be connected, the CK of QB output end and d type flip flop D17
Input terminal is connected, and reseting port RB is connected with two inputs with the output port of door I3；
The rising edge to determine window terminating distance decision circuit include: d type flip flop D10, the D input terminal of d type flip flop D10
It is connected with supply voltage vdd terminal mouth P1, RB reseting port and the D input port of d type flip flop D16 and the QB of d type flip flop D16
Output port is connected, Q output mouth and two inputs with one and d type flip flop D13, D14 in the input port of door I2,
The RB reseting port of D15, D16 are connected；The D input port of d type flip flop D13 and itself QB output port and d type flip flop D14
CK input port be connected, CK input port is connected with two inputs with the output port of door I4；The D of d type flip flop D14 is inputted
Port is connected with the CK input port of itself QB output port and d type flip flop D15；The D input port of d type flip flop D15 with
The CK input port of itself QB output port and d type flip flop D16 are connected；
The wake-up decision circuit includes: two inputs and door I2, and two inputs are resetted with door I2 output port and d type flip flop D17
Port RB is connected；The D input port of d type flip flop D17 is connected with supply voltage vdd terminal mouth P1, Q output mouth and wake-up electricity
Road output port P4 is connected.
2. the automatic wake-up circuit according to claim 1 applied to pacemaker internal radio communication circuit, special
Sign is, the Divide-by-3 circuit includes d type flip flop D11 and d type flip flop D12, the D input port of d type flip flop D11 and itself
QB output port, the CK input port of d type flip flop D12 and one of two inputs or the input port of door I1 are connected, CK input
Port is connected with two inputs with the output port of door I4, and the output port and D of the input of reseting port RB and two or door I1 touch
The reseting port RB of hair device D12 is connected；The D input port of d type flip flop D12 and itself QB output port and two inputs or door
One of input port of I1 is connected.
3. the automatic wake-up circuit according to claim 1 applied to pacemaker internal radio communication circuit, special
Sign is that the judgement window generation circuit includes: d type flip flop D2, d type flip flop D3, d type flip flop D4 and d type flip flop D5；D
The D input terminal of trigger D2 is connected with the QB output end of itself and the CK input terminal of d type flip flop D3, the CK of d type flip flop D2
Input terminal is connected with the Q output of d type flip flop D12；The D input terminal of d type flip flop D3 and the QB output end of itself and D trigger
The CK input terminal of device D4 is connected；The CK of the D input terminal of d type flip flop D4 and the QB output end of itself and d type flip flop D5 is inputted
End is connected；One of the D input terminal of d type flip flop D5 and itself QB output end and two inputs and input port of door I3 are connected
It connects.
4. the automatic wake-up circuit according to claim 1 applied to pacemaker internal radio communication circuit, special
Sign is that the rising edge counting circuit includes d type flip flop D6, d type flip flop D7 and d type flip flop D8, and the D of d type flip flop D6 is defeated
Enter end to be connected with the QB output end of itself and the CK input terminal of d type flip flop D7, CK input terminal and wake-up circuit input port
P2 is connected；The D input terminal of d type flip flop D7 is connected with itself QB output end, the CK input terminal of Q output and d type flip flop D8
It is connected；The Q output of d type flip flop D8 is connected with the CK input terminal of the RB reset terminal of d type flip flop D9 and d type flip flop D10.
5. the automatic wake-up circuit according to claim 1 applied to pacemaker internal radio communication circuit, special
Sign is that the second rising edge detection circuit includes d type flip flop D9, the D input terminal and supply voltage VDD of d type flip flop D9
Port P1 is connected, and CK input terminal is connected with wake-up circuit input port P2, and QB output port inputs defeated with door I2 with two
One in inbound port is connected.
6. the automatic wake-up circuit according to claim 1 applied to pacemaker internal radio communication circuit, special
Sign is, one of the input clock signal CLK port P3 and two inputs and input port of door I4 are connected；Scheme control
Port P5 and two inputs and one of the input port of door I3 and two are inputted to be connected with one of the input port of door I4.
7. the automatic wake-up circuit according to claim 1 applied to pacemaker internal radio communication circuit, special
Sign is that the not connected port of all d type flip flops is to empty port, not line；All d type flip flops are rising edge clock
Triggering, low level reset d type flip flop.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104399183A (en) * | 2014-11-25 | 2015-03-11 | 西安交通大学 | Automatic wake-up circuit applicable to cardiac pacemaker |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104399183A (en) * | 2014-11-25 | 2015-03-11 | 西安交通大学 | Automatic wake-up circuit applicable to cardiac pacemaker |
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