CN107346973B - Pipeline analog-to-digital converter based on time-sharing multiplexing of DAC (digital-to-analog converter) and Sub ADC (analog-to-digital converter) sampling networks - Google Patents
Pipeline analog-to-digital converter based on time-sharing multiplexing of DAC (digital-to-analog converter) and Sub ADC (analog-to-digital converter) sampling networks Download PDFInfo
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- CN107346973B CN107346973B CN201710552666.1A CN201710552666A CN107346973B CN 107346973 B CN107346973 B CN 107346973B CN 201710552666 A CN201710552666 A CN 201710552666A CN 107346973 B CN107346973 B CN 107346973B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
- H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
The invention discloses a sampling-and-holding-free pipeline analog-digital converter technology based on DAC and Sub ADC sampling network time-sharing multiplexing, which is mainly applied to the field of integrated circuits, in particular to the field of analog-digital converters designed by adopting a pipeline structure.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to the technical field of design of an analog-digital converter with a pipeline structure.
Background
The assembly line analog-to-digital converter adopts an assembly line working mode, a single sampling holding result of an input signal is quantized step by step, a complete quantization result is obtained after complete assembly line step quantization, and the conversion speed of the assembly line analog-to-digital converter is increased; due to the existence of the interstage margin amplifier, the requirement of the post-stage pipeline on the comparator is reduced, and the conversion precision which can be achieved by the pipeline analog-to-digital converter is improved, so that the pipeline analog-to-digital converter not only can achieve the high-speed and ultrahigh-speed converter speed of hundred megahertz or even gigahertz, but also can achieve the 16-bit conversion precision requirement.
The pipeline analog-to-digital converter is generally divided into a non-sampling-and-protection pipeline analog-to-digital converter and a sampling-and-protection pipeline analog-to-digital converter, namely whether a sampling-and-holding network is included or not.
The traditional analog-to-digital converter without the sampling and protection pipeline is directly connected with a continuous analog signal by a first-stage residue amplifying circuit (MDAC) and a first-stage Sub analog-to-digital converter (Sub ADC), and the continuous analog signal is tracked, sampled and held. The MDAC and the Sub ADC in the traditional structure are respectively provided with independent sampling and holding networks, and due to the influence of non-ideal factors such as process deviation, constant deviation and the like, the sampling and holding networks of the first-stage MDAC and the first-stage Sub ADC are inevitably mismatched, so that the sampling values of input signals coarsely quantized by the Sub ADC are inconsistent with the sampling values of the input signals in the MDAC margin generation circuit, and the performance of the analog-to-digital converter is reduced.
The prior art has two common methods for reducing the effect of mismatch errors:
firstly, the influence caused by mismatch is reduced to the maximum extent through layout accurate matching, and the defects are as follows: the method only reduces the influence of mismatch errors to the maximum extent, can not completely eliminate the mismatch errors, and the influence of the mismatch errors is more and more serious along with the continuous increase of the frequency of input signals;
secondly, the mismatch error of the MDAC and the Sub ADC sampling holding path is equivalent to the offset error of the comparator for digital correction and compensation, and the defects are that: the method will increase the difficulty of designing the comparator and the difficulty of designing the offset error correction algorithm of the comparator, and the influence will be more and more serious and the hardware consumption will increase with the increase of the input signal frequency.
Disclosure of Invention
Technical problem
The invention aims to solve the problem of mismatch of a first-stage MDAC and a sample-and-hold network of a first-stage Sub ADC in a pipeline analog-to-digital converter and other related technical problems.
Technical scheme
The invention provides a production line analog-digital converter based on DAC and Sub ADC sampling network time-sharing multiplexing, which comprises a first-stage margin gain amplifying circuit and a first-stage Sub analog-digital converter, wherein the sampling holding networks of the first-stage margin gain amplifying circuit and the first-stage Sub analog-digital converter (Sub ADC) are connected in parallel to form time-sharing multiplexing sampling networks which execute different functions at different time sequence stages; in the sampling stage, the time division multiplexing sampling network is used as a sampling and holding network to carry out sampling and holding on an input analog signal; in a Sub ADC coarse quantization stage, the time division multiplexing sampling network introduces a coarse quantization comparison reference level and completes a coarse quantization process by combining an input signal sampled and held in a sampling stage; in the margin signal amplifying stage, the time division multiplexing sampling network introduces analog signals converted from digital codes obtained by coarse quantization, and generates margin signals by combining input signals sampled and held in the input sampling stage.
The working principle of the scheme is as follows: the first-stage MDAC sampling and holding network of the analog-to-digital converter without the sampling and holding assembly line is wholly or partially time-division multiplexed in the first-stage Sub ADC coarse quantization stage, the input signal of the first-stage MDAC margin operation is completely the same as the input signal of the first-stage Sub ADC coarse quantization from the aspect of circuit design, the influence of mismatch of the first-stage MDAC and Sub ADC sampling and holding channels is fundamentally eliminated, and the chip area and the power consumption can be saved by adopting a time-division multiplexing technology.
Furthermore, the pipeline analog-to-digital converter does not need a front-end sample-and-hold circuit, and the first-stage MDAC and the sample-and-hold circuit network of the first-stage Sub ADC are subjected to time-sharing multiplexing according to a certain time sequence.
Specifically, in the sampling stage, the time-division multiplexing sampling network tracks, samples and holds the input analog signal; in a Sub ADC coarse quantization stage, performing coarse quantization on the input signal sampled and held by the time division multiplexing sampling network; in the margin amplifying stage, the analog signal obtained by the coarse quantization result is subtracted from the input signal sampled and held by the time-division multiplexing sampling network by using the coarse quantization result to obtain a margin signal, and the margin signal is amplified and transmitted to the secondary assembly line analog-to-digital converter.
The multiplexing method of the time division multiplexing sampling network at different time sequence stages comprises the following steps:
the time-sharing multiplexing sampling network is connected with an analog signal in a sampling stage, tracks and samples and holds an input analog signal value at the end moment of the sampling stage;
the time division multiplexing sampling network carries out coarse quantization on the analog signal sampled and held in the previous sampling stage at the Sub ADC coarse quantization stage to obtain a coarse quantization digital code;
in the MDAC margin signal amplification stage, the time-division multiplexing sampling network converts the digital code coarsely quantized by the last Sub ADC into an analog signal through a digital-to-analog converter, then subtracts the digital code coarsely quantized by the last Sub ADC from the analog signal sampled and held in the last sampling stage in the time-division multiplexing sampling and holding network to obtain the current margin signal, and amplifies and transmits the margin signal to a lower-stage pipeline analog-to-digital converter through a margin amplifier.
Further, the MDAC sample-and-hold network may only employ partial time division multiplexing for Sub ADCs, that is: the size of the sample-hold network of the SubADC is 1/2N times that of the MDAC sample-hold network, wherein N is a positive integer containing zero, and the value of N is determined according to the conversion rate and the power consumption of the analog-to-digital converter.
Specifically, in the sampling phase, the sample-and-hold network of the MDAC tracks, sample, and holds the input analog signal; in the coarse quantization stage of the subcodc, a part (1/2N times, N is a positive integer containing zero) of the MDAC sample-and-hold network is time-division multiplexed with the coarse quantization of the input signal; in the margin amplifying stage, the analog signal obtained by the coarse quantization result is subtracted from the input signal sampled and held by the MDAC sample-and-hold network by using the coarse quantization result to obtain a margin signal, and the margin signal is amplified and transmitted to the secondary pipeline analog-to-digital converter.
The technical effects are as follows:
the technical scheme of the invention can bring the following beneficial effects:
1) the invention can eliminate the influence caused by the mismatch of the first-stage MDAC and the SubADC sample-hold network of the traditional non-acquisition-and-protection pipeline analog-to-digital converter from the design principle, and improve the conversion performance of the non-acquisition-and-protection pipeline analog-to-digital converter on high-frequency input signals;
2) the invention reuses all or part of the first-stage MDAC sampling and holding network of the analog-to-digital converter without the sampling and holding pipeline in the Sub ADC coarse quantization process in time division, saves the chip area and the power consumption expense of the single sampling and holding network of the Sub ADC, and is very favorable for the design of the low-power consumption analog-to-digital converter.
Drawings
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram of a first-stage 2-bit MDAC and subcodc structure of a non-sampling-and-protection pipeline according to an embodiment of the present invention.
Fig. 2 is a timing diagram of the MDAC and Sub ADC of the first stage of the non-sampling and protection pipeline according to the embodiment of the present invention.
Fig. 3 is a diagram of the effect of an application example of the invention.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
The following embodiment is to illustrate the technical solution of the present invention from the viewpoint of a non-protected pipeline analog-to-digital converter, but this does not limit the application of the technical solution of the present invention to a protected pipeline analog-to-digital converter by a person skilled in the art according to the following technical description.
Description of technical terms
MDAC: the digital signal processing circuit is a first-stage margin gain amplifying circuit in a pipeline analog-to-digital converter, and a sampling and holding network of the first-stage margin gain amplifying circuit is also called an MDAC sampling and holding network.
SubADC: the digital signal processor is a first-stage sub analog-digital converter in a pipeline analog-digital converter, and a sample-hold network of the first-stage sub analog-digital converter is also called an MDAC sample-hold network.
The time sequence stage is three time sequence stages of the pipeline analog-to-digital converter and sequentially comprises a sampling stage, a coarse quantization stage and a margin signal amplification stage; wherein, the coarse quantization stage is also called Sub ADC coarse quantization stage, and the residual signal amplification stage is also called MDAC residual signal amplification stage.
Referring to fig. 1, a schematic diagram of a first stage 2-bit MDAC and sub adc structures of a non-sampling-and-holding pipeline according to an embodiment of the present invention is shown, where the first stage 2-bit MDAC and sub adc structures include a time-division multiplexing sample-and-hold network, an MDAC independent sample-and-hold network, 4 comparators CMOP, and a bottom plate sampling switch ΦspNegative feedback capacitor CfAnd an operational amplifier AMP, the time-division multiplexing sample-and-hold network comprising 4 sampling switches phis4 comparator reference level conducting switchΦc4 margin operation high reference level conducting switch phiB0、ΦB1、ΦB2And phiB34 margin operation low reference level conducting switch phiB0b、ΦB1b、ΦB2bAnd phiB3b4 sampling and amplifying stages conducting switch phisaAnd 4 sampling capacitors CsThe MDAC independent sample-and-hold network comprises 4 sampling switches Φs', 4 comparator reference level conducting switch phic' 4 residue operation high reference level conducting switch phiB0’、ΦB1’、ΦB2' and phiB3' 4 residue operation low reference level conducting switch phiB0b’、ΦB1b’、ΦB2b' and phiB3b', 4 sampling and amplifying stages conducting switch phisa' and 4 sampling capacitors Cs'. all control switches Φ in the MDAC independent sample-and-hold networks’、Φc’、ΦB0’、ΦB1’、ΦB2’、ΦB3’、ΦB0b’、ΦB1b’、ΦB2b’、ΦB3b’、Φsa' size and sampling capacitance Cs' all sizes are control switches phi in time division multiplexing sample-and-hold networks、Φc、ΦB0、ΦB1、ΦB2、ΦB3、ΦB0b、ΦB1b、ΦB2b、ΦB3b、ΦsaAnd a sampling capacitor CsN is a positive integer containing zero, when N is 0, it means that the MDAC has no independent sample-and-hold network, i.e., the MDAC and the Sub ADC time-division multiplex the whole sample-and-hold network.
Referring to fig. 2, a timing diagram of the first stage MDAC and Sub ADC of the non-sampling-and-protection pipeline provided by the embodiment of the present invention is shown, as shown in the figure, when the clock Φ issAnd phisWhen the level is high, the time-sharing multiplexing sampling network and the MDAC independent sampling holding network both enter a sampling state, and the clock phis、Φs’、Φsa、Φsa' and phispThe controlled switch is switched on, all the other switches are switched off, and the sampling capacitor CsAnd Cs' tracking the input signal;
when clock phispAt the arrival of the falling edge, clock phispControlled switch off, sampling capacitor CsAnd CsKeeping the input signal to finish the sampling process of the lower polar plate;
when sampling clock phisAnd phis' on falling edge, Sub ADC coarsely quantizes clock phic、Φc' AND clock phisa、Φsa' start to go high, clock phisAnd phis' controlled switch off, clock phic、Φc' AND clock phisa、Φsa' the controlled switch is turned on, all the other switches are turned off, and four comparators COMP respectively compare the input signal with the reference signal Vref1、Vref2、Vref3And Vref4To obtain a digital code B0、B1、B2And B3Completing the coarse quantization process;
when clock phicAnd phicWhen the 'high level' is reached, the MDAC enters the margin signal generation amplification stage, if the Sub ADC coarse quantization result BxWhen equal to 0, the clock phi is controlledBxAnd phiBxIs at a low level, phiBxbAnd phiBxb' is high; if the result of Sub ADC coarse quantization is BxControl clock phi when 1BxAnd phiBxIs high, phiBxbAnd phiBxb' is low, where (x ═ 0, 1, 2, 3), clock ΦsaAnd phisa' the controlled switch is turned on, controlling the clock phiBxAnd phiBx’、ΦBxbAnd phiBxb' according to the determination result, the high-level controlled switch is turned on, the low-level controlled switch is turned off, and the clock phis、Φs’、Φc、Φc' and phispOff, at the sampling capacitor CsAnd CsThe lower plate of the' is introduced with proper reference voltage to complete the process of generating and amplifying the MDAC margin signal;
when the falling edges of the clocks phi c and phi c 'arrive, the control switches phi Bx and phi Bx', phi Bxb and phi Bxb 'are all converted into low level, the clocks phi s and phi s' enter a high level state, the MDAC and Sub ADC enter the next input signal sampling and holding process, and so on, the … … sampling, holding and quantizing processes of the input signals are sequentially completed by the non-sampling and holding pipeline analog-to-digital converter.
From the above description, it can be seen that the technical scheme of the invention can not only eliminate the influence caused by the mismatch of the first-stage MDAC and Sub ADC sample-and-hold networks of the traditional non-sampling-and-hold pipeline analog-to-digital converter in design principle and improve the conversion performance of the non-sampling-and-hold pipeline analog-to-digital converter on high-frequency input signals, but also reuse all or part of the first-stage MDAC sample-and-hold network of the non-sampling-and-hold pipeline analog-to-digital converter in the Sub ADC coarse quantization process in time division, save the chip area and power consumption cost of the separate sample-and-hold network of the Sub ADC, and is very favorable for the design. The method is particularly suitable for designing and realizing the high-speed, high-precision, high-performance and low-power consumption analog-to-digital converter of the production-line without production guarantee.
For example, see fig. 3, which is an example of the application of the present invention in practice according to the above-mentioned embodiment. As shown in the figure, the time-division multiplexing sampling network may be modularized, and specific circuit connection relationships may be shown in fig. 3 and refer to fig. 1.
In the technical scheme of the invention, the MDAC and Sub ADC with 2-bit coarse quantization precision are mainly used for explanation, and any application with slight variation of the design idea should be considered to be within the protection scope of the invention.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and it is apparent that those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (3)
1. A pipeline analog-to-digital converter based on time division multiplexing of DAC and Sub ADC sampling networks comprises:
a first stage residue gain amplifying circuit;
a first stage sub analog-to-digital converter;
the method is characterized in that:
the sampling and holding network of the first-stage margin gain amplification circuit and the sampling and holding network of the first-stage Sub analog-digital converter (Sub ADC) are connected in parallel to form a time-division multiplexing sampling network which executes different functions at different time sequence stages;
in the sampling stage, the time-division multiplexing sampling network is used as a sampling and holding network to sample and hold the input analog signal, namely the sampling and holding network of the first-stage margin gain amplification circuit and the sampling and holding network of the first-stage sub analog-digital converter simultaneously sample and hold the input analog signal;
in a Sub ADC coarse quantization stage, the time division multiplexing sampling network introduces a coarse quantization comparison reference level, the coarse quantization process is completed through the first-stage Sub analog-digital converter by combining with an input signal sampled and held in the sampling stage, a coarse quantization digital code is obtained, and the sampling holding network of the first-stage residue gain amplification circuit is multiplexed in the Sub ADC coarse quantization stage;
in the phase of amplifying the residual signal, the time-division multiplexing sampling network introduces an analog signal converted from the digital code obtained by coarse quantization, the residual signal is generated by the first-stage residual gain amplifying circuit in combination with the input signal sampled and held in the input sampling phase, and the sampling and holding network of the first-stage sub analog-to-digital converter is multiplexed in the phase of amplifying the residual signal.
2. The DAC and Sub ADC sampling network time division multiplexing based pipeline analog-to-digital converter of claim 1, wherein: the pipeline analog-to-digital converter is a non-acquisition and non-protection pipeline analog-to-digital converter.
3. The DAC and Sub ADC sampling network time division multiplexing based pipeline analog-to-digital converter of claim 1, wherein: the size of a sampling and holding network of the first-stage margin gain amplification circuit is N times of that of a sampling and holding network of the first-stage sub analog-to-digital converter, wherein N is a positive integer, and the value of N is determined according to the conversion rate and the power consumption of the analog-to-digital converter.
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| CN102386921B (en) * | 2011-11-15 | 2014-04-09 | 北京时代民芯科技有限公司 | Mismatch calibration method for streamline ADC (Analog-to-Digital Converter) multi-bit sub DAC (Digital-to0Analog Converter) capacitor |
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| CN106911333A (en) * | 2017-03-06 | 2017-06-30 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter and conversion method based on sampling capacitance randomization |
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