CN107346963B - A kind of pulsewidth translation circuit and delay circuit - Google Patents

A kind of pulsewidth translation circuit and delay circuit Download PDF

Info

Publication number
CN107346963B
CN107346963B CN201710555722.7A CN201710555722A CN107346963B CN 107346963 B CN107346963 B CN 107346963B CN 201710555722 A CN201710555722 A CN 201710555722A CN 107346963 B CN107346963 B CN 107346963B
Authority
CN
China
Prior art keywords
drain
pmos
tube
transistor
nmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710555722.7A
Other languages
Chinese (zh)
Other versions
CN107346963A (en
Inventor
孔谋夫
陈华磊
张丙可
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201710555722.7A priority Critical patent/CN107346963B/en
Publication of CN107346963A publication Critical patent/CN107346963A/en
Application granted granted Critical
Publication of CN107346963B publication Critical patent/CN107346963B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H03K2005/00208—Layout of the delay element using FET's using differential stages

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

The invention belongs to signal converter technique field, a kind of pulsewidth translation circuit and delay circuit are particularly related to.Basic principle of the invention is that the constant current signal generated using capacitor to current source circuit is integrated, the grid of the PMOS tube in parallel with capacitor is controlled using the signal for needing to carry out pulsewidth transformation, to control the variation of capacitance voltage, and pass through voltage detecting circuit and shaping circuit, realize pulsewidth transformation, while by a kind of derivative delay circuit of the pulsewidth translation circuit.The beneficial effects of the present invention are: circuit structure is simple, accurately pulsewidth can be adjusted, while can realize accurately long delay using small capacitances.

Description

Pulse width conversion circuit and delay circuit
Technical Field
The invention belongs to the technical field of power supplies, and particularly relates to a pulse width conversion circuit and a time delay circuit.
Background
The application of pulse signals in the current electronic technology is more and more extensive, common pulse signal waveforms include square waves, rectangular waves and the like, and pulse signals are signals generated in a short time in the whole signal period compared with continuous signals. The pulse signal width is a basic parameter of the pulse signal, i.e. the time width of the pulse, usually expressed as a percentage of the duty cycle, i.e. the pulse width, in a period, the size of which determines the effective value of the voltage applied to the load. In application, the actually provided pulse signal sometimes does not meet the use condition, which needs to convert the pulse signal width, and at present, the commonly used mode, such as inputting the input voltage signal and the sawtooth wave generator into the voltage comparator, can obtain the pulse signals with different duty ratios by controlling the rising slope of the sawtooth wave, and in practical application, the circuit has a complex whole structure, large power consumption and low control precision. Meanwhile, for a delay circuit of a pulse signal in an integrated circuit, an RC delay unit is adopted in the traditional method, but when the delay time exceeds microsecond level, the required resistance and capacitance are large, so that the chip area is too large, and the precision is poor.
Disclosure of Invention
The invention aims to provide a pulse width conversion circuit which is simple in circuit structure and can accurately adjust the pulse duty ratio, and a delay circuit derived according to the pulse width conversion circuit, wherein the delay circuit can accurately realize microsecond-level long delay only by a small capacitor in a picofarad level.
The technical scheme of the invention is as follows: as shown in fig. 2, a pulse width conversion circuit includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M9, a fourth PMOS transistor M10, a fifth PMOS transistor M12, a sixth PMOS transistor M14, a first PMOS transistor M10An NMOS transistor M3, a second NMOS transistor M4, a third NMOS transistor M5, a fourth NMOS transistor M6, a fifth NMOS transistor M7, a sixth NMOS transistor M8, a seventh NMOS transistor M11, an eighth NMOS transistor M13, a ninth NMOS transistor M15, a first capacitor C1And a first resistor R1(ii) a Wherein,
the source electrode of the first PMOS pipe M1 is connected with a power supply VCCIts gate and drain are interconnected; the source electrode of the second PMOS tube M2 is connected with the power supply, and the grid electrode thereof is connected with the drain electrode of the first PMOS tube M1;
the drain of the first NMOS transistor M3 is connected to the drain of the first PMOS transistor M1, and the gate of the first NMOS transistor M3 is connected to the drain of the second PMOS transistor M2; the drain and the gate of the second NMOS transistor M4 are connected with the drain of the second PMOS transistor M2;
the drain of the third NMOS transistor M5 is connected to the source of the first NMOS transistor M3, the gate of the third NMOS transistor M5 is connected to the source of the second NMOS transistor M4, and the source of the third NMOS transistor M5 is connected to the first resistor R1Then grounding; the drain and the gate of the fourth NMOS transistor M6 are connected to the source of the second NMOS transistor M4, and the source of the fourth NMOS transistor M6 is grounded;
the source electrode of the third PMOS pipe M9 is connected with a power supply VCCThe grid of which is connected with an external input signal VinThe drain of which is connected to the first capacitor C1One terminal of (1), a first capacitor C1Another end of the power supply V is connected with a power supplyCC；
The drain of the fifth NMOS transistor M7 is connected to the drain of the third PMOS transistor M9 and the first capacitor C1The gate of the fifth NMOS transistor M7 is connected to the drain of the second PMOS transistor M2; the drain of the sixth NMOS transistor M8 is connected to the source of the fifth NMOS transistor M7, the gate of the sixth NMOS transistor M8 is connected to the source of the second NMOS transistor M4, and the source of the sixth NMOS transistor M8 is grounded;
the source electrode of the fourth PMOS tube M10 is connected with the power supply, and the grid electrode of the fourth PMOS tube M10 is connected with the drain electrode of the third PMOS tube M9; the drain electrode of the seventh NMOS transistor M11 is connected with the drain electrode of the fourth PMOS transistor M10, the gate electrode of the seventh NMOS transistor M11 is connected with the drain electrode of the third PMOS transistor M9, and the source electrode of the seventh NMOS transistor M11 is grounded;
the source electrode of the fifth PMOS tube M12 is connected with the power supply, and the grid electrode of the fifth PMOS tube M12 is connected with the drain electrode of the fourth PMOS tube M10; the drain of the eighth NMOS transistor M13 is connected to the drain of the fifth PMOS transistor M12, the gate of the eighth NMOS transistor M13 is connected to the drain of the fourth PMOS transistor M10, and the source of the eighth NMOS transistor M13 is grounded;
the source electrode of the sixth PMOS tube M14 is connected with the power supply, and the grid electrode of the sixth PMOS tube M14 is connected with the drain electrode of the fifth PMOS tube M12; the drain electrode of the ninth NMOS transistor M15 is connected with the drain electrode of the sixth PMOS transistor M14, the gate electrode of the ninth NMOS transistor M15 is connected with the drain electrode of the fifth PMOS transistor M12, and the source electrode of the ninth NMOS transistor M15 is connected with the power supply;
the connection point of the drain of the sixth PMOS transistor M14 and the drain of the ninth NMOS transistor M15 is the output terminal for outputting the target signal V01。
As shown in fig. 4, the present invention further provides a delay circuit, which is characterized by comprising a seventh PMOS transistor M18, an eighth PMOS transistor M19, a ninth PMOS transistor M16, a tenth PMOS transistor M26, an eleventh PMOS transistor M27, a twelfth PMOS transistor M29, a thirteenth PMOS transistor M31, a fourteenth PMOS transistor M33, a fifteenth PMOS transistor M34, a tenth NMOS transistor M20, an eleventh NMOS transistor M21, a twelfth NMOS transistor M22, a thirteenth NMOS transistor M23, a fourteenth NMOS transistor M24, a fifteenth NMOS transistor M25, a sixteenth NMOS transistor M17, a seventeenth NMOS transistor M28, an eighteenth NMOS transistor M30, a nineteenth NMOS transistor M32, a twentieth NMOS transistor M35, a twenty-first NMOS transistor M36, a second capacitor C53926, and a fifteenth NMOS transistor M3967262And a second resistor R2(ii) a Wherein,
the source electrode of the seventh PMOS tube M18 is connected with the power supply VCCIts gate and drain are interconnected; the source electrode of the eighth PMOS tube M19 is connected with the power supply, and the grid electrode of the eighth PMOS tube M19 is connected with the drain electrode of the seventh PMOS tube M18;
the drain of the tenth NMOS transistor M20 is connected to the drain of the seventh PMOS transistor M18, and the gate of the tenth NMOS transistor M20 is connected to the drain of the eighth PMOS transistor M19; the drain and the gate of the eleventh NMOS transistor M21 are connected with the drain of the eighth PMOS transistor M19;
the drain of the twelfth NMOS transistor M22 is connected to the source of the tenth NMOS transistor M20, the gate of the twelfth NMOS transistor M22 is connected to the source of the eleventh NMOS transistor M21, and the source of the twelfth NMOS transistor M22 is connected through a second resistor R2Then grounding; the drain and the gate of the thirteenth NMOS transistor M23 are connected to the source of the second NMOS transistor M4, and the source of the thirteenth NMOS transistor M23 is grounded;
the drain of the fourteenth NMOS transistor M24 passes through the second capacitor C2The back is connected with a power supply VCC, and the grid electrode of the back is connected with the drain electrode of the eighth PMOS tube M19; the drain of the fifteenth NMOS transistor M25 is connected to the source of the fourteenth NMOS transistor M24, the gate of the fifteenth NMOS transistor M25 is connected to the source of the eleventh NMOS transistor M21, and the source of the fifteenth NMOS transistor M25 is grounded;
the source electrode of the ninth PMOS tube M16 is connected with the power supply, the drain electrode of the sixteenth NMOS tube M17 is connected with the drain electrode of the ninth PMOS tube M16, and the source electrode of the sixteenth NMOS tube M17 is grounded; the gates of the ninth PMOS transistor M16 and the sixteenth NMOS transistor M17 are connected with the external input signal Vin；
The source of the tenth PMOS transistor M26 is connected to the power supply, the gate thereof is connected to the connection point of the drain of the ninth PMOS transistor M16 and the drain of the sixteenth NMOS transistor M17, and the drain of the tenth PMOS transistor M26 is connected to the second capacitor C2The connection point with the drain electrode of the fourteenth NMOS tube M24;
the source of the eleventh PMOS transistor M27 is connected with the power supply, and the grid thereof is connected with the second capacitor C2The connection point with the drain electrode of the fourteenth NMOS tube M24; the drain of the seventeenth NMOS transistor M28 is connected to the drain of the eleventh PMOS transistor M27, and the gate of the seventeenth NMOS transistor M28 is connected to the second capacitor C2The source electrode of the seventeenth NMOS tube M28 is grounded;
the source electrode of the twelfth PMOS tube M29 is connected with a power supply, the drain electrode of the eighteenth NMOS tube M30 is connected with the drain electrode of the twelfth PMOS tube M29, the source electrode of the eighteenth NMOS tube M30 is grounded, and the grid electrodes of the twelfth PMOS tube M29 and the eighteenth NMOS tube M30 are connected with the connection point of the drain electrode of the eleventh PMOS tube M27 and the seventeenth NMOS tube M28;
the source electrode of the thirteenth PMOS tube M31 is connected with the power supply, the drain electrode of the nineteenth NMOS tube M32 is connected with the drain electrode of the thirteenth PMOS tube M31, the source electrode of the nineteenth NMOS tube M32 is grounded, and the grid electrodes of the thirteenth PMOS tube M31 and the nineteenth NMOS tube M32 are connected with the connection point of the drain electrode of the twelfth PMOS tube M29 and the twelfth PMOS tube M29;
the source of the fourteenth PMOS transistor M33 is connected to the power supply, and the gate thereof is connected to the external input signal VinThe source of the fifteenth PMOS transistor M34 is connected to the drain of the fourteenth PMOS transistor M33, the tenthThe grid electrode of the five PMOS tube M34 is connected with the connection point of the drain electrode of the thirteenth PMOS tube M31 and the drain electrode of the nineteenth NMOS tube M32;
the gate of the twentieth NMOS transistor M35 is connected to the external input signal VinThe source of the transistor is grounded; the grid electrode of the twenty-first NMOS transistor M36 is connected with the connection point of the drain electrode of the thirteenth PMOS transistor M31 and the drain electrode of the nineteenth NMOS transistor M32; the source of the twenty-first NMOS transistor M36 is grounded; the connection point of the drain electrode of the twentieth NMOS transistor M35, the drain electrode of the twenty-first NMOS transistor M36 and the drain electrode of the fifteenth PMOS transistor M34 is an output end for outputting a target signal V03。
The delay circuit is provided on the basis of a pulse width conversion circuit.
The invention has the beneficial effects that: the circuit is simple in structure, can accurately adjust the pulse width, and can realize accurate long time delay by adopting a small capacitor.
Drawings
FIG. 1 is a schematic block diagram of a pulse width conversion circuit of the present invention;
FIG. 2 is a schematic diagram of a pulse width conversion circuit according to the present invention;
FIG. 3 is a schematic diagram of a pulse width conversion circuit simulation;
FIG. 4 is a schematic diagram of a delay circuit according to the present invention;
FIG. 5 is a schematic diagram of a delay circuit simulation;
FIG. 6 is a view showing V in FIG. 4o2And VinPerforming NOR operation to obtain Vo3The signal timing relationship diagram of (a);
FIG. 7 is a view showing V in FIG. 4o3And Vo1Performing an OR operation to obtain VoSchematic diagram of (a);
FIG. 8 is a view showing V in FIG. 4o3And Vo1Performing an OR operation to obtain VoThe signal timing relationship diagram of (a);
FIG. 9 is a view V in FIG. 4oAnd VinSchematic timing delay diagram of (1).
Detailed Description
The technical scheme of the invention is described in detail in the following with the accompanying drawings:
the basic principle of the invention is to use a capacitor C1Integrating the constant current signal generated by the current source circuit, and adopting the signal V to be subjected to pulse width conversioninThe grid voltage of a PMOS tube connected with the capacitor in parallel is controlled to control the opening and closing of the PMOS tube; the voltage V when the PMOS transistor is turned off is controlled by changing the size of the capacitor C1 and the width-to-length ratio of the M7 and M8 transistorsC1Or the width-to-length ratio of the transistors M10 and M11 is changed to change the threshold voltage of the inverter, and finally the pulse width conversion is realized.
The principle of the invention is shown in fig. 1, compare fig. 2, wherein transistors M1-M6 form a current source generating circuit generating a constant current I1Of course, the constant current generating circuit can be replaced by other current source generating circuit structures or a bipolar transistor current source generating circuit; m7 and M8 form a current mirror, and the current I can be converted by the current mirror principle1Mirror to I proportionally2And through a capacitor C1To I2Integrating; using signals V which require pulse width conversioninControl and capacitance C1An inverter formed by parallel crystals M9, M7 and M8 forms an integrated voltage detection and waveform conversion circuit, and two inverters formed by M12, M13, M14 and M15 form a signal shaping output circuit.
The working principle of the invention is as follows:
when using the signal V to be pulse-width convertedinWhen the voltage is low, the PMOS transistor M9 is turned on, Vc1Has a value of about VCC，Vo1The output is low level;
when V isinAt high level, M9 is turned off, and V is at this time because the voltage across the capacitor cannot break througho1The output is still low level while the current I is constant2Integrating the capacitor, the voltage across the capacitor increases over time, Vc1Will decrease when Vc1When the voltage is reduced to the threshold voltage of the inverter, the output jumps and changes from low level to high level.
The simulation result of the pulse width conversion circuit is shown in fig. 3, and it can be seen from the figure that the signal V which needs to be pulse width convertedin(pulse width about 10us) after processing by the circuit, its output signal Vo1The pulse width is changed (about 5us pulse width), and the pulse width can be changed by changing the parameters (M7 and M8 width-to-length ratio) of the circuit of the current mirror, i.e. I2And the size of the capacitance value is accurately adjusted.
As shown in fig. 4, the present invention also provides a novel delay circuit based on the pulse width conversion circuit shown in fig. 2. By using the same circuit structure, V is adjustedinAfter passing through an inverter formed by M16 and M17, the control circuit is used for controlling C2Likewise at Vo2The terminal obtains a signal V with changed pulse widtho2. The circuit and simulation results are shown in fig. 4 and 5, respectively. Wherein M33-M36 in FIG. 4 are NOR operation circuits. Then the obtained V is put intoo2And VinV is obtained by NOR operation with NOR circuit composed of M33-M36 in FIG. 4o3FIG. 6 shows Vo3And simultaneously shows the time sequence relation of each signal. By observing Vo3、Vo1And VinIn relation to (3), only need to be Vo3And Vo1By performing an OR operation, the value of V is obtainedinDelayed signal VoThe OR operation is shown in FIG. 7. FIG. 9 shows VoAnd VinTime-delay relationship of (V)oAnd VinIn contrast, the delay is 5 us. Magnitude of delay time and VoAnd VinWhether the pulse widths of the current mirrors in fig. 2 and 4 are completely consistent or not can be determined by changing the parameters of the circuits of the current mirrors in fig. 2 and 4 (M7 and M8 and M2)Width to length ratio of 4 to M25), i.e., I2、I4Size of (C), capacitance C1And C2The size of the transistors M10 and M11, and the width-to-length ratios of M27 and M28 are precisely adjusted, and the capacitor C1And C2Typically of the order of picofarads (pF), can be integrated into integrated circuits without occupying large areas.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the modifications to the specific embodiments of the present invention or equivalent substitutions for some technical features can be made without departing from the spirit of the technical solutions of the present invention, and all of them should be covered in the technical solutions of the present invention.

Claims (2)

1. A pulse width conversion circuit is characterized by comprising a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M9, a fourth PMOS tube M10, a fifth PMOS tube M12, a sixth PMOS tube M14, a first NMOS tube M3, a second NMOS tube M4, a third NMOS tube M5, a fourth NMOS tube M6, a fifth NMOS tube M7, a sixth NMOS tube M8, a seventh NMOS tube M11, an eighth NMOS tube M13, a ninth NMOS tube M15 and a first capacitor C1And a first resistor R1(ii) a Wherein,
the source electrode of the first PMOS pipe M1 is connected with a power supply VCCIts gate and drain are interconnected; the source of the second PMOS transistor M2 is connected to the power supply,the grid electrode of the first PMOS tube M1 is connected with the drain electrode of the first PMOS tube M1;
the drain of the first NMOS transistor M3 is connected to the drain of the first PMOS transistor M1, and the gate of the first NMOS transistor M3 is connected to the drain of the second PMOS transistor M2; the drain and the gate of the second NMOS transistor M4 are connected with the drain of the second PMOS transistor M2;
the drain of the third NMOS transistor M5 is connected to the source of the first NMOS transistor M3, the gate of the third NMOS transistor M5 is connected to the source of the second NMOS transistor M4, and the source of the third NMOS transistor M5 is connected to the first resistor R1Then grounding; the drain and the gate of the fourth NMOS transistor M6 are connected to the source of the second NMOS transistor M4, and the source of the fourth NMOS transistor M6 is grounded;
the source electrode of the third PMOS pipe M9 is connected with a power supply VCCThe grid of which is connected with an external input signal VinThe drain of which is connected to the first capacitor C1One terminal of (1), a first capacitor C1Another end of the power supply V is connected with a power supplyCC；
The drain of the fifth NMOS transistor M7 is connected to the drain of the third PMOS transistor M9 and the first capacitor C1The gate of the fifth NMOS transistor M7 is connected to the drain of the second PMOS transistor M2; the drain of the sixth NMOS transistor M8 is connected to the source of the fifth NMOS transistor M7, the gate of the sixth NMOS transistor M8 is connected to the source of the second NMOS transistor M4, and the source of the sixth NMOS transistor M8 is grounded;
the source electrode of the fourth PMOS tube M10 is connected with the power supply, and the grid electrode of the fourth PMOS tube M10 is connected with the drain electrode of the third PMOS tube M9; the drain electrode of the seventh NMOS transistor M11 is connected with the drain electrode of the fourth PMOS transistor M10, the gate electrode of the seventh NMOS transistor M11 is connected with the drain electrode of the third PMOS transistor M9, and the source electrode of the seventh NMOS transistor M11 is grounded;
the source electrode of the fifth PMOS tube M12 is connected with the power supply, and the grid electrode of the fifth PMOS tube M12 is connected with the drain electrode of the fourth PMOS tube M10; the drain of the eighth NMOS transistor M13 is connected to the drain of the fifth PMOS transistor M12, the gate of the eighth NMOS transistor M13 is connected to the drain of the fourth PMOS transistor M10, and the source of the eighth NMOS transistor M13 is grounded;
the source electrode of the sixth PMOS tube M14 is connected with the power supply, and the grid electrode of the sixth PMOS tube M14 is connected with the drain electrode of the fifth PMOS tube M12; the drain of the ninth NMOS transistor M15 is connected to the drain of the sixth PMOS transistor M14, the gate of the ninth NMOS transistor M15 is connected to the drain of the fifth PMOS transistor M12, and the source of the ninth NMOS transistor M15 is grounded;
the connection point of the drain of the sixth PMOS transistor M14 and the drain of the ninth NMOS transistor M15 is the output terminal for outputting the target signal VO1。
2. A time delay circuit is characterized by comprising a seventh PMOS tube M18, an eighth PMOS tube M19, a ninth PMOS tube M16, a tenth PMOS tube M26, an eleventh PMOS tube M27, a twelfth PMOS tube M29, a thirteenth PMOS tube M31, a fourteenth PMOS tube M33, a fifteenth PMOS tube M34, a tenth NMOS tube M20, an eleventh NMOS tube M21, a twelfth NMOS tube M22, a thirteenth NMOS tube M23, a fourteenth NMOS tube M24, a fifteenth NMOS tube M25, a sixteenth NMOS tube M17, a seventeenth NMOS tube M28, an eighteenth NMOS tube M30, a nineteenth NMOS tube M32, a twentieth NMOS tube M35, a twenty-first NMOS tube M36 and a second capacitor C2And a second resistor R2(ii) a Wherein,
the source electrode of the seventh PMOS tube M18 is connected with the power supply VCCIts gate and drain are interconnected; the source electrode of the eighth PMOS tube M19 is connected with the power supply, and the grid electrode of the eighth PMOS tube M19 is connected with the drain electrode of the seventh PMOS tube M18;
the drain of the tenth NMOS transistor M20 is connected to the drain of the seventh PMOS transistor M18, and the gate of the tenth NMOS transistor M20 is connected to the drain of the eighth PMOS transistor M19; the drain and the gate of the eleventh NMOS transistor M21 are connected with the drain of the eighth PMOS transistor M19;
the drain of the twelfth NMOS transistor M22 is connected with the source of the tenth NMOS transistor M20, the gate of the twelfth NMOS transistor M22 is connected with the source of the eleventh NMOS transistor M21, and the source of the twelfth NMOS transistor M22 is grounded through a second resistor R2; the drain and the gate of the thirteenth NMOS transistor M23 are connected to the source of the eleventh NMOS transistor M21, and the source of the thirteenth NMOS transistor M23 is grounded;
the drain of the fourteenth NMOS transistor M24 passes through the second capacitor C2Rear power supply VCCThe grid electrode of the PMOS transistor is connected with the drain electrode of the eighth PMOS transistor M19; the drain of the fifteenth NMOS transistor M25 is connected to the source of the fourteenth NMOS transistor M24, the gate of the fifteenth NMOS transistor M25 is connected to the source of the eleventh NMOS transistor M21, and the source of the fifteenth NMOS transistor M25 is grounded;
the source electrode of the ninth PMOS tube M16 is connected with the power supply, the drain electrode of the sixteenth NMOS tube M17 is connected with the drain electrode of the ninth PMOS tube M16, and the source electrode of the sixteenth NMOS tube M17 is grounded; the gates of the ninth PMOS transistor M16 and the sixteenth NMOS transistor M17 are connected with the external input signal Vin；
The source of the tenth PMOS transistor M26 is connected to the power supply, the gate thereof is connected to the connection point of the drain of the ninth PMOS transistor M16 and the drain of the sixteenth NMOS transistor M17The drain of the ten PMOS transistor M26 is connected with the second capacitor C2The connection point with the drain electrode of the fourteenth NMOS tube M24;
the source of the eleventh PMOS transistor M27 is connected with the power supply, and the grid thereof is connected with the second capacitor C2The connection point with the drain electrode of the fourteenth NMOS tube M24; the drain of the seventeenth NMOS transistor M28 is connected to the drain of the eleventh PMOS transistor M27, and the gate of the seventeenth NMOS transistor M28 is connected to the second capacitor C2The source electrode of the seventeenth NMOS tube M28 is grounded;
the source electrode of the twelfth PMOS tube M29 is connected with a power supply, the drain electrode of the eighteenth NMOS tube M30 is connected with the drain electrode of the twelfth PMOS tube M29, the source electrode of the eighteenth NMOS tube M30 is grounded, and the grid electrodes of the twelfth PMOS tube M29 and the eighteenth NMOS tube M30 are connected with the connection point of the drain electrode of the eleventh PMOS tube M27 and the seventeenth NMOS tube M28;
the source electrode of the thirteenth PMOS tube M31 is connected with the power supply, the drain electrode of the nineteenth NMOS tube M32 is connected with the drain electrode of the thirteenth PMOS tube M31, the source electrode of the nineteenth NMOS tube M32 is grounded, and the grid electrodes of the thirteenth PMOS tube M31 and the nineteenth NMOS tube M32 are connected with the connection point of the drain electrode of the twelfth PMOS tube M29 and the eighteenth NMOS tube M30;
the source of the fourteenth PMOS transistor M33 is connected to the power supply, and the gate thereof is connected to the external input signal VinThe source of the fifteenth PMOS transistor M34 is connected to the drain of the fourteenth PMOS transistor M33, and the gate of the fifteenth PMOS transistor M34 is connected to the connection point between the drain of the thirteenth PMOS transistor M31 and the drain of the nineteenth NMOS transistor M32;
the gate of the twentieth NMOS transistor M35 is connected to the external input signal VinThe source of the transistor is grounded; the grid electrode of the twenty-first NMOS transistor M36 is connected with the connection point of the drain electrode of the thirteenth PMOS transistor M31 and the drain electrode of the nineteenth NMOS transistor M32; the source of the twenty-first NMOS transistor M36 is grounded; the connection point of the drain electrode of the twentieth NMOS transistor M35, the drain electrode of the twenty-first NMOS transistor M36 and the drain electrode of the fifteenth PMOS transistor M34 is an output end for outputting a target signal V03。
CN201710555722.7A 2017-07-10 2017-07-10 A kind of pulsewidth translation circuit and delay circuit Active CN107346963B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710555722.7A CN107346963B (en) 2017-07-10 2017-07-10 A kind of pulsewidth translation circuit and delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710555722.7A CN107346963B (en) 2017-07-10 2017-07-10 A kind of pulsewidth translation circuit and delay circuit

Publications (2)

Publication Number Publication Date
CN107346963A CN107346963A (en) 2017-11-14
CN107346963B true CN107346963B (en) 2019-06-04

Family

ID=60257642

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710555722.7A Active CN107346963B (en) 2017-07-10 2017-07-10 A kind of pulsewidth translation circuit and delay circuit

Country Status (1)

Country Link
CN (1) CN107346963B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010148289A (en) * 2008-12-19 2010-07-01 Fujitsu Ten Ltd Switching regulator circuit
CN102369669A (en) * 2009-04-02 2012-03-07 高通股份有限公司 Techniques for non-overlapping clock generation
CN104270122A (en) * 2014-09-16 2015-01-07 中国科学院微电子研究所 Duty ratio correction circuit
CN105811923A (en) * 2016-02-29 2016-07-27 中国电子科技集团公司第五十八研究所 Clock duty ratio adjusting circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010148289A (en) * 2008-12-19 2010-07-01 Fujitsu Ten Ltd Switching regulator circuit
CN102369669A (en) * 2009-04-02 2012-03-07 高通股份有限公司 Techniques for non-overlapping clock generation
CN104270122A (en) * 2014-09-16 2015-01-07 中国科学院微电子研究所 Duty ratio correction circuit
CN105811923A (en) * 2016-02-29 2016-07-27 中国电子科技集团公司第五十八研究所 Clock duty ratio adjusting circuit

Also Published As

Publication number Publication date
CN107346963A (en) 2017-11-14

Similar Documents

Publication Publication Date Title
CN110557013B (en) PWM dead time control system
US4785262A (en) Pulse generator producing pulses having a width free from a power voltage and a threshold voltage of an inverter used therein
CN106100293A (en) It is applied to current detection circuit and the piezoelectric rectifier of piezoelectric rectifier
CN108809145B (en) Maximum power point tracking control piezoelectric energy acquisition circuit
CN107346963B (en) A kind of pulsewidth translation circuit and delay circuit
CN109672408A (en) A kind of programmable crystal-oscillator circuit of low-power consumption fast start-up
CN104796003A (en) Calculating circuit for output current under DCM (discontinuous conducting mode) of flyback PWM (pulse width modulation) converter
CN107241085B (en) Large-amplitude high-repetition-frequency nanosecond balanced pulse signal generator
CN101764596B (en) Inbuilt miicromicro farad stage capacitance intermittent microcurrent second-level time delay circuit
CN117060890A (en) RC relaxation oscillator
KR101716786B1 (en) Rising edge detection circuit
CN203552172U (en) Singlechip and on-chip power-on reset circuit thereof
CN103475338A (en) High-precision low-voltage oscillator
CN108667278B (en) Programmable delay setting circuit and working method
CN203457106U (en) A crystal oscillator shaping circuit with low power consumption
CN106130518A (en) delay circuit
CN211531068U (en) Self-excited multivibrator circuit
CN106849922A (en) A kind of adjustable delay circuit
CN104216457B (en) A kind of high-order temperature compensation circuit of non-bandgap reference source
CN103490729B (en) A kind of low-power consumption crystal oscillator shaping circuit
CN203965612U (en) A kind of TEV detection prover
CN116827333B (en) Level shift circuit
CN203590154U (en) Oscillator with low phase jitter
CN214754674U (en) Ultrafast pulse laser drive circuit and laser range unit
CN213342171U (en) Programmable adjustable PWM output circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant