CN107346943B - Dual-mode sync rectifier control circuit suitable for DCM and CCM - Google Patents
Dual-mode sync rectifier control circuit suitable for DCM and CCM Download PDFInfo
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- CN107346943B CN107346943B CN201710564643.2A CN201710564643A CN107346943B CN 107346943 B CN107346943 B CN 107346943B CN 201710564643 A CN201710564643 A CN 201710564643A CN 107346943 B CN107346943 B CN 107346943B
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
- H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
- H02M7/2195—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
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- Rectifiers (AREA)
Abstract
Suitable for the dual-mode sync rectifier control circuit of DCM and CCM, belong to technical field of power management.The configuration of the present invention is simple can effectively reduce rectification conduction loss, realize the high efficiency of synchronous rectification.Wherein, the second negative level detector realizes minimum Power MOSFET；Turn-off time shroud module prevents opening by mistake for synchronous rectifier M2 from opening, and opening time shroud module prevents the mistake of synchronous rectifier M2 from turning off；First sampling end bears high pressure using the drain electrode of high tension apparatus LDMOS and DEMOS, avoids and is clamped with drain terminal VD of the Zener to synchronous rectifier M2, prevents the drain terminal VD of synchronous rectifier M2 leakage current over the ground；The above measure realizes the high efficiency of synchronous rectification jointly；In addition synchronization control module is introduced, the synchronous rectification under continuous current mode CCM is realized.
Description
Technical field
The invention belongs to technical field of power management, more particularly to a kind of dual-mode sync suitable for DCM and CCM
Rectifier control circuit.
Background technique
As Modern High-Speed super large-scale integration size constantly reduces, power consumption is constantly reduced, it is desirable that supply voltage
Also lower and lower, output electric current is then increasing.Low pressure, high current output environment under, traditional rectifier diode conducting
Pressure drop is higher, even if can also be generated the pressure drop of 0.4V or more using the Schottky diode of low pressure drop, rectifier loss is caused to increase
Add, power-efficient reduces.Synchronous rectification can substantially reduce rectifying part by using the MOSFET of more low on-resistance
Power consumption, improve the performance of converter, realize the high efficiency of power supply.
Synchronous rectification can be divided into voltage-type driving and current mode drive by driving method, by the source of driving signal
It can be divided into again from driving and outer driving.Wherein, voltage-type is structurally simple, economical efficiently from driving method, is at present by pass
The synchronous rectification actuation techniques of note, voltage-type self-device synchronous rectification are suitable for the applied topology of flyback converter Flyback such as
Shown in Fig. 1.The working principle of the applied topology are as follows: when primary side switch pipe M1 is opened, synchronous commutating control circuit is detected together
Walk drain electrode and the source voltage difference V of rectifying tube M2DS> 0, synchronous rectifier M2 is closed, vice-side winding NSStore energy, system according to
By output capacitance COUTPowering load；When primary side switch pipe M1 is closed, vice-side winding NSVoltage reversal, synchronous rectification control
Circuit detects drain electrode and the source voltage difference V of synchronous rectifier M2DS< 0, synchronous rectifier M2 is opened, vice-side winding NSStorage
The energy deposited is supplied to load, while supplementing output capacitance COUTThe energy of loss.The detection of two zero crossings is voltage-type self-powered
The key of dynamic synchronous rectification, and in practice it is not stringent detection zero crossing, but two are detected close to no-voltage
Negative threshold value judges opening or closing rather than using a zero-crossing comparator for synchronous rectifier M2 using two negative threshold values
The reason is that, can reduce VDSInfluence of the shake of voltage to accurate decision circuitry state.And select one close to zero it is negative
Threshold test point can reduce body diode D2 turn-on time, improve rectification efficiency.In addition, same in synchronous rectifier M2 shutdown
The drain electrode (end VD) of step rectifying tube M2 can cause VD voltage to generate ringing since LC vibrates, and VD ringing voltage may be made
It is opened at 1) opening by mistake synchronous rectifier, reduces rectification efficiency；2) internal components of rectification chip are broken down by high-voltage.For the former,
It usually is shielded accidentally to turn off/open by mistake with one section of TON/TOFF signal and be opened, and for the latter, traditional way is with Zener to VD
Sampling end is clamped, and by VD voltage clamp in a safety level when Zener punctures, but this scheme can make power supply logical
The Zener of breakdown is crossed to ground leakage current, causes the reduction of rectification efficiency.
Summary of the invention
In view of the above shortcomings, the present invention provides a kind of dual-mode sync rectification control electricity suitable for DCM and CCM
Road, structure is simple, can effectively reduce rectification conduction loss, realizes the high efficiency of synchronous rectification.
The technical solution of the present invention is as follows:
Suitable for the dual-mode sync rectifier control circuit of DCM and CCM, including opening time shroud module, turn-off time
Shroud module, the first S/R latch, the second S/R latch, first and door, second and door, drive module, the first Zener Dz1With
Second Zener Dz2,
The synchronous commutating control circuit further includes the first negative level detector, the second negative level detector, ring detection
Device and synchronization control module,
The second negative level detector includes sampling pipe, and the sampling pipe includes the 13rd NMOS tube MN13 and the 14th
NMOS tube MN14, first sampling end of the drain electrode of the 13rd NMOS tube as the synchronous commutating control circuit, source electrode
Export the first input end of the first sampled voltage to the first negative level detector；The drain electrode conduct of 14th NMOS tube
Second sampling end of the synchronous commutating control circuit, source electrode export the second sampled voltage to the first negative level detector
The second input terminal；
The input terminal of the ringing detector connects the first sampling end of the synchronous commutating control circuit；First SR
The end S of latch connects the output end of the ringing detector, and the end R connects the input terminal of the drive module, the connection of the end Q
The input terminal of the turn-off time shroud module and described first with the first input end of door；Described first inputs with the second of door
End connects the output end of the turn-off time shroud module, and third input terminal connects the output of the first negative level detector
The input terminal at end and the opening time shroud module；Described second connect the second negative level inspection with the first input end of door
The output end of device is surveyed, the second input terminal connects the output end of the opening time shroud module；The S of second S/R latch
End connection described first and the output end of door, the end R connect described second and the output end of door and the synchronization control module
Output end, the end Q connect the input terminal of the drive module；
The first Zener Dz1Anode connect the second Zener Dz2Cathode and the synchronization control module input
End, cathode meet supply voltage, the second Zener Dz2Plus earth；The output end of the drive module as it is described synchronize it is whole
The output end of flow control circuit.
Specifically, the synchronous commutating control circuit further includes internal reference and current offset module, for generating benchmark
Voltage VREFAnd bias current.
Specifically, the second negative level detector further includes first resistor R1, second resistance R2,3rd resistor R3,
Four resistance R4, first capacitor C1, the second capacitor C2, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th
NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube
MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 15th NMOS tube MN15, the 16th
NMOS tube MN16, the 17th NMOS tube MN17, the 18th NMOS tube MN18, the first PMOS tube MP1, the second PMOS tube MP2, third
PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube
MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the 11st PMOS tube MP11, the 12nd PMOS tube MP12, the 13rd PMOS
Pipe MP13, the 14th PMOS tube MP14, the 15th PMOS tube MP15, the 16th PMOS tube MP16, the 17th PMOS tube MP17,
18 PMOS tube MP18, the 19th PMOS tube MP19 and the 20th PMOS tube MP20,
The source electrode of the gate interconnection of 13rd NMOS tube MN13 and the 14th NMOS tube MN14, the 13rd NMOS tube MN13 connects
Connect the source electrode and the 17th PMOS tube MP17, the 12nd of the 7th NMOS tube MN7, the 4th NMOS tube MN4, the 11st NMOS tube MN11
The source electrode of the drain electrode of NMOS tube MN12, the 14th NMOS tube MN14 connects third NMOS tube MN3, the 8th NMOS tube MN8 and the tenth
One end of the source electrode of NMOS tube MN10, the drain electrode of the 18th PMOS tube MP18 and the 4th resistance R4, the 4th resistance R4's is another
The drain electrode of the 11st NMOS tube MN11 of end connection；
The gate interconnection of 7th NMOS tube MN7 and the 8th NMOS tube MN8 simultaneously connects the 5th NMOS tube MN5 and the 12nd PMOS
The drain electrode of pipe MP12, the leakage of the source electrode and the 16th PMOS tube MP16 of the 5th NMOS tube MN5 of drain electrode connection of the 7th NMOS tube MN7
Pole, the drain electrode of the source electrode and the 15th PMOS tube MP15 of the 6th NMOS tube MN6 of drain electrode connection of the 8th NMOS tube MN8；
The gate interconnection of 5th NMOS tube MN5 and the 6th NMOS tube MN6 and grid and the drain electrode for connecting third NMOS tube MN3
And the tenth PMOS tube MP10 drain electrode, the 13rd PMOS tube MP13 drain electrode connection the 6th NMOS tube MN6 drain electrode and the 9th
The grid of NMOS tube MN9, source electrode connect the drain electrode of the 7th PMOS tube MP7, and grid connects the 9th PMOS tube MP9, the tenth PMOS
The grid and the 9th PMOS of pipe MP10, the 11st PMOS tube MP11, the 12nd PMOS tube MP12 and the 14th PMOS tube MP14
The drain electrode of pipe MP9 and the second NMOS tube MN2；
The drain electrode of 6th PMOS tube MP6 connects the source electrode of the 12nd PMOS tube MP12, and grid meets the first PMOS tube MP1,
Two PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 7th PMOS tube MP7 and the 8th PMOS
The drain electrode of the grid of pipe MP8 and the first PMOS tube MP1 and the source electrode of the 9th PMOS tube MP9, the drain electrode of the second PMOS tube MP2 connect
The source electrode of tenth PMOS tube MP10, the drain electrode of third PMOS tube MP3 connect the source electrode of the 11st PMOS tube MP11, the 4th PMOS tube
The drain electrode of MP4 connects the source electrode of the 17th PMOS tube MP17 and the 18th PMOS tube MP18, and the drain electrode of the 5th PMOS tube MP5 connects the tenth
The drain electrode of the source electrode of five PMOS tube MP15 and the 16th PMOS tube MP16, the 8th PMOS tube MP8 connects the 14th PMOS tube MP14's
Source electrode；
The grid leak of 4th NMOS tube MN4 is shorted and connects the drain electrode of the 11st PMOS tube MP11, the 15th NMOS tube MN15
Drain electrode meet drain electrode and the 17th NMOS of the 9th NMOS tube MN9, the 16th NMOS tube MN16 and the 14th PMOS tube MP14
The grid of pipe MN17 and the 19th PMOS tube MP19, source electrode are followed by the grid of the 9th NMOS tube MN9 by third capacitor C3；The
The grid of source electrode connection the 18th PMOS tube MP18 and the 16th PMOS tube MP16 of 16 NMOS tube MN16 simultaneously passes through the second electricity
It is grounded after holding C2；The gate interconnection of 18th NMOS tube MN18 and the 20th PMOS tube MP20 connect the 17th NMOS tube MN17 and
The drain electrode of 19th PMOS tube MP19, drain electrode also interconnects and the output end as the second negative level detector；
The grid leak of first NMOS tube MN1 interconnects and connects the grid of the second NMOS tube MN2 and one end of second resistance R2, the
The other end of two resistance R2 connects one end of first resistor R1, one end of first capacitor C1, the 15th PMOS tube MP15 and the tenth
The grid of seven PMOS tube MP17, the equivalent reference voltage V1 of another termination of first resistor R1, another termination of first capacitor C1
Ground；The equivalent reference voltage V1 of a termination of 3rd resistor R3, the drain electrode of the tenth NMOS tube MN10 of another termination；It is described equivalent
Reference voltage V1 is by reference voltage VREFIt is generated by a voltage follower；The grid connection the 11st of tenth NMOS tube MN10
The grid of the grid of NMOS tube MN11, the 12nd NMOS tube MN12, the 15th NMOS tube MN15 connects the 16th NMOS tube MN16's
Grid；
First PNMOS pipe MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube
MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 19th PMOS tube MP19 and the 20th PMOS tube
The source electrode of MP20 meets supply voltage, the first NMOS tube MN1, the second NMOS tube MN2, the 9th NMOS tube MN9, the 12nd NMOS tube
The source electrode of MN12, the 17th NMOS tube MN17 and the 18th NMOS tube MN18 are grounded；
The 13rd NMOS tube MN13 and the 14th NMOS tube MN14 is high pressure lateral diffusion metal oxide semiconductor.
Specifically, the first negative level detector includes the first clamp operational amplifier OP1, the 5th resistance R5, the 6th
Resistance R6, the 21st PMOS tube MP21, the 22nd PMOS tube MP22, the 23rd PMOS tube MP23, the 24th PMOS
Pipe MP24, the 25th PMOS tube MP25, the 26th PMOS tube MP26, the 27th PMOS tube MP27, the 19th NMOS tube
MN19, the 20th NMOS tube MN20, the 21st NMOS tube MN21, the 22nd NMOS tube MN22, the 23rd NMOS tube
MN23,
Described in first input end connection of the grid of 27th PMOS tube MP27 as the first negative level detector
The source electrode of 13rd NMOS tube MN13 in second negative level detector, the grid of the 26th PMOS tube MP26 is as described first
Second input terminal of negative level detector connects the source electrode of the 14th NMOS tube MN14 in the second negative level detector；
The positive input of first clamp operational amplifier OP1 connects reference voltage VREF, negative input connection the tenth
The source electrode of nine NMOS tube MN19 and by being grounded after the 5th resistance R5, output end connects the grid of the 19th NMOS tube MN19；
The grid leak of 21st PMOS tube MP21 is shorted and connects the drain electrode of the 19th NMOS tube MN19, the 22nd PMOS
The grid of pipe MP22, the 23rd PMOS tube MP23 and the 24th PMOS tube MP24；
The grid leak of 20th NMOS tube MN20 is shorted and connects the grid and the 22nd of the 21st NMOS tube MN21
The drain electrode of PMOS tube MP22, source electrode connect the source electrode of the 26th PMOS tube MP26；The drain electrode of 21st NMOS tube MN21 connects
The drain electrode of 23rd PMOS tube MP23 and the grid of the 25th PMOS tube MP25, source electrode are followed by the by the 6th resistance R6
The source electrode of 27 PMOS tube MP27；
The grid leak of 22nd NMOS tube MN22 is shorted and connects the grid and the 24th of the 23rd NMOS tube MN23
The drain electrode of PMOS tube MP24, the drain electrode of the 23rd NMOS tube MN23 connect the drain electrode of the 25th PMOS tube MP25 and as institutes
State the output end of the first negative level detector；
21st PMOS tube MP21, the 22nd PMOS tube MP22, the 23rd PMOS tube MP23, the 24th PMOS
The source electrode of pipe MP24 and the 25th PMOS tube MP25 connect supply voltage, the 26th PMOS tube MP26 and the 27th PMOS tube
The source electrode of the drain electrode of MP27 and the 22nd NMOS tube MN22 and the 23rd NMOS tube MN23 ground connection.
Specifically, the ringing detector includes the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance
R10,28 PMOS tube MP28, the 29th PMOS tube MP29, the 30th PMOS tube MP30, the 31st PMOS tube MP31,
32nd PMOS tube MP32, the first DEMOS pipe DEMOS1, the 2nd DEMOS pipe DEMOS2, the 24th NMOS tube MN24,
25 NMOS tube MN25,
The grid leak of first DEMOS pipe DEMOS1 is shorted and connects the grid and the 28th of the 2nd DEMOS pipe DEMOS2
The drain electrode of PMOS tube MP28, source electrode after the cascaded structure of the 7th resistance R7 and the 9th resistance R9 by being grounded；2nd DEMOS pipe
The drain electrode of DEMOS2 is followed by the first sampling end of the synchronous commutating control circuit by the 8th resistance R8, and source electrode connects the 20th
The drain electrode of nine PMOS tube MP29 and the grid of the 32nd PMOS tube MP32；The grid connection second of 28th PMOS tube MP28
In 19 PMOS tube MP29, the 30th PMOS tube MP30, the 31st PMOS tube MP31 and the first negative level detector
The grid of 24 PMOS tube MP24, the 28th PMOS tube MP28, the 29th PMOS tube MP29, the 30th PMOS tube MP30
Supply voltage is connect with the source electrode of the 31st PMOS tube MP31,
The grid leak of 24th NMOS tube MN24 is shorted and connects the grid and the 30th of the 25th NMOS tube MN25
The source electrode of the drain electrode of PMOS tube MP30, the 24th NMOS tube and the 25th NMOS tube MN25 are grounded, the 25th drain electrode
Connect the drain electrode of the 32nd PMOS tube MP32 and the output end as the ringing detector, the leakage of the 31st PMOS tube MP31
Pole is followed by the second sampling end of the synchronous commutating control circuit by the tenth resistance R10.
Specifically, the synchronization control module includes the second clamp operational amplifier OP2, eleventh resistor R1, the 12nd
Resistance R12, thirteenth resistor R13, the 14th resistance R14, the 15th resistance Rpull, the 33rd PMOS tube MP33, the 30th
Four PMOS tube MP34, the 35th PMOS tube MP35, the 36th PMOS tube MP36, the 26th NMOS tube MN26, the 20th
Seven NMOS tube MN27, the 28th NMOS tube MN28 and the 29th NMOS tube MN29,
The positive input of second clamp operational amplifier OP2 connects reference voltage VREF, negative input connection second
The source electrode of 16 NMOS tube MN26 and by being grounded after eleventh resistor R1, output end connects the 26th NMOS tube MN26's
Grid；
The grid leak of 33rd PMOS tube MP33 is shorted and connects the drain electrode and the 34th of the 26th NMOS tube MN26
The grid of PMOS tube MP34, the drain electrode of the 34th PMOS tube MP34 connect the drain electrode of the 27th NMOS tube MN27, and the 33rd
The source electrode of PMOS tube MP33 and the 34th PMOS tube MP34 connect supply voltage；
The grid leak of 35th PMOS tube MP35 is shorted and connects the grid and the 28th of the 36th PMOS tube MP36
The drain electrode of NMOS tube MN28, source electrode are followed by power supply electricity by the cascaded structure of thirteenth resistor R13 and twelfth resistor R12
The source electrode of pressure, the 36th PMOS tube MP36 passes through the 14th resistance R14 and the 15th resistance RpullCascaded structure be followed by electricity
Source voltage, the drain electrode of the 29th NMOS tube MN29 of drain electrode connection and the output end as the synchronization control module, the tenth
Four resistance R14 and the 15th resistance RpullInput terminal of the series connection point as the synchronization control module；
The gate interconnection of 27th NMOS tube MN27, the 28th NMOS tube MN28 and the 29th NMOS tube MN29,
Its source grounding.
Specifically, the opening time shroud module and turn-off time shroud module are in the rising edge for detecting its input terminal
A low level signal is exported when signal.
Specifically, when the synchronous commutating control circuit is used for flyback converter, the output voltage of the flyback converter
As the supply voltage of the synchronous commutating control circuit, first sampling end samples synchronous rectification in the flyback converter
The drain terminal voltage of pipe, second sampling end sample the source voltage terminal of synchronous rectifier in the flyback converter.
The invention has the benefit that the configuration of the present invention is simple, can effectively reduce rectification conduction loss, realizes and synchronize
The high efficiency of rectification.Wherein when being used for flyback converter, the second negative level detector realizes minimum Power MOSFET；
Turn-off time shroud module prevents opening by mistake for synchronous rectifier M2 from opening, and opening time shroud module prevents the mistake of synchronous rectifier M2
Shutdown；Sampling end is using high tension apparatus LDMOS (i.e. the 13rd NMOS tube MN13 and the 14th NMOS in the second negative level detector
Pipe MN14) and the drain electrode of DEMOS (i.e. the first DEMOS pipe DEMOS2 and the 2nd DEMOS pipe DEMOS2 in ringing detector) hold
By high pressure, avoids and clamped with drain terminal VD of the Zener to synchronous rectifier M2, prevent the drain terminal VD of synchronous rectifier M2
Leakage current over the ground；The above measure realizes the high efficiency of synchronous rectification jointly；In addition synchronization control module is introduced, is realized
Synchronous rectification under continuous current mode CCM.
Detailed description of the invention
Fig. 1 is the applied topology structure chart in framework and embodiment of the invention.
Fig. 2 is signal timing diagram of the circuit work at discontinuous conduct mode DCM in embodiment.
Fig. 3 is signal timing diagram of the circuit work at continuous current mode CCM in embodiment.
Fig. 4 is the circuit diagram of the second negative level detector NLD2 in embodiment.
Fig. 5 is that the circuit of the first negative level detector NLD1 and ringing detector Ringing Detector in embodiment shows
It is intended to.
Fig. 6 is the circuit diagram of synchronization control module SYNC Controller in embodiment.
Specific embodiment
With reference to the accompanying drawing, the technical schemes of the invention are described in detail:
It is applied to flyback converter with the dual-mode sync rectifier control circuit proposed by the present invention suitable for DCM and CCM
It is embodiment when flyback, as shown in Figure 1, wherein bold portion is circuit topology of the invention, it is inclined by internal reference and electric current
Module, ringing detector, the first negative level detector, the second negative level detector, the first S/R latch, the 2nd SR is set to latch
Device, turn-off time shroud module, opening time shroud module, synchronization control module, first and door, second and door, the first Zener
Pipe DZ1, the second Zener DZ2, drive module composition, the first sampling end sample flyback converter in synchronous rectifier M2 drain electrode
Level VD, the source level of the second sampling end sample-synchronous rectifying tube M2, the input terminal of synchronization control module pass through inverse-excitation converting
Plug-in resistance R in deviceSYNCWith plug-in coupled capacitor CSYNCCascaded structure after connect primary side switch pipe drain electrode.In the present embodiment
Synchronous commutating control circuit powered by the output of flyback converter Flyback, internal reference and current offset module give it
Complementary modul block provides reference voltage Vref and bias current Ibias.The specific working mode of circuit in the present embodiment is described below:
If the secondary inductance electric current I before switching tube M1 unlatchingSECZero is had descended to, system works in DCM (electric current
Discontinuous mode) mode.Under DCM mode, when switching tube M1 is closed, the drain electrode level VD of synchronous rectifier M2 sharply declines, when the
One negative level detector, which detects, exports high level when synchronous rectifier M2 drain-source voltage VDS drops to -150mV or less, by
It is high level that two S/R latches, which export set, is opened synchronous rectifier M2 by drive module, while the opening time shields mould
Block detects the rising edge signal of the first negative level detector output, exports a low level pulse, and shielding comes from the second negative electricity
The signal of flat detector, the small sample perturbations that the drain electrode level VD of synchronous rectifier M2 is generated when preventing synchronous rectifier M2 from opening make
Synchronous rectification M2 is accidentally turned off, in synchronous rectifier M2 open stage, secondary inductance electric current ISECSupplying power for outside.With secondary electrical
Feel the energy consumption of Ns, secondary inductance electric current ISECIt is gradually reduced, when the drain voltage for detecting synchronous rectifier M2 drops to zero
When, system judges secondary inductance electric current ISECAlso zero is had descended to, synchronous rectifier M2 is closed.However it is right under actual conditions
It can not accomplish in the zero passage detection of the drain electrode level VD of synchronous rectifier M2 absolutely accurately, if in secondary inductance electric current ISEC
Synchronous rectifier M2 is also not turned off when dropping to zero, load current will by secondary inductance and the synchronous rectifier M2 of conducting to
Ground flows backward, and rectification efficiency is seriously reduced, for this reason, it may be necessary in secondary inductance electric current ISECBy synchronous rectifier M2 before dropping to zero
Shutdown.And when turning off synchronous rectifier M2 in advance, inductive current ISECIt has not degraded to zero, the body of synchronous rectifier M2 will be passed through
Diode D2 afterflow, the conducting damage since the conduction voltage drop of body diode D2 is bigger (generally 0.7V), in the time
Loss-rate is larger, reduces rectification efficiency.Thus the negative threshold value test point closer to zero is conducive to reduce body diode D2 conducting damage
Consumption.The scheme of the present embodiment is when the second negative level detector detects that synchronous rectifier M2 drain-source voltage VDS is greater than -5mV
High level is exported, the timing of opening time shroud module is at this time, and the second latch SR2 is reset to low level, is passed through
Drive module turns off synchronous rectifier M2.After synchronous rectifier M2 shutdown, drain electrode can cause VD electric since LC vibrates
Pressure generates ringing, exports high level when ring detection module detects that VDS voltage is higher than 1.5V, judges that VD starts to shake
Bell, the first S/R latch SR1 are set to high level, and turn-off time shroud module detects the rising of the first S/R latch SR1
One section of low level pulse is generated along signal, the signal from the first negative level detector NLD1 is shielded, prevents synchronous rectifier
M2, which is opened by mistake, to be opened.Signal sequence under DCM mode is as shown in Figure 2.In the present embodiment the first negative level detector detect-
150mV and-the 5mV of the second negative level detector detection is preferred value.
If when synchronous switch pipe M1 were opened, secondary inductance electric current ISECIt has not degraded to zero, system enters CCM (electric current
Continuous mode) mode.Due to secondary inductance electric current ISECZero will not be dropped to, so cut-off signals can not be generated in time next
A period closes synchronous rectifier before arriving, therefore general is not suitable for CCM mode from the synchronous rectification scheme of drive mode.
In order to realize synchronous rectification under CCM and DCM mode simultaneously, invention introduces synchronization control module come quick closedown synchronize it is whole
Flow tube M2.Concrete operating principle is: when primary side switch pipe M1 is opened, M1 drain terminal moment is pulled to low level, the low level pulse
Pass through coupled capacitor C plug-in in flyback converterSYNCWith plug-in resistance RSYNCQuick coupling is to synchronization control module, synchronously control
The input terminal of module i.e. the 14th resistance R14 and the 15th resistance RpullTie point be the end SYNC, when synchronization control module
The SYNC level at the end SYNC exports a low level signal and is sent into the second S/R latch lower than VCC-2V (value is empirical value)
SR2 closes synchronous rectifier M2.First Zener DZ1With the second Zener DZ2For being clamped to SYNC level, prevent
Excessively high SYNC level damages circuit.Signal sequence under CCM mode is as shown in Figure 3.
Second negative level detector in the present embodiment is as shown in figure 4, the module is realized to synchronous rectifier grid end simultaneously
The sampling of level VD and source level VS and the detection of -5mV level.The sampling pipe of second negative level detector i.e. the 13rd NMOS
Pipe MN13 and the 14th NMOS tube MN14 sampling high-voltage LDMOS (lateral diffusion metal oxide semiconductor), it is resistance to using its drain terminal
Pressure characteristic bears the high pressure at the end VD, source voltage terminal, that is, synchronous rectifier M2 drain terminal voltage VD's of the 13rd NMOS tube MN13
Sampled voltage VDSENSE, the sampled voltage of source voltage terminal, that is, synchronous rectifier M2 source voltage terminal VS of the 14th NMOS tube MN14
VSSENSE, by the signal sampled and VSSENSESignal is sent into the module itself and the first negative level detector.Second negative level
The working principle of detector is detailed in patent 201710274231.5.
First negative level detector framework is as shown in Figure 5.The VD sampled by the second negative level detectorSENSESignal and
VSSENSESignal is sent into the first negative level detector, and the turn threshold of the first negative level detector is analyzed as follows:
I=VREF/R5 (1)
V-=VDSENSE+VGS27+IR6 (2)
V+=VSSENSE+VGS27 (3)
(1)-(2):
V--V+=VDSENSE-VSSENSE+IR6 (4)
VDSENSE-VSSENSE=VD-VS (5)
Simultaneous (3), (4), (5):
Thus the turn threshold for obtaining the first negative level detector isRationally the 6th resistance R of setting6, the 5th
Resistance R5The available needs of value -150mV threshold value.
Ring detection module using the drain terminal voltage endurance of two DEMOS (DEMOS1 and DEMOS2) as shown in figure 5, held
By high VD voltage, and when VD voltage is lower, the drain terminal voltage of DEMOS is lower than its source voltage terminal, and the source and drain of LDMOS realizes function
It can exchange, finally realize that normal voltage compares.11st PMOS tube MP11 equal proportion mirror image the 8th PMOS tube MP8 and the 9th
The electric current of PMOS tube MP9, the electric current for realizing the power supply inflow end VD and VS is equal, reduces the error of the sampling of VD and VS.
R7=R8 is set, so the overturning point of ringing detector is
VD=VTHARM (8)
The rationally turn threshold V of the available ring detection module of value of the 9th resistance R9 of settingTHARM=1.5V.
The circuit framework of synchronization control module is as shown in Figure 6.The turn threshold V of the synchronization control module circuitTH,SYNCIt can
To indicate are as follows:
Work as VPRIWhen low level pulse arrives, signal passes through capacitor CSYNCWith resistance RSYNCIt is coupled to synchronous detection module
The end SYNC, the end SYNC will take one electric current I away from supply voltage VCCSYNC, so having:
VSYNC=VCC-ISYNCRpull (10)
Work as ISYNCIt is enough to make VSYNC<VTH,SYNCWhen, comparator will be overturn, and synchronous rectifier M2 is closed.
Plug-in resistance RSYNCIt is determined by (11) formula:
VSYNCIt is pulled to lower than VTH,SYNCTime at least should be more than response time tMINIt just can guarantee synchronization control module energy
Enough responses, so plug-in coupled capacitor CSYNCValue can be determined by (12) formula:
In summary, the invention proposes a kind of high efficiency DCM/CCM dual-mode sync rectifier control circuit, second is utilized
Negative level detector realizes minimum Power MOSFET；The mistake of synchronous rectifier M2 is prevented using turn-off time shroud module
It opens, opening time shroud module prevents the mistake of synchronous rectifier M2 from turning off；VD sampling end using high tension apparatus LDMOS and
High pressure is born in the drain electrode of DEMOS, is avoided and is clamped with Zener to the end VD, prevents the end VD leakage current over the ground.More than
Measure realizes the high efficiency of synchronous rectification jointly.In addition introduce synchronization control module, realize under CCM mode synchronize it is whole
Stream.
Those skilled in the art disclosed the technical disclosures can make various do not depart from originally according to the present invention
Various other specific variations and combinations of essence are invented, these variations and combinations are still within the scope of the present invention.
Claims (8)
1. being suitable for the dual-mode sync rectifier control circuit of DCM and CCM, including opening time shroud module, turn-off time screen
Cover module, the first S/R latch, the second S/R latch, first with door, second with door, drive module, the first Zener (Dz1) and
Second Zener (Dz2),
It is characterized in that, the synchronous commutating control circuit further includes the first negative level detector, the second negative level detector, vibration
Bell detector and synchronization control module,
The second negative level detector includes sampling pipe, and the sampling pipe includes the 13rd NMOS tube (MN13) and the 14th
NMOS tube (MN14), first sampling of the drain electrode of the 13rd NMOS tube (MN13) as the synchronous commutating control circuit
End, source electrode export the first input end of the first sampled voltage to the first negative level detector；14th NMOS tube
(MN14) second sampling end of the drain electrode as the synchronous commutating control circuit, source electrode the second sampled voltage of output is to described
Second input terminal of the first negative level detector；
The input terminal of the ringing detector connects the first sampling end of the synchronous commutating control circuit；First SR is latched
The end S of device connects the output end of the ringing detector, and the end R connects the input terminal of the drive module, described in the connection of the end Q
The input terminal of turn-off time shroud module and described first with the first input end of door；Described first connects with the second input terminal of door
Connect the output end of the turn-off time shroud module, third input terminal connect the first negative level detector output end and
The input terminal of the opening time shroud module；Described second connect the second negative level detector with the first input end of door
Output end, the second input terminal connects the output end of the opening time shroud module；The end S of second S/R latch connects
The output end of described first Yu door is connect, the end R connects described second and the output end of door and the output of the synchronization control module
End, the end Q connects the input terminal of the drive module；
First Zener (the Dz1) anode connect the second Zener (Dz2) cathode and the synchronization control module input
End, cathode meet supply voltage, the second Zener (Dz2) plus earth；The output end of the drive module is as the synchronization
The output end of rectifier control circuit.
2. the dual-mode sync rectifier control circuit according to claim 1 suitable for DCM and CCM, which is characterized in that institute
Stating synchronous commutating control circuit further includes internal reference and current offset module, for generating reference voltage (VREF) and biased electrical
Stream.
3. the dual-mode sync rectifier control circuit according to claim 2 suitable for DCM and CCM, which is characterized in that institute
Stating the second negative level detector further includes first resistor (R1), second resistance (R2), 3rd resistor (R3), the 4th resistance (R4),
First capacitor (C1), the second capacitor (C2), the first NMOS tube (MN1), the second NMOS tube (MN2), third NMOS tube (MN3),
Four NMOS tubes (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th NMOS tube
(MN8), the 9th NMOS tube (MN9), the tenth NMOS tube (MN10), the 11st NMOS tube (MN11), the 12nd NMOS tube (MN12),
15th NMOS tube (MN15), the 16th NMOS tube (MN16), the 17th NMOS tube (MN17), the 18th NMOS tube (MN18),
First PMOS tube (MP1), the second PMOS tube (MP2), third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th PMOS tube
(MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9), the tenth
PMOS tube (MP10), the 11st PMOS tube (MP11), the 12nd PMOS tube (MP12), the 13rd PMOS tube (MP13), the 14th
PMOS tube (MP14), the 15th PMOS tube (MP15), the 16th PMOS tube (MP16), the 17th PMOS tube (MP17), the 18th
PMOS tube (MP18), the 19th PMOS tube (MP19) and the 20th PMOS tube (MP20),
The gate interconnection of 13rd NMOS tube (MN13) and the 14th NMOS tube (MN14), the source electrode of the 13rd NMOS tube (MN13)
Connect the source electrode and the 17th PMOS tube of the 7th NMOS tube (MN7), the 4th NMOS tube (MN4), the 11st NMOS tube (MN11)
(MP17), the drain electrode of the 12nd NMOS tube (MN12), source electrode connection third NMOS tube (MN3) of the 14th NMOS tube (MN14),
The source electrode of 8th NMOS tube (MN8) and the tenth NMOS tube (MN10), the drain electrode of the 18th PMOS tube (MP18) and the 4th resistance
(R4) one end, the other end of the 4th resistance (R4) connect the drain electrode of the 11st NMOS tube (MN11)；
The gate interconnection of 7th NMOS tube (MN7) and the 8th NMOS tube (MN8) simultaneously connects the 5th NMOS tube (MN5) and the 12nd
The drain electrode of PMOS tube (MP12), the drain electrode of the 7th NMOS tube (MN7) connect the source electrode and the 16th PMOS of the 5th NMOS tube (MN5)
The drain electrode of (MP16) is managed, the drain electrode of the 8th NMOS tube (MN8) connects the source electrode and the 15th PMOS tube of the 6th NMOS tube (MN6)
(MP15) drain electrode；
The gate interconnection of 5th NMOS tube (MN5) and the 6th NMOS tube (MN6) and grid and the leakage for connecting third NMOS tube (MN3)
The drain electrode of pole and the tenth PMOS tube (MP10), the drain electrode of the 13rd PMOS tube (MP13) connect the leakage of the 6th NMOS tube (MN6)
The grid of pole and the 9th NMOS tube (MN9), source electrode connect the drain electrode of the 7th PMOS tube (MP7), and grid connects the 9th PMOS tube
(MP9), the tenth PMOS tube (MP10), the 11st PMOS tube (MP11), the 12nd PMOS tube (MP12) and the 14th PMOS tube
(MP14) drain electrode of grid and the 9th PMOS tube (MP9) and the second NMOS tube (MN2)；
The drain electrode of 6th PMOS tube (MP6) connects the source electrode of the 12nd PMOS tube (MP12), grid connect the first PMOS tube (MP1),
Second PMOS tube (MP2), third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 7th PMOS tube
(MP7) and the source electrode of the drain electrode of the grid of the 8th PMOS tube (MP8) and the first PMOS tube (MP1) and the 9th PMOS tube (MP9),
The drain electrode of second PMOS tube (MP2) connects the source electrode of the tenth PMOS tube (MP10), and the drain electrode of third PMOS tube (MP3) connects the 11st
The drain electrode of the source electrode of PMOS tube (MP11), the 4th PMOS tube (MP4) connects the 17th PMOS tube (MP17) and the 18th PMOS tube
(MP18) source electrode, the drain electrode of the 5th PMOS tube (MP5) connect the 15th PMOS tube (MP15) and the 16th PMOS tube (MP16)
The drain electrode of source electrode, the 8th PMOS tube (MP8) connects the source electrode of the 14th PMOS tube (MP14)；
The grid leak of 4th NMOS tube (MN4) is shorted and connects the drain electrode of the 11st PMOS tube (MP11), the 15th NMOS tube
(MN15) drain electrode connect the drain electrode of the 9th NMOS tube (MN9), the 16th NMOS tube (MN16) and the 14th PMOS tube (MP14) with
And the 17th NMOS tube (MN17) and the 19th PMOS tube (MP19) grid, source electrode is followed by the 9th by third capacitor (C3)
The grid of NMOS tube (MN9)；The source electrode of 16th NMOS tube (MN16) connects the 18th PMOS tube (MP18) and the 16th PMOS
It manages the grid of (MP16) and is grounded afterwards by the second capacitor (C2)；18th NMOS tube (MN18) and the 20th PMOS tube (MP20)
Gate interconnection connect the 17th NMOS tube (MN17) and the 19th PMOS tube (MP19) drain electrode, drain electrode also interconnect and conduct
The output end of the second negative level detector；
The grid leak of first NMOS tube (MN1) interconnects and connects the grid of the second NMOS tube (MN2) and one end of second resistance (R2),
The other end of second resistance (R2) connects the one end of first resistor (R1), one end of first capacitor (C1), the 15th PMOS tube
(MP15) and the grid of the 17th PMOS tube (MP17), the equivalent reference voltage (V1) of another termination of first resistor (R1),
The other end of one capacitor (C1) is grounded；The equivalent reference voltage (V1) of one termination of 3rd resistor (R3), another termination the tenth
The drain electrode of NMOS tube (MN10)；The equivalent reference voltage (V1) is by reference voltage (VREF) generated by a voltage follower；
The grid of tenth NMOS tube (MN10) connects the grid of the 11st NMOS tube (MN11), the 12nd NMOS tube (MN12), and the 15th
The grid of NMOS tube (MN15) connects the grid of the 16th NMOS tube (MN16)；
First PNMOS manages (MP1), the second PMOS tube (MP2), third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th PMOS
Manage (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the 19th PMOS tube (MP19) and
The source electrode of 20th PMOS tube (MP20) connects supply voltage, the first NMOS tube (MN1), the second NMOS tube (MN2), the 9th NMOS tube
(MN9), the source electrode ground connection of the 12nd NMOS tube (MN12), the 17th NMOS tube (MN17) and the 18th NMOS tube (MN18)；
13rd NMOS tube (MN13) and the 14th NMOS tube (MN14) are high pressure lateral diffusion metal oxide semiconductor.
4. the dual-mode sync rectifier control circuit according to claim 2 or 3 suitable for DCM and CCM, feature exist
In, the first negative level detector include the first clamp operational amplifier (OP1), the 5th resistance (R5), the 6th resistance (R6),
21st PMOS tube (MP21), the 22nd PMOS tube (MP22), the 23rd PMOS tube (MP23), the 24th PMOS tube
(MP24), the 25th PMOS tube (MP25), the 26th PMOS tube (MP26), the 27th PMOS tube (MP27), the 19th
NMOS tube (MN19), the 20th NMOS tube (MN20), the 21st NMOS tube (MN21), the 22nd NMOS tube (MN22),
23 NMOS tubes (MN23),
First input end connection described the of the grid of 27th PMOS tube (MP27) as the first negative level detector
The source electrode of 13rd NMOS tube (MN13) in two negative level detectors, the grid of the 26th PMOS tube (MP26) is as described
Second input terminal of one negative level detector connects the source electrode of the 14th NMOS tube (MN14) in the second negative level detector；
The positive input of first clamp operational amplifier (OP1) connects reference voltage (VREF), negative input connection the tenth
The source electrode of nine NMOS tubes (MN19) is simultaneously grounded by the 5th resistance (R5) afterwards, and output end connects the 19th NMOS tube (MN19)
Grid；
The grid leak of 21st PMOS tube (MP21) is shorted and connects the drain electrode of the 19th NMOS tube (MN19), the 22nd PMOS
Manage the grid of (MP22), the 23rd PMOS tube (MP23) and the 24th PMOS tube (MP24)；
The grid leak of 20th NMOS tube (MN20) is shorted and connects the grid and the 22nd of the 21st NMOS tube (MN21)
The drain electrode of PMOS tube (MP22), source electrode connect the source electrode of the 26th PMOS tube (MP26)；21st NMOS tube (MN21)
Drain electrode connects the drain electrode of the 23rd PMOS tube (MP23) and the grid of the 25th PMOS tube (MP25), and source electrode passes through the 6th electricity
Resistance (R6) is followed by the source electrode of the 27th PMOS tube (MP27)；
The grid leak of 22nd NMOS tube (MN22) is shorted and connects the grid and the 24th of the 23rd NMOS tube (MN23)
The drain electrode of the drain electrode of PMOS tube (MP24), the 23rd NMOS tube (MN23) connects the drain electrode of the 25th PMOS tube (MP25) simultaneously
Output end as the first negative level detector；
21st PMOS tube (MP21), the 22nd PMOS tube (MP22), the 23rd PMOS tube (MP23), the 24th
The source electrode of PMOS tube (MP24) and the 25th PMOS tube (MP25) connects supply voltage, the 26th PMOS tube (MP26) and second
The source electrode of the drain electrode of 17 PMOS tube (MP27) and the 22nd NMOS tube (MN22) and the 23rd NMOS tube (MN23) connects
Ground.
5. the dual-mode sync rectifier control circuit according to claim 4 suitable for DCM and CCM, which is characterized in that institute
Stating ringing detector includes the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9), the tenth resistance (R10), 28
PMOS tube (MP28), the 29th PMOS tube (MP29), the 30th PMOS tube (MP30), the 31st PMOS tube (MP31),
32 PMOS tube (MP32), the first DEMOS pipe (DEMOS1), the 2nd DEMOS manage (DEMOS2), the 24th NMOS tube
(MN24), the 25th NMOS tube (MN25),
The grid leak of first DEMOS pipe (DEMOS1) is shorted and connects the grid and the 28th of the 2nd DEMOS pipe (DEMOS2)
The drain electrode of PMOS tube (MP28), source electrode after the cascaded structure of the 7th resistance (R7) and the 9th resistance (R9) by being grounded；Second
The drain electrode of DEMOS pipe (DEMOS2) is followed by the first sampling end of the synchronous commutating control circuit by the 8th resistance (R8),
Source electrode connects the drain electrode of the 29th PMOS tube (MP29) and the grid of the 32nd PMOS tube (MP32)；28th PMOS tube
(MP28) grid connects the 29th PMOS tube (MP29), the 30th PMOS tube (MP30), the 31st PMOS tube (MP31)
With the grid of the 24th PMOS tube (MP24) in the first negative level detector, the 28th PMOS tube (MP28), second
The source electrode of 19 PMOS tube (MP29), the 30th PMOS tube (MP30) and the 31st PMOS tube (MP31) connects supply voltage；
The grid leak of 24th NMOS tube (MN24) is shorted and connects the grid and the 30th of the 25th NMOS tube (MN25)
The source electrode of the drain electrode of PMOS tube (MP30), the 24th NMOS tube and the 25th NMOS tube (MN25) is grounded, the 25th
Drain electrode connects the drain electrode of the 32nd PMOS tube (MP32) and the output end as the ringing detector, the 31st PMOS tube
(MP31) drain electrode is followed by the second sampling end of the synchronous commutating control circuit by the tenth resistance (R10).
6. the dual-mode sync rectifier control circuit according to claim 2 or 5 suitable for DCM and CCM, feature exist
In the synchronization control module includes the second clamp operational amplifier (OP2), eleventh resistor (R1), twelfth resistor
(R12), thirteenth resistor (R13), the 14th resistance (R14), the 15th resistance (Rpull), the 33rd PMOS tube (MP33),
34th PMOS tube (MP34), the 35th PMOS tube (MP35), the 36th PMOS tube (MP36), the 26th NMOS tube
(MN26), the 27th NMOS tube (MN27), the 28th NMOS tube (MN28) and the 29th NMOS tube (MN29),
The positive input of second clamp operational amplifier (OP2) connects reference voltage (VREF), negative input connection second
The source electrode of 16 NMOS tubes (MN26) is simultaneously grounded by eleventh resistor (R1) afterwards, and output end connects the 26th NMOS tube
(MN26) grid；
The grid leak of 33rd PMOS tube (MP33) is shorted and connects the drain electrode and the 34th of the 26th NMOS tube (MN26)
The drain electrode of the grid of PMOS tube (MP34), the 34th PMOS tube (MP34) connects the drain electrode of the 27th NMOS tube (MN27), the
The source electrode of 33 PMOS tube (MP33) and the 34th PMOS tube (MP34) connects supply voltage；
The grid leak of 35th PMOS tube (MP35) is shorted and connects the grid and the 28th of the 36th PMOS tube (MP36)
The drain electrode of NMOS tube (MN28), source electrode are followed by electricity by the cascaded structure of thirteenth resistor (R13) and twelfth resistor (R12)
The source electrode of source voltage, the 36th PMOS tube (MP36) passes through the 14th resistance (R14) and the 15th resistance (Rpull) series connection
Structure is followed by supply voltage, and drain electrode connects the drain electrode of the 29th NMOS tube (MN29) and as the synchronization control module
Output end, the 14th resistance (R14) and the 15th resistance (Rpull) input terminal of the series connection point as the synchronization control module；
The grid of 27th NMOS tube (MN27), the 28th NMOS tube (MN28) and the 29th NMOS tube (MN29) is mutual
Even, source grounding.
7. the dual-mode sync rectifier control circuit according to claim 1 suitable for DCM and CCM, which is characterized in that institute
State opening time shroud module and turn-off time shroud module exported in the rising edge signal for detecting its input terminal one it is low
Level signal.
8. the dual-mode sync rectifier control circuit according to claim 1 suitable for DCM and CCM, which is characterized in that institute
When stating synchronous commutating control circuit for flyback converter, the output voltage of the flyback converter is as the synchronous rectification control
The supply voltage of circuit processed, first sampling end samples the drain terminal voltage of synchronous rectifier in the flyback converter, described
Second sampling end samples the source voltage terminal of synchronous rectifier in the flyback converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710564643.2A CN107346943B (en) | 2017-07-12 | 2017-07-12 | Dual-mode sync rectifier control circuit suitable for DCM and CCM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN108494277B (en) * | 2018-05-07 | 2019-10-18 | 电子科技大学 | A kind of synchronous commutating control circuit improving electric efficiency |
| CN108494232B (en) * | 2018-05-07 | 2019-09-27 | 电子科技大学 | A kind of synchronous commutating control circuit for preventing electric current from flowing backward |
| CN108566104B (en) * | 2018-05-07 | 2019-10-18 | 电子科技大学 | A kind of synchronous commutating control circuit |
| CN108494276B (en) * | 2018-05-07 | 2019-10-18 | 电子科技大学 | A kind of synchronous rectification driving circuit |
| CN109004840B (en) * | 2018-07-17 | 2020-02-18 | 东南大学 | Control method for improving output precision of switching power supply |
| CN109088532B (en) * | 2018-09-14 | 2020-02-18 | 电子科技大学 | Current type segmented gate drive circuit with active clamp |
| CN109586581A (en) * | 2018-12-15 | 2019-04-05 | 华南理工大学 | Digital Realization device for full-bridge DC/DC transducer synchronous rectification |
| CN111192917B (en) * | 2019-11-27 | 2023-08-18 | 成都芯源系统有限公司 | Lateral field effect transistor |
| CN111865055B (en) * | 2020-07-27 | 2021-06-04 | 电子科技大学 | Synchronous rectification drive circuit for pulling down grid voltage of synchronous rectification tube in advance |
| CN111934525B (en) * | 2020-08-10 | 2023-04-28 | 电子科技大学 | Negative level detection circuit |
| CN112910227B (en) * | 2021-03-19 | 2022-04-26 | 中国电子科技集团公司第五十八研究所 | Flyback power supply system and control method |
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| KR100730090B1 (en) * | 2006-04-12 | 2007-06-19 | 삼성전기주식회사 | Flyback circuit comprising synchronous rectifier |
| CN101431297B (en) * | 2008-11-26 | 2011-04-27 | 天宝电子（惠州）有限公司 | Synchronous rectifier |
| CN104539163B (en) * | 2014-12-19 | 2018-01-19 | 广州金升阳科技有限公司 | The synchronous rectification control method and its control module of anti exciting converter |
| CN105048836A (en) * | 2015-09-01 | 2015-11-11 | 中国电子科技集团公司第四十三研究所 | Switching power supply flyback synchronous rectification self-driving circuit |
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