CN107346764A - 双面电子封装 - Google Patents

双面电子封装 Download PDF

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Publication number
CN107346764A
CN107346764A CN201710312714.XA CN201710312714A CN107346764A CN 107346764 A CN107346764 A CN 107346764A CN 201710312714 A CN201710312714 A CN 201710312714A CN 107346764 A CN107346764 A CN 107346764A
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encapsulation
lead frame
integrated circuit
attached
circuit die
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肯·M·兰姆
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Atmel Corp
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Atmel Corp
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Abstract

本发明揭示一种双面电子封装及用于制造双面电子封装的方法的实施例。在实施例中，一种电子封装包括：衬底，其具有第一表面及第二表面；引线框，其具有附接到所述衬底的所述第一表面的封装垫特征件；第一集成电路裸片，其附接到所述引线框且电耦合到所述封装垫特征件中的至少一者；及模制件，其在所述衬底的所述第一表面上安置于所述封装垫特征件之间，使得所述封装垫特征件从所述衬底的所述第一表面垂直延伸到所述电子封装的表面，所述封装垫特征件形成暴露于所述电子封装的所述表面上的导电路径。

Description

双面电子封装
技术领域
本发明的标的物大体上涉及电子封装。
背景技术
复杂的系统产品通常集成不同功能。一个公司可能无法制造用于实施不同功能的所有集成电路(IC)装置。难以从其它公司，尤其是从竞争对手获得IC裸片。尽管现今可在市场中购买成品电子封装，但此类成品电子封装可能不允许顾客加入其独特的装置功能以形成最终产品。
发明内容
本发明揭示一种双面电子封装及用于制造双面电子封装的方法的实施例。在实施例中，一种电子封装包括：衬底，其具有第一表面及第二表面；引线框，其具有附接到所述衬底的所述第一表面的封装垫特征件；第一集成电路裸片，其附接到所述引线框且电耦合到所述封装垫特征件中的至少一者；及模制件，其在所述衬底的所述第一表面上安置于所述封装垫特征件之间，使得所述封装垫特征件从所述衬底的所述第一表面垂直延伸到所述电子封装的表面，所述封装垫特征件形成暴露于所述电子封装的所述表面上的导电路径。
在另一实施例中，一种方法包括：将引线框附接到衬底的第一表面，所述引线框具有封装垫特征件；将第一集成电路裸片附接到所述引线框，并将所述第一集成电路裸片电耦合到所述封装垫特征件中的至少一者；及在所述衬底的所述第一表面上将模制件安置于所述封装垫特征件之间，使得所述封装垫特征件从所述衬底的所述第一表面垂直延伸到所述电子封装的表面，所述封装垫特征件形成到所述电子封装的所述表面的导电路径。
在另一实施例中，一种封装堆叠(PoP)组合件包括：第一封装；及第二封装，其耦合到所述第一封装，所述第二封装包含：衬底，其具有第一表面及第二表面；引线框，其具有附接到所述衬底的所述第一表面的封装垫特征件；第一集成电路裸片，其附接到所述引线框且电耦合到所述封装垫特征件中的至少一者；及模制件，其在所述衬底的所述第一表面上安置于所述封装垫特征件之间，使得所述封装垫特征件从所述衬底的所述第一表面延伸到所述电子封装的表面，所述封装垫特征件形成暴露于所述电子封装的所述表面上的导电路径。
附图说明
图1A是根据实施例的双面(或多层)层压衬底的侧视图。
图1B是根据实施例的附接到图1A中所展示的衬底的引线框的侧视图。
图1C是根据实施例的图1B中所展示的引线框的俯视图。
图1D是根据实施例的图1B中所展示的引线框的垫特征件的透视图。
图1E是根据实施例的具有所附接的引线框及集成电路裸片的衬底的侧视图。
图1F是根据实施例的包含模制件的图1E中所展示的结构的侧视图。
图1G是根据实施例的经翻转以暴露用于表面安装技术(SMT)组合件的垫特征件的顶表面的图1F的结构的侧视图。
图1H是根据实施例的图1G的结构的侧视图，其展示在空的附接位点处添加装置以生产最终封装。
图2是根据实施例的封装堆叠(PoP)组合件的侧视图。
图3是根据实施例的具有集成RF屏蔽的实例引线框的俯视图。
图4A是根据实施例的具有集成RF屏蔽的另一实例引线框的俯视图。
图4B是根据实施例的具有冲压天线及RF IC裸片的引线框4A的俯视图。
图5A是根据实施例的实例双面或多层层压衬底的俯视图。
图5B是根据实施例的说明用于SMT组件的焊膏印刷沉积的实例双面或多层层压衬底的侧视图。
图6A是根据实施例的包含裸片附接线接合组件的实例SMT组合件的俯视图。
图6B是根据实施例的包含裸片附接线接合组件的实例SMT组合件的侧视图。
图6C是根据实施例的实例SMT组合件引线框焊料回流的俯视图。
图6D是根据实施例的实例SMT组合件引线框焊料回流的侧视图。
图6E是根据实施例的具有膜辅助包覆模制的实例SMT组合件的侧视图。
图6F是根据实施例的实例经模制SMT组合件的俯视图。
图6G是根据实施例的实例经模制SMT组合件的侧视图。
图7是根据实施例的经配置用于有效散热的封装组合件的侧视图。
图8是根据实施例的制造双面电子封装的实例过程的流程图。
具体实施方式
封装堆叠(PoP)是一种组合垂直离散逻辑与存储器球栅阵列(BGA)封装的IC封装方法。两个或两个以上封装以接口彼此上下堆叠，以在所述封装之间路由信号。这允许例如移动电话的装置中的更高组件密度。现今市场中的POP解决方案不具有后组装附加特征的灵活性以允许最终产品的定制，尤其是由第三方顾客进行的定制。下文本发明描述一种可附接到经完整测试/特性化封装模块的顶表面的灵活的后组装附加电子封装设计/占用面积。
实例双面电子封装
图1A是具有第一表面117a及第二表面117b的双面(或多层)层压衬底100的侧视图。图1B展示具有附接到衬底100的第一表面117a的封装垫特征件116a、116b及离散组件102a、102b的引线框101。图1C是展示封装垫特征件116的引线框101的俯视图。图1D是引线框101的封装垫特征件116的透视图。图1E展示附接到衬底100的集成电路(IC)裸片103，其中裸片附接材料105及线接合件107将IC裸片103电连接到引线框101。IC裸片104是使用焊接凸块106电连接到引线框101的倒装芯片。图1F展示施加膜辅助模制件108以覆盖IC裸片103、104及离散组件102a、102b。应注意，封装垫特征件116a、116b的顶表面通过模制暴露。
图1G是经翻转的模制封装100的侧视图，其中封装的底侧(衬底表面117b)处于顶部。所述底侧可用作用于电子组件的印刷电路板(PCB)，且包含导电迹线。在所展示的实例中，将振荡器109添加到所述底侧。还添加芯片盖111及屏蔽射频(RF)装置112。为了促进添加元件，一或多个空附接位点110可包含于经模制封装100的所述底侧上。图H展示在空附接位点110处添加装置113(例如，传感器)以生产最终封装。空附接位点110允许客户或其它第三方添加一或多个装置以制造总系统。
图2是包含三个经模制封装以增加产品功能的PoP组合件200的侧视图。为实现高组装成品率，每一封装201a到201c可在最终组装到PoP组合件200中之前被个别测试/特性化。在实施例中，封装201a到201c焊接在一起，从而允许重做或替换封装以改变产品功能。封装连接技术还可包含机械或导电粘合。
图3是根据实施例的具有集成RF屏蔽的实例引线框300的俯视图。引线框300包含经蚀刻部分301(例如，一半被蚀刻)及完整引线框厚度部分302。完整厚度部分302包含封装垫及附接位点304到306的侧。附接位点304到306也经蚀刻(例如，一半被蚀刻)以为IC裸片提供RF屏蔽。
图4A是根据实施例的具有集成RF屏蔽的另一实例引线框400的俯视图。引线框400类似于引线框300，除了附接位点304由天线位点402取代之外。天线位点402经蚀刻(例如，一半被蚀刻)以屏蔽冲压天线使其免受RF干扰。天线位点402电耦合到封装垫401。图4B是在天线位点402处具有冲压天线403的引线框400的俯视图。
图5A及5B分别是实例双面或多层层压衬底500的俯视图及侧视图。衬底500包含具有用于SMT组件的模板图案的附接位点501到503及封装垫504。图5B说明SMT组件的焊膏印刷沉积，其中焊膏505沉积于垫504上。在实施例中，焊膏505经沉积且接着在加热的烘箱中熔化以形成焊接接点。形成焊接接点的此方法改进生产时间、在成品的数量方面改进生产能力、增加可安装于PCB制造物上的组件密度，且帮助生产具有更小大小的产品。
图6A及6B分别是根据实施例的包含裸片附接线接合组件601、602的实例SMT组合件600的俯视图及侧视图。图6C及6D分别是附接到层压衬底600上的SMT组合件600、引线框焊料回流603的俯视图及侧视图。图6E是根据实施例的具有膜辅助包覆模制604的实例SMT组合件600的侧视图。图6F及6G分别是经翻转使得衬底的底侧(表面117b)变成准备好用于组件组装的顶侧PCB的经模制SMT组合件600的俯视图及侧视图。
图7是根据实施例的经配置以用于有效散热的封装组合件700的侧视图。高功率装置702的背侧可(例如，使用导电环氧树脂)直接附接到金属屏蔽件703上以用于有效散热。模具703中可包含用于模流的孔口701a到701c。
封装垫特征件116，当电连接到衬底100时，形成从衬底100到封装特征件116的顶表面的导电路径(图1F)，在这之后，模制件108通过模制暴露以允许电连接到PoP组合件中的另一封装。这形成具有顶侧接触件及底侧接触件两者的封装。“倒装”具有封装垫特征件116的暴露的顶表面的封装的经模制侧，且将其用于SMT组合件。相对的封装侧变成用于待附接的电子组件的封装的“顶”侧。封装垫特征件116还帮助形成允许组件(例如RF屏蔽件或天线)被集成到引线框101中的双面封装，从而导致更低制造成本。
实例过程
图8是根据实施例的制造双面电子封装的实例过程800的流程图。
在实施例中，过程800通过将封装垫框附接到双面层压衬底的第一侧(801)开始。过程800通过将一或多个组件附接到所述封装垫引线框并将所述组件电连接到所述封装垫(802)继续。过程800通过将膜辅助模制件施加到所述双面层压衬底的所述第一侧使得所述组件由模制材料覆盖(803)继续。过程800通过将所述双面层压衬底的第二侧配置成具有用于添加组件的一或多个空位点的PCB(804)继续。在所述一或多个空位点处添加一或多个额外组件(805)。过程800通过任选地测试完成的电子封装(806)继续。过程800通过任选地将所述完成的电子封装添加到PoP组合件(807)继续。
虽然此文档含有许多特定实施细节，但这些细节不应解释为对可主张的事物的范围的限制，而应解释为可特定于特定实施例的特征的描述。本说明书中在单独实施例的上下文中所描述的某些特征也可组合实施于单个实施例中。相反地，单个实施例的上下文中所描述的各种特征也可单独或以任何合适的子组合实施于多个实施例中。此外，尽管可上文将特征描述为以某些组合起作用，且甚至最初如此主张，但在一些情况中，可从所述组合删除来自所主张的组合的一或多个特征，且所主张的组合可涉及子组合或子组合的变型。

Claims (20)

1.一种电子封装，其包括：
衬底，其具有第一表面及第二表面；
引线框，其具有附接到所述衬底的所述第一表面的封装垫特征件；
第一集成电路裸片，其附接到所述引线框且电耦合到所述封装垫特征件中的至少一者；及
模制件，其在所述衬底的所述第一表面上安置于所述封装垫特征件之间，使得所述封装垫特征件从所述衬底的所述第一表面垂直延伸到所述电子封装的表面，所述封装垫特征件形成暴露于所述电子封装的所述表面上的导电路径。
2.根据权利要求1所述的电子封装，其包括：
第二集成电路裸片，其在附接位点处附接到所述第二表面。
3.根据权利要求1所述的电子封装，其中所述第一集成电路裸片附接到为所述第一集成电路裸片提供射频屏蔽的所述引线框的经蚀刻部分。
4.根据权利要求1所述的电子封装，其中冲压天线安置于所述引线框的经蚀刻部分上。
5.根据权利要求1所述的电子封装，其中所述第一集成电路裸片是表面安装技术SMT组件。
6.根据权利要求1所述的电子封装，其中所述电子封装包含用于模流的孔口。
7.根据权利要求1所述的电子封装，其中所述第一集成电路裸片倒装芯片使用焊接凸块安装到所述引线框。
8.一种方法，其包括：
将引线框附接到衬底的第一表面，所述引线框具有封装垫特征件；
将第一集成电路裸片附接到所述引线框，并将所述第一集成电路裸片电耦合到所述封装垫特征件中的至少一者；及
在所述第一表面上将模制件安置于所述封装垫特征件之间，使得所述封装垫特征件从所述衬底的所述第一表面垂直延伸到所述电子封装的表面，所述封装垫特征件形成到所述电子封装的所述表面的导电路径。
9.根据权利要求8所述的方法，其进一步包括：
将第二集成电路裸片附接到所述第二表面。
10.根据权利要求8所述的方法，其中附接所述第一集成电路裸片进一步包括：
蚀刻所述引线框的部分；及
将所述第一集成电路附接到所述经蚀刻部分。
11.根据权利要求8所述的方法，其进一步包括：
蚀刻所述引线框的部分；及
在所述引线框的所述经蚀刻部分上形成冲压天线。
12.根据权利要求8所述的方法，其进一步包括：
在所述电子封装中形成用于模流的孔口。
13.根据权利要求8所述的方法，其进一步包括：
使用焊接凸块将所述第一集成电路裸片焊接到所述第一表面。
14.一种封装堆叠PoP组合件，其包括：
第一封装；及
第二封装，其耦合到所述第一封装，所述第二封装包含：
衬底，其具有第一表面及第二表面；
引线框，其具有附接到所述衬底的所述第一表面的封装垫特征件；
第一集成电路裸片，其附接到所述引线框且电耦合到所述封装垫特征件中的至少一者；及
模制件，其在所述衬底的所述第一表面上安置于所述封装垫特征件之间，使得所述封装垫特征件从所述衬底的所述第一表面延伸到所述电子封装的表面，所述封装垫特征件形成暴露于所述电子封装的所述表面上的导电路径。
15.根据权利要求14所述的PoP组合件，其包括：
第二集成电路裸片，其在附接位点处附接到所述第二表面。
16.根据权利要求14所述的PoP组合件，其中所述第一集成电路裸片附接到为所述第一集成电路裸片提供射频屏蔽的所述引线框的经蚀刻部分。
17.根据权利要求14所述的PoP组合件，其中冲压天线安置于所述引线框的经蚀刻部分上。
18.根据权利要求14所述的PoP组合件，其中所述第一集成电路裸片是表面安装技术SMT组件。
19.根据权利要求14所述的PoP组合件，其中所述第一封装通过所述封装垫特征件电耦合到所述第二封装。
20.根据权利要求14所述的PoP组合件，其中所述第一封装焊接到所述第二封装。
CN201710312714.XA 2016-05-06 2017-05-05 双面电子封装 Pending CN107346764A (zh)

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