CN107340800B - CPLD with Delay Feedback circuit - Google Patents
CPLD with Delay Feedback circuit Download PDFInfo
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- CN107340800B CN107340800B CN201710452686.1A CN201710452686A CN107340800B CN 107340800 B CN107340800 B CN 107340800B CN 201710452686 A CN201710452686 A CN 201710452686A CN 107340800 B CN107340800 B CN 107340800B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The present invention relates to a kind of CPLD with Delay Feedback circuit.N variable delay, each logic unit and the Delay Feedback circuit that the CPLD includes DLL, connect with DLL；DLL generates 1 the first clock signal of tunnel and the road n phase delay coding；DLL is by the first clock signal transmission to each logic unit；Phase delay coding is corresponded with variable delay, and variable delay encodes according to corresponding phase delay received second clock signal carrying out phase shift, and dephased second clock signal is transmitted to each logic unit；Delay Feedback circuit is not distributed by the output terminal of clock of DLL via the Clock Tree of CPLD to be connect with the clock return terminal of DLL.The present invention can provide different clocks signal for CPLD logic unit, increase CPLD compensation of delay, clock adjustment, phase adjustment and multiple either synchronously or asynchronously clock out of phase shifting functions, the application that extension CPLD application field is read to digital information, simplify circuit design and the system integration, power consumption, exploitation and Material Cost are reduced, it is easy to use.
Description
Technical field
The invention belongs to IC design technical fields, and in particular to a kind of CPLD with Delay Feedback circuit.
Background technique
Programmed logic device refers to that all can be configured by software approach, change device inner connecting structure and logic list
Member completes the digital integrated electronic circuit of given design function.Common programmable logic device mainly has simple logic array
(PAL/GAL), 3 major class such as Complex Programmable Logic Devices (CPLD) and Field Programmable Logic Array (FPGA).
Referring to Figure 1, the structure of CPLD is mainly the programmable interconnection matrix that center is surrounded by programmable logic unit
Unit (" routing pool, wiring matrix " i.e. in figure) composition.Wherein, the logic unit has multiple logic macrocell (Macro
Cell), logic macrocell structure is more complex, and has complicated I/O cell interconnection structure, can generate as needed spy by user
Fixed circuit structure completes certain function.Since the metal wire inside CPLD using regular length carries out each logic unit
Interconnection avoids what segmented interconnection structure timing was not exclusively predicted so the logic circuit of design has time predictability
Disadvantage.
Conventionally, as the Clock management that CPLD is provided is too simple, it is necessary to there is the phaselocked loop (PLL) of collocation to mention
For removing clock skew, clock delay is adjusted, frequency synthesis etc. is carried out, can refer to Fig. 2, system clock distribution can be regulated and controled by PLL.But
It is since there are the accumulation of unstability and phase offset for the voltage-controlled oscillator (VCO) (VCO) used in PLL, thus in compensating clock point
When time delay caused by cloth network, the performance of PLL can be reduced, and clock caused by PLL completes phase shift, frequency
Frequency multiplication, frequency frequency dividing etc. is after functions, and still synchronous with input clock, PLL can not handle the phase shifting function of asynchronous clock.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of with Delay Feedback circuit
CPLD.The technical problem to be solved by the present invention is how to overcome clock when integrating PLL in CPLD unstable and phase offset product
Tired problem.And provide the phase shifting function in the asynchronous clock source of multiple identical frequencies.
An embodiment provides a kind of CPLD with Delay Feedback circuit, including delay phase-locked loop, with
N variable delay, each logic unit and the Delay Feedback circuit of the delay phase-locked loop connection, the n are not less than 1
Integer；Wherein,
The delay phase-locked loop generates 1 the first clock signal of tunnel and the road n phase delay coding；Wherein, the delay locking phase
Ring is by first clock signal transmission to each logic unit；The phase delay coding and the variable delay one
One is corresponding, and the variable delay encodes according to corresponding phase delay received second clock signal carrying out phase shift, and
Dephased second clock signal is transmitted to each logic unit；
The Delay Feedback circuit is by the output terminal of clock of the delay phase-locked loop not via the Clock Tree of the CPLD point
Cloth is connect with the clock return terminal of the delay phase-locked loop.
In one embodiment of the invention, the delay phase-locked loop is by first clock signal by the delay locking phase
Variable delay inside ring is postponed, and by the delay coding transmission after delay to each logic unit.
In one embodiment of the invention, the CPLD be equipped with n output terminal of clock, the n output terminal of clock and
The n variable delay connects one to one, when the output terminal of clock is connected to each logic unit and outside
Clock output end.
In one embodiment of the invention, the CPLD further include: n+1 Selecting phasing branch, the delay locking phase
For exporting between the output end of first clock signal and each logic unit and external clock output end on ring
It is connected by 1 Selecting phasing branch, each variable delay is exported with each logic unit and corresponding external clock
Pass through 1 Selecting phasing branch connection in remaining Selecting phasing branch between end.
In one embodiment of the invention, every Selecting phasing branch includes: third data selector and buffer.
In one embodiment of the invention, every Selecting phasing branch include: third data selector, buffer and
Alternative phase selector.
In one embodiment of the invention, the CPLD further include: the first data selector；The first data selection
The output end of device is connect with the clock return terminal of the delay phase-locked loop, 1 input terminal of first data selector and institute
It states and is connected on delay phase-locked loop for exporting the output end of first clock signal, another 1 of first data selector
Input terminal is connect with the output terminal of clock of the delay phase-locked loop.
In one embodiment of the invention, the CPLD further include: m external clock input terminal and the selection of the second data
Device, 1 external clock input terminal is connect with 1 input terminal of second data selector, in remaining external clock input terminal
N connect one to one with the n variable delay, the output end of second data selector and the delay locking phase
The input end of clock of ring connects, and m is the integer not less than n+1.
In one embodiment of the invention, the CPLD is equipped with external clock return terminal, the external clock return terminal
It is connect with 1 input terminal in the first data selector residue input terminal.
The embodiment of the present invention, the present invention can overcome in CPLD and integrate by the way that delay phase-locked loop DLL to be integrated in CPLD
Unstable and phase offset when PLL accumulates problem, and different clock signals is provided for the logic unit in CPLD, increases CPLD
Add compensation of delay, clock adjustment, phase adjustment, and the phase shift function that the asynchronous clock signal source for providing multiple identical frequencies is different
Can, expand the application that the application field of CPLD is read to digital information, simplify circuit design and the system integration, reduces power consumption, opens
Cost and Material Cost are sent out, it is easy to use.
Detailed description of the invention
Fig. 1 is the internal logic block diagram of CPLD in the prior art；
Fig. 2 is the clock distribution circuit schematic diagram of CPLD collocation phase-locked loop pll in the prior art；
Fig. 3 is the circuit diagram of DLL in the prior art；
Fig. 4 is a kind of circuit diagram of CPLD provided in an embodiment of the present invention；
Fig. 5 is the circuit diagram of the variable delay integrated in CPLD shown in Fig. 4 and a kind of relationship of DLL；
Fig. 6 is the circuit diagram of the variable delay integrated in CPLD shown in Fig. 4 and another relationship of DLL；
Fig. 7 is the circuit diagram of the DLL integrated in CPLD shown in Fig. 4.
Specific embodiment
Further detailed description is done to the present invention combined with specific embodiments below, but embodiments of the present invention are not limited to
This.
Below to illustrate the present invention by taking the delay locked loop generates 4 tunnel clock signals (i.e. n=3) as an example, but do not limit
Protection scope of the present invention.Refer to Fig. 3 to Fig. 7, the Complex Programmable Logic Devices has been internally integrated: delay phase-locked loop and
N variable delay connecting with the delay phase-locked loop, the n are the integer not less than 1；
The delay phase-locked loop generates 1 the first clock signal of tunnel and the road n phase delay coding, the phase delay coding with
The variable delay corresponds, and the variable delay is encoded according to corresponding phase delay believes received second clock
It number carries out phase shift, and each is patrolled what dephased second clock signal was transmitted in the Complex Programmable Logic Devices
Collect unit.
In a particular application, the delay phase-locked loop usually can be by first clock signal by the delay phase-locked loop
The variable delay in portion is postponed, and the delay coding transmission after delay is each into the Complex Programmable Logic Devices
A logic unit refers to Fig. 5, the Complex Programmable Logic Devices further include: by the clock output of the delay phase-locked loop
End is not distributed the Delay Feedback circuit connecting with the clock return terminal of the delay phase-locked loop via the Clock Tree of CPLD；
In this case, the clock source of the Complex Programmable Logic Devices is provided by external clock input terminal, is
Convenient for providing multiple clock signals that out of phase is moved to external circuit, it is preferable that the Complex Programmable Logic Devices is equipped with n
A output terminal of clock (in present embodiment, which is realized using the I/O unit in Complex Programmable Logic Devices),
The n output terminal of clock connects one to one with the n variable delay, and the output terminal of clock is connected to the complexity
Each logic unit and external clock output end in programmable logic device.
It will be appreciated that in the Complex Programmable Logic Devices of the present embodiment shown in fig. 5 integrate variable delay with
The principle of the circuit diagram of the relationship of delay phase-locked loop DLL specifically:
The usage mode of DLL is DLL home loop, and Uo and Ui (clock 0) are matched, not via the distribution of Clock Tree, immediately
Clock 0 generates delay coding, clock 1 via DLL, and clock 2 waits receiving ends clock or read clock using variable delay and delay
Coding, generates phase shift appropriate, to read the digital signal of receiving end.Three internal clockings of this configuration mode are all inputs
The phase shift of clock can support the reception of the digital information of 3 communication channels simultaneously；
In another concrete application, the delay phase-locked loop can compile first clock signal transmission to the complexity
Each logic unit in journey logical device, refers to Fig. 6, and the delay phase-locked loop is prolonged first clock signal by described
Variable delay inside slow phaselocked loop carries out Delay Feedback circuit via the Clock Tree of CPLD, the first clock after being postponed
Signal, and each logic unit by the first clock signal transmission after the delay into the Complex Programmable Logic Devices
(i.e. the phase shift output of clock 0 is also pushed to Clock Tree, is distributed to logic macrocell)；
In this case, the clock source of the Complex Programmable Logic Devices is provided by external clock input terminal, is
Convenient for providing multiple clock signals that out of phase is moved to external circuit, it is preferable that the Complex Programmable Logic Devices is equipped with n
(in present embodiment, the output terminal of clock is using the I/O unit in Complex Programmable Logic Devices for+1 external clock output end
Realize), 1 external clock output end connects on the delay phase-locked loop for exporting the output end of first clock signal
It connects, remaining n external clock output end connects one to one with the n variable delay.
It will be appreciated that in the Complex Programmable Logic Devices of the present embodiment shown in fig. 5 integrate variable delay with
The principle of the circuit diagram of the relationship of delay phase-locked loop DLL specifically:
DLL generates the coding of variable delay via the circuit of Ui, Ud, Uc, Uo, while generating first clock output Uo
And it is exported by output end C0；Due to the function of DLL, Uo+ clock tree delays and Ui exact matching (Fig. 4)；It is variable inside DLL
Delayer replicates 3 times in CPLD, is supplied to the other 3 clocks input of CPLD；DLL exports multiple delay codings, packet simultaneously
It includes but is not limited to 90 degree, 180 degree, 270 degree of phase delay encode and pass through output end C1, C2, C3 and export to corresponding and variable prolong
When device.The present embodiment can produce the clock of clock 1, clock 2 or the phase shift corresponding with Ui of clock 3, for macro in CPLD
Unit uses.In application, clock 1, clock 2 and clock 3 can be the reading restored from 3 different communication channels
Clock.Since clock 1, clock 2, clock 3 are from different routing restorations, and Ui is asynchronous clock.Corresponding PLL's
Using mono- clock source of PLL generates multiple clocks, cannot handle the application in multiple asynchronous clock sources.
In a particular application, certain interference signal can be generated by external return terminal due to clock feedback circuit, asked
Referring to Fig. 7, in order to prevent external interference signal as far as possible, it is preferable that for exporting described first on the delay phase-locked loop
The clock return terminal (Clock feedback, abbreviation CF) of the output end of clock signal and the delay phase-locked loop connects, by institute
The clock return terminal CF of the first clock signal transmission caused by DLL to the DLL is stated, and is returned by the clock of the DLL
Signal received by the CF of end carries out anti-regulation delay, shake and inclination to clock signal and handles, and can reach almost glitch-free
State；
For the ease of by the clock return terminal CF for being transmitted to the DLL of the clock signal of the generation of DLL selectivity, preferably
Ground, the Complex Programmable Logic Devices further include: the first data selector, the output end of the first data selector D1 with
The clock return terminal CF connection of the delay phase-locked loop, 1 input terminal of the first data selector D1 and the delay are locked
For exporting the output end connection of first clock signal on phase ring.
In a particular application, it is inputted to be easy to implement multiple external clocks, it is preferable that the Complex Programmable Logic Devices
Further include: m external clock input terminal and the second data selector D2,1 external clock input terminal and second data are selected
1 input terminal connection of device D2 is selected, n in remaining external clock input terminal correspond company with the n variable delay
It connects, the output end of the second data selector D2 and input end of clock (Clock input, the abbreviation of the delay phase-locked loop
CI it) connects, m is the integer not less than n+1.
For convenient for the DLL to be connect with external clock reference, and guarantee the performance for being supplied to the clock signal of external circuit,
Regulation delay, shake and inclination are prevented as far as possible, it is preferable that the Complex Programmable Logic Devices is returned equipped with external clock
End, the external clock return terminal are connect with 1 input terminal in the first data selector D1 residue input terminal.
For the Selecting phasing convenient for carrying out 0 degree or 180 degree to DLL clock signal generated, it is preferable that described multiple
Miscellaneous programmable logic device further include: n+1 Selecting phasing branch, for exporting first clock on the delay phase-locked loop
Lead between each logic unit and external clock output end in the output end of signal and the Complex Programmable Logic Devices
Cross the connection of 1 Selecting phasing branch, each variable delay and each logic in the corresponding Complex Programmable Logic Devices
Pass through 1 Selecting phasing branch connection in remaining Selecting phasing branch between unit and external clock output end.
It should be noted that 1 Selecting phasing branch in the present embodiment can only be by 1 variable delay and the Variable delay
Each logic unit and external clock output end in the corresponding Complex Programmable Logic Devices of device link together.It lifts
For example, referring to Fig. 4, the Complex Programmable Logic Devices includes 4 Selecting phasing branches (Selecting phasing branch 1, phase choosing
Select branch 2, Selecting phasing branch 3 and Selecting phasing branch 4) and 3 variable delays (variable delays 1, variable delay 2
With variable delay 3), it can be selected by phase for exporting the output end C0 of first clock signal on the delay phase-locked loop
The connection of branch 1 is selected, variable delay 1 is connected by Selecting phasing branch 2, and variable delay 2 is connected by Selecting phasing branch 3
It connects, variable delay 3 is connected by Selecting phasing branch 4.
In a particular application, to be easy to implement Selecting phasing, it is preferable that every Selecting phasing branch includes: third number
According to selector and buffer；Alternatively, every Selecting phasing branch includes: third data selector, buffer and alternative phase
Digit selector.
For example, referring again to Fig. 4, for the Selecting phasing branch 1 in scheme, every Selecting phasing branch is wrapped
It includes: third data selector (the third data selector of Selecting phasing branch 1 is " D31 " in figure), alternative Selecting phasing
Device (the alternative phase selector of Selecting phasing branch 1 is " X1 " in figure, carries out the alternative of 0 degree or 180 degree) and buffering
Device (buffer of Selecting phasing branch 1 includes: " H1 ", " H2 ", " H3 ", " H4 " and " H5 " in figure), every Selecting phasing branch
Lu Kexian is combined by third data selector and alternative phase selector, then connect with buffer composition (i.e. in figure phase
Select branch 1 that can first be combined by third data selector D31 and alternative phase selector X1, then with buffer H1, H2, H3,
H4 connects composition with H5).
In the practical application of prior art CPLD, general design of electronic circuits usually use PLL as system when
Clock management.A stable base frequency clock is generated using a crystal oscillator component on electronic circuit board.Based on this stabilization
Base frequency use PLL frequency multiplication and frequency splitting technology, generate different any clock frequencies.Therefore the application of PLL is extremely
Extensively, it popularizes, often arranges in pairs or groups and use with CPLD；
And DLL is usually applied to restore the digital signal of media medium.In terms of communication, digital signal is via communication channel
Remotely transmitted.Communication channel is typically at complicated, uncontrollable environment, such as radio microware communication via earth table
The atmosphere in face, there is Changes in weather, the uncontrollable factors such as terrain differences.Receiving end digital signal due to communication channel
It is variable, uncontrollable factor, along with interfering with each other for signal, received digital signal usually has frequency shift (FS), and phase is inclined
It moves, the problem of the clock domain shaken etc..It can restore the clock being embedded in digital signal using the technology of DLL, and produce
Raw, out of phase synchronous with signal source, the clock of frequency multiplication frequency dividing.Therefore DLL is commonly used in the receiving end of communication channel.In consumption electricity
Subdomains, DLL is also commonly used to read the information from digital signal storage media, for example reads information from optical disc.It is read in optical disc
It takes in environment there is also the jitter read, deviates, the factors such as shake need the technology using DLL.
General electronic circuit technology personnel (can make commonly using PLL in the generation end of information or the transmission end of information
With PLL), but DLL is not known about usually.Related technical staff (usually communication industry or consumption electricity are read with media medium
The portion of techniques personnel of sub- industry) it will use DLL (in the reading end of information or the receiving end of information, using DLL).
It is the application scenarios in the prior art of DLL and PLL, inherently different using opportunity, and DLL core
Piece area is small, at low cost, low in energy consumption, that completes function identical with PLL, but does not have the problem of accumulated phase is moved, specific
Using, the application of DLL suitable multi-clock similar and different phase shift more advantageous than PLL, PLL is suitable by a Base clock source production
The application of raw multiple and different clock frequency.
The Complex Programmable Logic Devices of the reinforcing asynchronous clock management of the present embodiment, can overcome and integrate PLL in CPLD
When it is unstable problem is accumulated with phase offset, different clock signals is provided for the logic unit in CPLD, increases CPLD
Compensation of delay, clock adjustment, the phase adjustment phase shifting function different with multiple clocks expand the application field of CPLD to digital
The application that information is read simplifies circuit design and the system integration, reduces power consumption, development cost and Material Cost, easy to use.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (9)
1. a kind of CPLD with Delay Feedback circuit, which is characterized in that including delay phase-locked loop and with the delay phase-locked loop
N variable delay of connection and each logic unit and Delay Feedback circuit, the n are the integer not less than 1；Wherein,
The delay phase-locked loop generates 1 the first clock signal of tunnel and the road n phase delay coding；Wherein, the delay phase-locked loop will
First clock signal transmission is to each logic unit；The phase delay coding and the variable delay one are a pair of
It answers, the variable delay encodes according to corresponding phase delay received second clock signal carrying out phase shift, and by phase
Second clock signal after displacement is transmitted to each logic unit；
The Delay Feedback circuit by the delay phase-locked loop output terminal of clock not via the CPLD Clock Tree distribution with
The clock return terminal of the delay phase-locked loop connects.
2. CPLD according to claim 1, which is characterized in that the delay phase-locked loop is by first clock signal by institute
It states the variable delay inside delay phase-locked loop to be postponed, and by the delay coding transmission after delay to each logic list
Member.
3. CPLD according to claim 1, which is characterized in that the CPLD is equipped with n output terminal of clock, at described n
Clock output end connects one to one with the n variable delay, and the output terminal of clock is connected to each logic unit
And external clock output end.
4. CPLD according to claim 3, which is characterized in that the CPLD further include: n+1 Selecting phasing branch, institute
It states on delay phase-locked loop for exporting the output end and each logic unit and external clock of first clock signal
By the connection of 1 Selecting phasing branch between output end, each variable delay and each logic unit and it is corresponding outside
Pass through 1 Selecting phasing branch connection in remaining Selecting phasing branch between portion's output terminal of clock.
5. CPLD according to claim 4, which is characterized in that every Selecting phasing branch includes: the selection of third data
Device and buffer.
6. CPLD according to claim 4, which is characterized in that every Selecting phasing branch includes: the selection of third data
Device, buffer and alternative phase selector.
7. CPLD according to claim 1, which is characterized in that further include: the first data selector；The first data choosing
The output end for selecting device is connect with the clock return terminal of the delay phase-locked loop, 1 input terminal of first data selector with
It is connected on the delay phase-locked loop for exporting the output end of first clock signal, another the 1 of first data selector
A input terminal is connect with the output terminal of clock of the delay phase-locked loop.
8. CPLD according to claim 7, which is characterized in that further include: m external clock input terminal and the choosing of the second data
Device is selected, 1 external clock input terminal is connect with 1 input terminal of second data selector, remaining external clock input terminal
In n connect one to one with the n variable delay, the output end of second data selector and delay lock
The input end of clock of phase ring connects, and m is the integer not less than n+1.
9. CPLD according to claim 7, which is characterized in that the CPLD is equipped with external clock return terminal, the outside
Clock return terminal is connect with 1 input terminal in the first data selector residue input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710452686.1A CN107340800B (en) | 2015-01-23 | 2015-01-23 | CPLD with Delay Feedback circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710452686.1A CN107340800B (en) | 2015-01-23 | 2015-01-23 | CPLD with Delay Feedback circuit |
| CN201510035684.3A CN104615192B (en) | 2015-01-23 | 2015-01-23 | A kind of CPLD for strengthening asynchronous clock management |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510035684.3A Division CN104615192B (en) | 2015-01-23 | 2015-01-23 | A kind of CPLD for strengthening asynchronous clock management |
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| Publication Number | Publication Date |
|---|---|
| CN107340800A CN107340800A (en) | 2017-11-10 |
| CN107340800B true CN107340800B (en) | 2019-06-14 |
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| CN201710452686.1A Active CN107340800B (en) | 2015-01-23 | 2015-01-23 | CPLD with Delay Feedback circuit |
| CN201510035684.3A Active CN104615192B (en) | 2015-01-23 | 2015-01-23 | A kind of CPLD for strengthening asynchronous clock management |
| CN201710452695.0A Active CN107342764B (en) | 2015-01-23 | 2015-01-23 | Complex programmable logic device |
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| CN107844672B (en) * | 2017-12-06 | 2023-11-28 | 西安智多晶微电子有限公司 | Clock tree unit, clock network structure and FPGA clock structure |
| CN111835345B (en) * | 2020-07-30 | 2024-07-12 | 云知声智能科技股份有限公司 | DLL control circuit and control method |
| CN113325918B (en) * | 2021-06-15 | 2022-09-27 | 展讯通信（上海）有限公司 | Clock management circuit, chip and electronic equipment |
| CN114253346A (en) * | 2021-12-09 | 2022-03-29 | 杭州长川科技股份有限公司 | Timing signal generator and calibration system and method thereof |
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| CN1801625A (en) * | 2004-11-08 | 2006-07-12 | 三星电子株式会社 | Delay locked loop and semiconductor memory device having the same |
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| CN103677077A (en) * | 2013-12-18 | 2014-03-26 | 西安智多晶微电子有限公司 | Complex programmable logic device (CPLD) for strengthening clock management |
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| EP1214788B1 (en) * | 1999-09-22 | 2003-03-26 | Siemens Aktiengesellschaft | Integrated circuit comprising at least two clock systems |
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| JP4745127B2 (en) * | 2006-05-23 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | Clock switching circuit |
| CN101504861A (en) * | 2009-03-16 | 2009-08-12 | 东南大学 | Full digital time-delay locking loop circuit |
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| US7109765B1 (en) * | 1998-11-03 | 2006-09-19 | Altera Corporation | Programmable phase shift circuitry |
| CN1801625A (en) * | 2004-11-08 | 2006-07-12 | 三星电子株式会社 | Delay locked loop and semiconductor memory device having the same |
| CN102882516A (en) * | 2011-07-13 | 2013-01-16 | 南亚科技股份有限公司 | Method for resetting dll with frequency change application |
| CN102624383A (en) * | 2012-04-06 | 2012-08-01 | 南通金枫电气有限公司 | Digital phase-locked phase-shift trigger circuit |
| CN103677077A (en) * | 2013-12-18 | 2014-03-26 | 西安智多晶微电子有限公司 | Complex programmable logic device (CPLD) for strengthening clock management |
Also Published As
| Publication number | Publication date |
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| CN107342764A (en) | 2017-11-10 |
| CN107340800A (en) | 2017-11-10 |
| CN107342764B (en) | 2020-06-12 |
| CN104615192A (en) | 2015-05-13 |
| CN104615192B (en) | 2017-08-11 |
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Denomination of invention: CPLD with delay feedback loop Effective date of registration: 20201221 Granted publication date: 20190614 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2020610000239 |
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