CN107305910A - Super junction semiconductor subassembly - Google Patents
Super junction semiconductor subassembly Download PDFInfo
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- CN107305910A CN107305910A CN201610250234.0A CN201610250234A CN107305910A CN 107305910 A CN107305910 A CN 107305910A CN 201610250234 A CN201610250234 A CN 201610250234A CN 107305910 A CN107305910 A CN 107305910A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 230000000295 complement effect Effects 0.000 claims description 31
- 238000007789 sealing Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000003068 static effect Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 description 14
- 239000012535 impurity Substances 0.000 description 14
- 230000015556 catabolic process Effects 0.000 description 13
- 239000011159 matrix material Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of super junction semiconductor subassembly, it includes substrate, the drift layer being arranged on substrate, lightly doped district, insulating barrier and main loop field plate.Drift layer has multiple n-type doped regions and multiple p-type doped regions, and multiple n-type doped regions are alternately arranged to form super contact structure with multiple p-type doped regions.Drift layer defines a component area and the termination environment around component area.Lightly doped district be located at drift layer inside and connection surface, and lightly doped district have one close to component area first end portion and a second end portion away from component area.Insulating barrier is arranged on surface, and at least covers termination environment.Main loop field plate is arranged on insulating barrier, wherein main loop field plate covering second end portion.
Description
Technical field
The present invention relates to a kind of semiconductor subassembly, and more particularly to a kind of golden oxygen with super contact structure half
Field-effect transistor (MOSFET, full name is " Metal-Oxide Semiconductor field-effect transistor ") component.
Background technology
In super junction (super-junction) transistor component, the increase of conducting resistance (Rds-on) with
The increase of breakdown voltage (BV) is directly proportional, and increases slower than traditional semiconductor structure.Therefore,
Super junction transistor component can maintain very high off state (off state) breakdown voltage (breakdown
Voltage, BV) while, with low conducting resistance (R ds-on).
Super junction transistor component would generally have active region and the terminator around active region.When
Super junction component is in off state, and vertical direction and horizontal direction in terminator all have electric field point
Cloth.
In conventional super junction transistor component, the plan view shape of the p-type doped region in termination environment is ring
Shape.However, when forming p-type doped region by epitaxial growth process, on the corner needing to form special
Lattice plane, can just make p-type doped region on the corner have preferably lattice arrangement.In this way, being made improving
Journey difficulty.In addition, impurity doping concentration on the corner is less easy to control, it is also possible to therefore and reduce
Super junction transistor component is in the pressure-resistant of terminator.
The content of the invention
The present invention provides a kind of super junction semiconductor subassembly, multiple p-types doping of super junction semiconductor subassembly
Area is tossed about by the two-phase in component area towards component area and extended in termination environment, and coordinates the design of annular field plate,
Breakdown voltage of the super junction semiconductor subassembly at off state (OFF-state) can be made to meet the requirements.
A wherein embodiment of the invention provides a kind of super junction semiconductor subassembly, it include substrate, drift layer,
Lightly doped district, insulating barrier and main loop field plate.Drift layer is arranged on substrate, and with contrast to base
Multiple n-type doped regions and multiple p-type doped regions are formed in one surface of plate, wherein drift layer, and it is multiple
N-type doped region is extended with multiple p-type doped regions by surface towards the direction of substrate, and is alternately arranged, with
Formation one surpasses contact structure.Drift layer define a component area and one surround component area termination environment.It is lightly doped
Area be located at drift layer inside and connection surface, and lightly doped district have one close to component area first end portion
And the second end portion away from component area.Insulating barrier, which is arranged on surface, covers termination environment.Main loop
Plate is arranged on insulating barrier, main loop field plate is covered second end portion.
In summary, super junction semiconductor subassembly provided by the present invention, by covering main loop field plate
The second end portion of lightly doped district, it is possible to decrease the electric-field intensity in second end portion, so as to improve super junction
The overall breakdown voltage of semiconductor subassembly.In addition, in the super junction semiconductor subassembly of the embodiment of the present invention,
Multiple p-type doped regions are to be tossed about to extend in termination environment by the two-phase in component area towards component area.Compared to habit
For the super junction transistor component known, when forming these p-type doped regions using epitaxial growth process, due to p
Type doped region does not have corner, thus can improve epitaxy uniformity, and reduces process complexity.
For the above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and
Coordinate accompanying drawing, be described in detail below.
Brief description of the drawings
Fig. 1 is the schematic top plan view of the super junction semiconductor subassembly of one embodiment of the invention.
Fig. 2 be Fig. 1 in along II-II diagrammatic cross-section.
Fig. 3 A are the schematic top plan view of the super junction semiconductor subassembly of another embodiment of the present invention.
Fig. 3 B are the enlarged drawing in Fig. 3 A in region A.
Fig. 4 be Fig. 3 A in along IV-IV diagrammatic cross-section.
Fig. 5 is the local overlooking schematic diagram of the super junction semiconductor subassembly of another embodiment of the present invention.
Fig. 6 is the schematic top plan view of the super junction semiconductor subassembly of another embodiment of the present invention.
Reference：
Super junction semiconductor subassembly 1,1 ', 3；Substrate 10；Upper surface 10a；Back side 10b；
Drift layer 11；Surface 11a；Insulating barrier 12；Main loop field plate 13,13 ', 23；
First straight line section 13a, 13 ' a, 23a；Second straight line section 13b, 13 ' b, 23b；
Turning point 13c, 13 ' c, 23c；First end face 131,131'；Second end face 132,132'；
Length L, L1；Transistor arrangement 15；Component area A1；Termination environment A2；
N-type doped region 112,113；Second width W2；P-type doped region 110,111；
End 110a, 111a；First width W1；Lightly doped district 114；First end portion 114a；
Second end portion 114b；First direction D1；Second direction D2；Contact hole h1；
Matrix area 150；Source area 151；Gate insulation layer 152；Gate 153；Dielectric layer 154；
Source layer 155；End face 155e；Predetermined distance d；Sealing ring 16,26,36；
Means of complementary annular field plate 14,24,34a, 34b；First straight line portion 14a, 24a；
Second straight line portion 14b, 24b；Return portion 14c, 24c；Width w
Embodiment
Illustrated referring to Fig. 1 with Fig. 2, wherein Fig. 1 partly leads for the super junction of the embodiment of the present invention
The schematic top plan view of body component, and Fig. 2 be Fig. 1 in along II-II diagrammatic cross-section.
The super junction semiconductor subassembly 1 of the embodiment of the present invention includes substrate 10, drift layer 11, is lightly doped
Area 114, insulating barrier 12, main loop field plate 13 and an at least transistor arrangement 15.
In fig. 2, substrate 10 be semiconductor substrate, and with a upper surface 10a and with upper surface 10a
One back side 10b of opposite opposite side.Substrate 10 has the first conductive-type impurity of high concentration.First is conductive
Type impurity can be distributed in the regional area of substrate 100 or be distributed in whole substrate 10, for making
For drain contact layer.It is distributed across in first conductive-type impurity of the present embodiment in whole substrate 10, but
It is only used for illustrating and is not used to the limitation present invention.Drain contact pad (not shown) can be formed at the back of the body of substrate 10
Face 10b, for being electrically connected at the control circuit of outside.
The first foregoing conductive-type impurity can be N-type or P-type conductivity impurity.Assuming that substrate 10 is
Silicon substrate, N-type conductivity impurity is pentad ion, such as phosphonium ion or arsenic ion, and p-type is led
Electrical impurity is triad ion, such as boron ion, aluminium ion or gallium ion.
Drift layer (drift layer) 11 is located on the upper surface 10a of substrate 10, and first with low concentration
Type conductive impurities.In the present embodiment, substrate 10 is the n-type doping (N+) of high concentration, and drifts about
Layer 11 is then the n-type doping (N-) of low concentration.The side of drift layer 11 and the upper surface 10a of substrate 10
Connection, and the surface 11a with contrast to the opposite side of substrate 10.
As shown in Figures 1 and 2, in the present embodiment, drift layer 11 be defined out a component area A1 with
And one surround component area A1 termination environment (termination area) A2.As shown in figure 1, component area A1
It is the middle section positioned at super junction semiconductor subassembly 1, termination environment A2 is then around component area A1 and position
In the neighboring area of super junction semiconductor subassembly 1.
Refer to has multiple n-type doped regions 112,113 and multiple p-types in Fig. 2, drift layer 11
Doped region 110,111.These n-type doped regions 112,113 and p-type doped region 110,111 replace
Formula it is arranged side by side, to form super contact structure.In addition, these n-type doped regions 112,113 and p-type
Doped region 110,111 extends along current flowing direction, that is, by the surface 11a courts of drift layer 11
The direction extension of substrate 10.
Fig. 1 is refer to, in the present embodiment, a portion p-type doped region 110 can be by component area A1
Nei Chao components area A1 both sides are extended out in the A2 of termination environment.That is, each p-type is mixed
The center section in miscellaneous area 110 is located in component area A1, and fore-end is then located at rear end part
In the A2 of termination environment.
In addition, in the embodiment of fig. 2, these p-type doped regions 110,111 are to be in the form of a column (pylon),
And n-type doped region 112,113 be respectively staggeredly and around these columns p-type doped region 110,111.
Furthermore, it is that multiple grooves arranged side by side are first formed in drift layer 11, p-type epitaxy is inserted afterwards
Material is in these grooves, to form these p-type doped regions 110,111.
When super junction semiconductor subassembly 1 is in opening (On state), these n-type doped regions 112,
113 and p-type doped region 110,111 electric charge can be provided, and when super junction semiconductor subassembly 1 is in pass
Disconnected state (Off state), understands these n-type doped regions 112,113 and p-type doped region 110,111 meetings
In the horizontal direction by vague and general (or exhausting, depletion), to reach charge balance in drift layer 11.Cause
This, super junction semiconductor subassembly 1 can be under relatively low conducting resistance, with higher breakdown voltage.
If the impurity doping concentration in p-type doped region 110,111 is uneven, it be able to not can most probably consume
Electric charge to the greatest extent in drift layer 11, and cause the breakdown voltage of super junction semiconductor subassembly 1 to reduce.Therefore,
In embodiments of the present invention, p-type doped region 110,111, which is all parallel to each other, is listed in drift layer 11,
And each p-type doped region 110,111 does not have turn section.Forming p-type doped region 110,111
When, it can make p-type doped region 110,111 that there is more uniform impurity doping concentration, so as to avoid surpassing
Junction semiconductor subassembly 1 it is pressure-resistant because n-type impurity doping concentration is uneven and reduces.
It is listed in because p-type doped region 110,111 is all parallel to each other in drift layer 11, and each p-type
Doped region 110,111 does not have turn section.Therefore, inserting p-type epitaxy material to form these p
During type doped region 110,111, it is not necessary to the problem of whether lattice plane matches considered, it is possible to decrease processing procedure is difficult
The epitaxy quality of degree and lifting p-type doped region 110,111.
In embodiments of the present invention, each p-type doped region 110,111 has one first width W1
And first concentration be p1, there is each n-type doped region one second width W2 and its concentration to be n1.
Furthermore, a preset distance is spaced apart between two adjacent p-type doped regions 110,111, and
Foregoing preset distance is the second width W2 of n-type doped region 112,113.In one embodiment,
Between one width W1, the second width W2, the first concentration p1 and the second concentration n1, meet following relationship
Formula：p1*W1≒n1*W2.
It should be noted that, termination environment A2 area can also influence the collapse electricity of super junction semiconductor subassembly 1
Pressure.Usual breakdown voltage can increase and increase with termination environment A2 area.In the implementation shown in Fig. 2
In example, at least there is six groups of p-type doped regions 111 and n-type doped region 113, to prolong in the A2 of termination environment
The distribution of electric field is stretched, so as to lift the overall breakdown voltage of super junction semiconductor subassembly 1.
Fig. 2 is refer to, in the present embodiment, drift layer 11 is in the A2 of termination environment with more a neighbouring drift
Move layer 11 surface 11a lightly doped district 114, and lightly doped district 114 be connected to p-type doped region 111 with
Between 11 surfaces.Furthermore, lightly doped district 114 is to be located at p-type doped region 111 close to drift layer
11 surface 11a side, and it is connected to surface 11a.In addition, conductivity type and the drift of lightly doped district 114
The conductivity type for moving layer 11 is opposite.In the present embodiment, lightly doped district 114 extends to end by component area A1
Petiolarea A2, and the first end portion 114a with one in component area A1, and positioned at termination environment
A2 second end portion 114b.
Insulating barrier 12 is arranged at covering termination environment A2 on the surface 11a of drift layer 11.In an embodiment
In, insulating barrier 12 is oxide layer or nitration case.Fig. 1 and Fig. 2 are refer to, main loop field plate 13 is surround
Ground is arranged on insulating barrier 12, with the internal electric field scope of drift layer 11 that extends, and improves super junction semiconductor group
Part 1 is pressure-resistant termination environment A2's.As shown in figure 1, main loop field plate 13 is to be located at super junction semiconductor
The peripheral region of component 1, and around the middle section of super junction semiconductor subassembly 1.
Fig. 2 is refer to, in embodiments of the present invention, the of the covering lightly doped district 114 of main loop field plate 13
Two terminal part 114b, and make second end portion 114b positioned at the lower section of main loop field plate 13.Specifically,
Main loop field plate 13 has close to a component area A1 first end face 131 and away from component area A1
One second end face 132, wherein first end face 131 and second end face 132 not homonymy relatively.In this implementation
In example, the position of main loop field plate 13 can at least partly overlap with lightly doped district 114, and main loop
Plate 13 is beyond the length L of second end portion 114b mono-, the i.e. second end face 132 of main loop field plate 13 and gently
The distance between second end portion 114b of doped region 114.
It should be noted that, through emulation testing, as a result show the position of the setting of main loop field plate 13 and prolong
The length L beyond second end portion 114b is stretched, the breakdown voltage of super junction semiconductor subassembly 1 can be all influenceed.
In the present embodiment, main loop field plate 13 extends beyond second end portion 114b part and at least covers two
The individual n-type doped region of p-type doped region 111 and one.That is, length L, the first width W1 and
Second width W2 meets following relationship：a*(W1+W2)>L>(a* (W1+W2)-W2), wherein a
For positive integer.Main loop field plate 13 covers the second end portion 114b of lightly doped district 114, helps to relax
The slow portion 114b of concentration second end originally electric-field intensity.This is to apply field plate principle, is gently mixed to extend
The exhaustion region that miscellaneous area 114 extends outward, to reduce in first end portion 114a and second end portion 114b
PN junctions Interface electric field intensity so that the breakdown voltage of super junction semiconductor subassembly 1 meet need
Ask.
Referring again to Fig. 1, these p-type doped regions 110,111 are on the 11a of surface along a first direction
D1 extends.The plan view shape of main loop field plate 13 has first straight line section 13a, second straight line section 13b
And turning point 13c.First straight line section 13a is parallel with first direction D1, and second straight line section 13b
Then substantially parallel with second direction D2, wherein first direction D1 is vertical with second direction D2.Namely
Say, second straight line section 13b is substantially vertical with first straight line section 13a.
Turning point 13c is connected between first straight line section 13a and second straight line section 13b, and corresponding to group
A part area A1 corner is set.In embodiments of the present invention, turning point 13c can be arc turning point
Or right angle turns portion, it is of the invention not to be any limitation as.
Multiple transistor arrangements 15 be located at component area A1 in, and including matrix area 150, source area 151,
Gate insulation layer 152, gate 153, dielectric layer 154 and source layer 155.
Matrix area 150 have and substrate 10 and the opposite conductivity type of drift layer 11, and and lightly doped district
114 have identical conductivity type.For example, substrate 10 and drift layer 11 adulterate for n-type, then base
Body area 150 is all p-type doping with lightly doped district 114, and matrix area 150 is with being lightly doped in one embodiment
Area 114 can be designed adulterates simultaneously.Also, each matrix area 150 is that connection is located in component area A1
Each p-type doped region 110.Specifically, matrix area 150 is connected to p-type doped region 110 and leaned on
The nearly surface 11a of drift layer 11 one end.
At least source region 151 is formed in each matrix area 150, and source area 151 has and base
The opposite conductivity type in body area 150, and there is identical conductivity type with drift layer 11 and substrate 10.In figure
In embodiment shown by 2, provided with two source areas 151 being separated from each other in each matrix area 150.
Each source area 151 by n-type doped region 112 in matrix area 150 and component area A1 mutually every
From.
Gate insulation layer 152 is all arranged on the surface 11a of drift layer 11 with gate 153, and gate
153 are electrically insulated by gate insulation layer 152 and drift layer 11.Furthermore, in the present embodiment,
The position for the n-type doped region 112 that gate 153 is corresponded in component area is arranged on gate insulation layer 152
On.In addition, gate 153 and the part of source area 151 in matrix area 150 overlap.
Dielectric layer 154 is covered on gate 153, and with multiple contact hole h1 (2 are shown in Fig. 2).
Multiple contact hole h1 are the positions for corresponding respectively to matrix area 150.That is, not yet forming source
Before pole layer 155, part source area 151 can be exposed with part of matrix area 150 by contact hole h1
In on the surface 11a of drift layer 11.
Source layer 155 is covered on dielectric layer 154.Source layer 155 is by contact hole h1 and each
Individual source area 151 is electrically connected with.In addition, source layer 155 and and being lightly doped in the A2 of termination environment
Area 114 is electrically connected with.
It should be noted that, source layer 155 and main loop field plate 13 are separated from each other, as shown in Figure 2.In detail
For thin, the end face 155e of source layer 155 and the first end face 131 of main loop field plate 13 are relatively simultaneously
It is separated by a predetermined distance d, and foregoing predetermined distance d is at least above one of p-type doped region 111
The first width W1, or more than the second width W2 of one of n-type doped region 113.It is real one
Apply in example, source layer 155 may be selected from by titanium, platinum, tungsten, nickel, chromium, molybdenum, tin and its metal silicide
The group constituted is one kind of.
In addition, the super junction semiconductor subassembly 1 of the present embodiment further includes the (closed of sealing ring 16 of a closing
Seal ring), with around termination environment A2 and component area A1.Sealing ring 16 can prevent what is produced during cutting
The super junction semiconductor subassembly 1 of stress damage.In addition, the material of sealing ring 16 be usually conductive material (such as：
Metal) and can electrical ground, to avoid the electrostatic produced in cutting process from concentrating on sealing ring 16, production
Give birth to static discharge (electrostatic discharge, ESD) and damage super junction semiconductor subassembly 1.
Fig. 3 A, Fig. 3 B and Fig. 4 are refer to, wherein Fig. 3 A show the super of another embodiment of the present invention
The schematic top plan view of junction semiconductor subassembly, Fig. 3 B are the enlarged drawing in Fig. 3 A in region A, Fig. 4
For the diagrammatic cross-section of IV-IV along in Fig. 3 A.The super junction semiconductor subassembly 1 ' of the present embodiment and previous
In the super junction semiconductor subassembly 1 of embodiment, identical component has identical label, and identical portion
Divide and repeat no more.The super junction semiconductor subassembly 1 ' of the present embodiment in addition to main loop field plate 13 ',
Also include at least one means of complementary annular field plate 14 (being shown in Fig. 3 A multiple).
Please also refer to Fig. 4, the main loop field plate 13 ' of the present embodiment can equally cover lightly doped district 114
Second end portion 114b, to reduce second end portion 114b electric-field intensity.In the present embodiment, it is main
Annular field plate 13 ' protrudes from second end portion 114b length L1, that is, main loop field plate 13 '
Second end face 131 ' is to second end portion 114b beeline, and p-type doped region 110,111
Between first width W1, following relationship is met：(a*(W1+W2)>L1>(a* (W1+W2)-W2)),
Wherein L1 is the length, and W1 is first width, and W2 is second width, and a is just whole
Number.
In the embodiment of the present invention, the width of main loop field plate 13 ' can be more than any one means of complementary annular field plate
14 width, in one embodiment, means of complementary annular field plate 14 can design same widths w, such as Fig. 4 institutes
Show.In addition, the material for constituting main loop field plate 13 ' and means of complementary annular field plate 14 is conductive material, example
In this way metal either heavy doping polysilicon.In addition, in embodiments of the present invention, main loop field plate 13 '
It is suspension joint.
Fig. 3 A are refer to, means of complementary annular field plate 14 is located at the outside of main loop field plate 13 ', and around master
Ring-like field plate 13 '.Each means of complementary annular field plate 14 has one and first direction D1 almost parallel
First straight line portion 14a, and the almost parallel second straight line portion 14b of second direction D2, and it is connected to
Return portion 14c between one line part 14a and second straight line portion 14b.
As shown in Fig. 3 B and Fig. 4, first straight line portion 14a can cover two adjacent n-type doped regions 113
A boundary between p-type doped region 111.That is, means of complementary annular field plate 14 is mixed across n-type
Miscellaneous area 113 interlocks with p-type doped region 111.Also, the closer component area A1 of means of complementary annular field plate 14
One end be p-type doped region 111, the opposite other end be n-type doped region 113.In other words, Mei Yifu
The inward flange for helping annular field plate 14 is located on p-type doped region 111, and means of complementary annular field plate 14 is outer
Edge is located on n-type doped region 113.
In one embodiment, width w (the namely first straight line portion 14a width of means of complementary annular field plate 14
Degree), the width W1 of p-type doped region 111, and the width W2 of n-type doped region 113 meet following
Relational expression：w≧0.5(W1+W2).
It should be noted that, close to surface 11a and n-type doped region 113 and p-type doped region 111
Intersection, can have larger electric-field intensity.Therefore, means of complementary annular field plate 14 is covered in n-type doping
Mixed with the boundary of p-type doped region 111, contributing to improve in n-type doped region 113 and p-type in area 113
The phenomenon that the electric field of the miscellaneous intersection of area 111 is concentrated, and optimizing surface Electric Field Distribution, to improve super junction half
The breakdown voltage of conductor assembly 1 '.Furthermore, using field plate principle, expansible lightly doped district is past
The exhaustion region of outer extension, to reduce the PN junctions in n-type doped region 113 and p-type doped region 111
Electric-field intensity.
It refer to Fig. 3 B, the return portion 14c of means of complementary annular field plate 14 and the turnover of main loop field plate 13
Portion 13c is all arc.In the present embodiment, positioned at outermost means of complementary annular field plate 14 width compared with
Other aid in the width of ring-like field plate 14 big, and return portion 14c can cover each p-type doped region
111 end 111a.As shown in Figure 3 B, institute between the end 111a of each p-type doped region 111
The online of formation is a curved line, and positioned at the return portion 14c of outermost means of complementary annular field plate 14
Overlapped with foregoing curved line.
In addition, Fig. 3 A and Fig. 3 B are refer to, a part of p-type doped region similar with Fig. 1 embodiment
110 can be tossed about by component area A1 Nei Chao components area A1 two-phase extends out in the A2 of termination environment.But
In the present embodiment, 110 liang of opposite end 110a of each p-type doped region are positioned at outermost auxiliary
Help the lower section of toroidal field intralamellar part 14.That is, positioned at the outermost means of complementary annular field plates of termination environment A2
Two opposite ends of 14 meeting blanket p-type doped regions 110.In addition, by Fig. 3 B it can also be seen that being located at
Outermost means of complementary annular field plate 14 can also cover two opposite ends of another part p-type doped region 111
111a。
Continue referring to Fig. 5.Fig. 5 is the part of the super junction semiconductor subassembly of another embodiment of the present invention
Schematic top plan view.In the present embodiment, main loop field plate 23 has rectangular turning point 23c.Similarly,
Means of complementary annular field plate 24 also has rectangular return portion 24c.In addition, the embodiment phase with Fig. 3 B
Seemingly, the end of each p-type doped region 110,111 can be covered positioned at outermost means of complementary annular field plate 24
Portion 110a, 111a.In this way, the exhaustion region that expansible lightly doped district 11 extends outward, to reduce in p
The electric-field intensity of end 110a, 111a of type doped region 110,111 PN junctions.
In other embodiments, it is not necessarily to blanket p-type doping positioned at outermost means of complementary annular field plate
End 110a, the 111a in area 110,111.Fig. 6 is refer to, it shows another embodiment of the present invention
The schematic top plan view of super junction semiconductor subassembly.In the present embodiment, multiple means of complementary annular field plate 34a,
34b is sequentially arranged on the A2 of termination environment from inside to outside.
Multiple p-type doped regions extend to the outermost means of complementary annular field plates of termination environment A2 by component area A1
34b outside.That is, a part for p-type doped region 111,110 can extend beyond means of complementary annular
Field plate 34b encloses the scope set.It is seen by top view, the end of each p-type doped region 110,111
Portion 110a, 111a are located between sealing ring 36 and outermost means of complementary annular field plate 34b.
In summary, in the super junction semiconductor subassembly of the embodiment of the present invention, multiple p-type doped regions are horizontal
Across component area and termination environment.For known super junction transistor component, epitaxial growth process is utilized
When forming these p-type doped regions, because p-type doped region does not have circular arc-shaped corner, it is not necessary to consider lattice
The problem of whether face matches, it is possible to decrease processing procedure difficulty and lifting epitaxy quality.Secondly, mixed in formation p-type
During miscellaneous area, also it can make p-type doped region that there is more uniform impurity doping concentration, so as to avoid super junction
Semiconductor subassembly it is pressure-resistant because n-type impurity doping concentration is uneven and reduces.
In addition, super junction semiconductor subassembly provided by the present invention, coordinates main loop field plate and means of complementary annular
Field plate, can improve the Electric Field Distribution in drift layer, so that the overall collapse electricity of super junction semiconductor subassembly
Pressure meets the requirements.Specifically, main loop field plate covers the second end portion of lightly doped district, it is possible to decrease
The electric-field intensity in second end portion, so as to improve the overall breakdown voltage of super junction semiconductor subassembly.
Although embodiments of the present invention are disclosed above, the right present invention is not limited to above-described embodiment, appoints
What those of ordinary skill in the art, is not departing from disclosed herein it in the range of, when can
Make a little change and adjustment, therefore the equivalence techniques for using description of the invention and figure content to be done such as
Change, is both contained in protection scope of the present invention.
Claims (12)
1. a kind of super junction semiconductor subassembly, it is characterised in that the super junction semiconductor subassembly includes：
One substrate；
One drift layer, is arranged on the substrate, and the surface with contrast to the substrate, wherein institute
Stating has multiple n-type doped regions and multiple p-type doped regions inside drift layer, multiple n-types are mixed
Miscellaneous area and multiple p-type doped regions by the surface towards the substrate direction extension and alternately
Arrangement, formation one surpasses contact structure, wherein the drift layer defines a component area and around described group
One termination environment in part area；
One lightly doped district, inside the drift layer and connects the surface, and the lightly doped district has
One close to the component area first end portion and a second end portion away from the component area；
One insulating barrier, is arranged on the surface and covers the termination environment；And
One main loop field plate, is arranged on the insulating barrier, makes the main loop field plate covering second end
End.
2. super junction semiconductor subassembly as claimed in claim 1, p-type doped region has described in each of which
One first width W1 and one first concentration p1, each n-type doped region has one second width
W2 and one second concentration n1, and meet following relationship：p1*W1≈n1*W2.
3. super junction semiconductor subassembly as claimed in claim 1, wherein the termination environment, which has, at least has six
Group p-type doped region is alternately arranged with n-type doped region.
4. super junction semiconductor subassembly as claimed in claim 1, wherein the main loop field plate protrudes from institute
State the length L of second end portion one, each p-type doped region has one first width W1, each
The n-type doped region has one second width W2, and meets following relationship：a*(W1+W2)>
L>(a* (W1+W2)-W2), wherein a is positive integer.
5. super junction semiconductor subassembly as claimed in claim 4, is still further comprised：An at least subring
Shape field plate is located at the termination environment and surrounds the main loop field plate, wherein the main loop field plate
Width is more than the width of any means of complementary annular field plate.
6. super junction semiconductor subassembly as claimed in claim 5, wherein the width of the means of complementary annular field plate
All it is all mutually w, meets following relationship：w≧0.5(W1+W2).
7. super junction semiconductor subassembly as claimed in claim 5, wherein the means of complementary annular field plate is across institute
State p-type doped region with the n-type doped region to interlock, wherein closer group of the means of complementary annular field plate
Part area one end is p-type doped region, and the opposite other end is n-type doped region.
8. super junction semiconductor subassembly as claimed in claim 5, the plurality of p-type doped region is by institute
Component area is stated to extend to inside the outermost means of complementary annular field plate of the termination environment.
9. super junction semiconductor subassembly as claimed in claim 5, wherein the p-type doped region is by described group
The outermost means of complementary annular field plate that part area extends to the termination environment is outside.
10. super junction semiconductor subassembly as claimed in claim 1, is still further comprised：At least one is located at institute
The transistor arrangement in component area is stated, the transistor arrangement includes a source layer, wherein the master
Annular field plate has the end face close to the component area, one end of the end face and the source layer
Face is relative and is separated by a preset distance, and the preset distance is at least above the p-type doped region
One first width.
11. super junction semiconductor subassembly as claimed in claim 1, wherein, multiple p-type doped regions
There is a roughly the same bearing of trend on said surface, the main loop field plate has and described
The parallel first straight line section of the bearing of trend second straight line section vertical with the bearing of trend with
And the turning point between the first straight line section and second straight line section is connected to, wherein described
Turning point is an arc turning point or a right angle turning point.
12. super junction semiconductor subassembly as claimed in claim 1, further includes a sealing ring, around institute
Termination environment periphery is stated, to avoid static discharge from producing.
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| CN201610250234.0A CN107305910B (en) | 2016-04-21 | 2016-04-21 | Super junction semiconductor assembly |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445860A (en) * | 2002-03-18 | 2003-10-01 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| US20050280086A1 (en) * | 2004-06-21 | 2005-12-22 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN103794640A (en) * | 2012-10-31 | 2014-05-14 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device comprising a cell area and an edge area |
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2016
- 2016-04-21 CN CN201610250234.0A patent/CN107305910B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445860A (en) * | 2002-03-18 | 2003-10-01 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| US20050280086A1 (en) * | 2004-06-21 | 2005-12-22 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN103794640A (en) * | 2012-10-31 | 2014-05-14 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device comprising a cell area and an edge area |
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