CN107305910B - Super junction semiconductor assembly - Google Patents
Super junction semiconductor assembly Download PDFInfo
- Publication number
- CN107305910B CN107305910B CN201610250234.0A CN201610250234A CN107305910B CN 107305910 B CN107305910 B CN 107305910B CN 201610250234 A CN201610250234 A CN 201610250234A CN 107305910 B CN107305910 B CN 107305910B
- Authority
- CN
- China
- Prior art keywords
- region
- type doped
- doped regions
- field plate
- annular field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000015556 catabolic process Effects 0.000 description 15
- 230000005684 electric field Effects 0.000 description 14
- 239000012535 impurity Substances 0.000 description 14
- 210000000746 body region Anatomy 0.000 description 12
- 238000000034 method Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- -1 phosphorus ion Chemical class 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A super junction semiconductor component comprises a substrate, a drift layer arranged on the substrate, a lightly doped region, an insulating layer and a main annular field plate. The drift layer is provided with a plurality of n-type doped regions and a plurality of p-type doped regions, and the n-type doped regions and the p-type doped regions are alternately arranged to form a super junction structure. The drift layer defines a device region and a termination region surrounding the device region. The lightly doped region is located in the drift layer and connected to the surface, and the lightly doped region has a first end portion close to the device region and a second end portion far away from the device region. The insulating layer is arranged on the surface and at least covers the terminal area. A main annular field plate is disposed on the insulating layer, wherein the main annular field plate covers the second end portion.
Description
Technical Field
The present invention relates generally to semiconductor devices, and more particularly to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device having a super junction structure.
Background
In a super-junction transistor device, the on-resistance (Rds-on) increases in proportion to the increase of the Breakdown Voltage (BV), which is more slowly than the conventional semiconductor structure. Therefore, the superjunction transistor device can have a low on-resistance (rds-on) while maintaining a high off-state (BV) breakdown voltage.
A superjunction transistor device typically has an active region and a termination region surrounding the active region. When the super junction device is in an off state, there is an electric field distribution in both the vertical and horizontal directions of the termination region.
In conventional superjunction transistor devices, the top-down shape of the p-type doped region within the termination region is a ring. However, when the p-type doped region is formed by an epitaxial process, a special lattice plane is required to be formed at the corner so that the p-type doped region has a better lattice arrangement at the corner. Thus, the process difficulty is increased. In addition, the impurity doping concentration at the corner is not easy to control, and the voltage resistance of the super junction transistor component at the termination region can be reduced.
Disclosure of Invention
The invention provides a super junction semiconductor component, wherein a plurality of p-type doped regions of the super junction semiconductor component extend into a terminal region from a component region to two opposite sides of the component region, and the breakdown voltage of the super junction semiconductor component in an OFF-state (OFF-state) can meet the requirement by matching with the design of an annular field plate.
One embodiment of the present invention provides a super junction semiconductor device, which includes a substrate, a drift layer, a lightly doped region, an insulating layer, and a main ring field plate. The drift layer is arranged on the substrate and provided with a surface opposite to the substrate, wherein a plurality of n-type doped regions and a plurality of p-type doped regions are formed in the drift layer, and the n-type doped regions and the p-type doped regions extend from the surface to the direction of the substrate and are alternately arranged to form a super junction structure. The drift layer defines a device region and a termination region surrounding the device region. The lightly doped region is located in the drift layer and connected to the surface, and the lightly doped region has a first end portion close to the device region and a second end portion far away from the device region. The insulating layer is arranged on the surface and covers the terminal area. The main annular field plate is disposed on the insulating layer such that the main annular field plate covers the second end portion.
In summary, in the super junction semiconductor device provided by the present invention, the main ring field plate covers the second end portion of the lightly doped region, so that the electric field intensity at the second end portion can be reduced, and the breakdown voltage of the whole super junction semiconductor device can be increased. In addition, in the super junction semiconductor device according to the embodiment of the invention, the plurality of p-type doped regions extend from the device region to two opposite sides of the device region into the termination region. Compared with the conventional super junction transistor device, when the p-type doped regions are formed by an epitaxial process, the epitaxial uniformity can be improved and the process complexity can be reduced because the p-type doped regions have no corners.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic top view of a super junction semiconductor device according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view along the line II-II in fig. 1.
Fig. 3A is a schematic top view of a super junction semiconductor device according to another embodiment of the present invention.
Fig. 3B is an enlarged view of fig. 3A at area a.
Fig. 4 is a schematic cross-sectional view along the line IV-IV in fig. 3A.
Fig. 5 is a partial top view of a super junction semiconductor device according to another embodiment of the present invention.
Fig. 6 is a schematic top view of a super junction semiconductor device according to another embodiment of the present invention.
Reference numerals:
super junction semiconductor elements 1, 1', 3; a substrate 10; an upper surface 10 a; a back surface 10 b;
a drift layer 11; a surface 11 a; an insulating layer 12; primary annular field plates 13, 13', 23;
a first straight line segment 13a, 13' a, 23 a; second straight sections 13b, 13' b, 23 b;
turns 13c, 13' c, 23 c; a first end face 131, 131'; second end faces 132, 132';
length L, L1; a transistor structure 15; module area a 1; terminal area a 2;
n-type doped regions 112, 113; a second width W2; p-type doped regions 110, 111;
ends 110a, 111 a; a first width W1; a lightly doped region 114; a first end portion 114 a;
a second end portion 114 b; a first direction D1; a second direction D2; contact windows h 1;
a base region 150; a source region 151; a gate insulating layer 152; a gate electrode 153; a dielectric layer 154;
a source layer 155; end surfaces 155 e; a predetermined distance d; seal rings 16, 26, 36;
auxiliary annular field plates 14, 24, 34a, 34 b; the first rectilinear portions 14a, 24 a;
second linear portions 14b, 24 b; return portions 14c, 24 c; width w
Detailed Description
Reference is now made to fig. 1 and 2, wherein fig. 1 is a schematic top view of a super junction semiconductor device according to an embodiment of the present invention, and fig. 2 is a schematic cross-sectional view taken along line II-II in fig. 1.
The super junction semiconductor device 1 of the embodiment of the invention includes a substrate 10, a drift layer 11, a lightly doped region 114, an insulating layer 12, a main ring field plate 13 and at least one transistor structure 15.
In fig. 2, the substrate 10 is a semiconductor substrate and has an upper surface 10a and a back surface 10b opposite to the upper surface 10 a. The substrate 10 has a high concentration of the first conductive type impurity. The first conductive type impurity may be distributed in a local region of the substrate 100 or in the entire substrate 10 to serve as a drain contact layer. The first conductive type impurities in the present embodiment are distributed in the whole substrate 10, but are only for illustration and not for limiting the invention. Drain contact pads (not shown) are formed on the back surface 10b of the substrate 10 for electrical connection to external control circuitry.
The first conductive type impurity may be an N-type or P-type conductive type impurity. Assuming that the substrate 10 is a silicon substrate, the N-type conductivity impurity is a pentavalent element ion, such as a phosphorus ion or an arsenic ion, and the P-type conductivity impurity is a trivalent element ion, such as a boron ion, an aluminum ion, or a gallium ion.
The drift layer (drift layer)11 is located on the upper surface 10a of the substrate 10 and has a low concentration of first-type conductivity impurities. In the present embodiment, the substrate 10 is doped with N + with high concentration, and the drift layer 11 is doped with N + with low concentration. The drift layer 11 is connected on one side to the upper surface 10a of the substrate 10 and has a surface 11a opposite to the other side of the substrate 10.
As shown in fig. 1 and fig. 2, in the present embodiment, the drift layer 11 is defined as a device region a1 and a termination region (termination area) a2 surrounding the device region a 1. As shown in fig. 1, the device region a1 is located in the central region of the superjunction semiconductor device 1, and the terminal region a2 surrounds the device region a1 and is located in the peripheral region of the superjunction semiconductor device 1.
Referring to fig. 2, the drift layer 11 has a plurality of n-type doped regions 112 and 113 and a plurality of p-type doped regions 110 and 111 therein. The n-type doped regions 112, 113 and the p-type doped regions 110, 111 are alternately juxtaposed to form a super junction structure. The n-type doped regions 112 and 113 and the p-type doped regions 110 and 111 extend in the current flowing direction, that is, from the surface 11a of the drift layer 11 toward the substrate 10.
Referring to fig. 1, in the present embodiment, a portion of the p-type doped region 110 extends from the device region a1 to the two sides of the device region a1 and to the termination region a 2. That is, the middle portion and the rear portion of each p-type doped region 110 are located in the device region a1, and the front end portion and the rear end portion are located in the terminal region a 2.
In the embodiment of fig. 2, the p-type doped regions 110 and 111 are pillars (pylon), and the n-type doped regions 112 and 113 are respectively staggered and surround the p-type doped regions 110 and 111. Further, a plurality of parallel trenches are formed in the drift layer 11, and then p-type epitaxial material is filled in the trenches to form the p-type doped regions 110 and 111.
When the super junction semiconductor device 1 is in an On state, the n-type doped regions 112, 113 and the p-type doped regions 110, 111 provide charges, and when the super junction semiconductor device 1 is in an Off state, the n-type doped regions 112, 113 and the p-type doped regions 110, 111 are depleted (or depleted) in a horizontal direction to achieve charge balance in the drift layer 11. Therefore, the super junction semiconductor device 1 can have a higher breakdown voltage with a relatively lower on-resistance.
If the impurity doping concentration in the p-type doped regions 110 and 111 is not uniform, the charges in the drift layer 11 may not be depleted, and the breakdown voltage of the super junction semiconductor device 1 may be reduced. Therefore, in the embodiment of the invention, the p-type doped regions 110, 111 are parallel to each other and are aligned in the drift layer 11, and each of the p-type doped regions 110, 111 has no turning section. When the p-type doped regions 110, 111 are formed, the p-type doped regions 110, 111 can have a relatively uniform impurity doping concentration, so that the breakdown voltage of the super junction semiconductor assembly 1 can be prevented from being reduced due to the non-uniform p-type impurity doping concentration.
Since the p-type doped regions 110, 111 are parallel to each other and are aligned in the drift layer 11, each p-type doped region 110, 111 has no turning section. Therefore, when filling the p-type epitaxial material to form the p-type doped regions 110 and 111, there is no need to consider whether the lattice planes are matched, which can reduce the process difficulty and improve the epitaxial quality of the p-type doped regions 110 and 111.
In the embodiment of the invention, each of the p-type doped regions 110, 111 has a first width W1 and a first concentration p1, and each of the n-type doped regions has a second width W2 and a concentration n 1. Further, two adjacent p-type doped regions 110 and 111 are separated from each other by a predetermined distance, which is the second width W2 of the n-type doped regions 112 and 113. In one embodiment, the first width W1, the second width W2, the first concentration p1 and the second concentration n1 satisfy the following relationship: p1 × W1 × n1 × W2.
It should be noted that the area of the termination region a2 also affects the breakdown voltage of the superjunction semiconductor device 1. Typically the breakdown voltage increases as the area of the termination region a2 increases. In the embodiment shown in fig. 2, at least six sets of p-type doped regions 111 and n-type doped regions 113 are provided in the termination region a2 to extend the electric field distribution range, thereby increasing the breakdown voltage of the super junction semiconductor device 1 as a whole.
Referring to fig. 2, in the present embodiment, the drift layer 11 further has a lightly doped region 114 adjacent to the surface 11a of the drift layer 11 in the termination region a2, and the lightly doped region 114 is connected between the p-type doped region 111 and the surface 11. Further, the lightly doped region 114 is located on a side of the p-type doped region 111 close to the surface 11a of the drift layer 11 and is connected to the surface 11 a. In addition, the lightly doped region 114 has a conductivity type opposite to that of the drift layer 11. In the present embodiment, the lightly doped region 114 extends from the device region a1 to the termination region a2, and has a first terminal portion 114a located in the device region a1 and a second terminal portion 114b located in the termination region a 2.
The insulating layer 12 is disposed on the surface 11a of the drift layer 11 covering the termination region a 2. In one embodiment, the insulating layer 12 is an oxide layer or a nitride layer. Referring to fig. 1 and 2, the main annular field plate 13 is disposed on the insulating layer 12 in a surrounding manner to extend the electric field range in the drift layer 11, so as to improve the voltage resistance of the superjunction semiconductor device 1 in the termination region a 2. As shown in fig. 1, the main annular field plate 13 is located in the peripheral region of the superjunction semiconductor device 1 and surrounds the central region of the superjunction semiconductor device 1.
Referring to fig. 2, in the embodiment of the present invention, the main annular field plate 13 covers the second end portion 114b of the lightly doped region 114, so that the second end portion 114b is located below the main annular field plate 13. In detail, the primary annular field plate 13 has a first end face 131 close to the device region a1 and a second end face 132 far from the device region a1, wherein the first end face 131 and the second end face 132 are opposite and different. In the present embodiment, the position of the main annular field plate 13 overlaps at least a portion of the lightly doped region 114, and the main annular field plate 13 exceeds the second end portion 114b by a length L, i.e. a distance between the second end surface 132 of the main annular field plate 13 and the second end portion 114b of the lightly doped region 114.
It should be noted that, through simulation tests, the position of the main annular field plate 13 and the length L extending beyond the second end portion 114b both affect the breakdown voltage of the superjunction semiconductor device 1. In the present embodiment, the portion of the main annular field plate 13 extending beyond the second end portion 114b covers at least two p-type doped regions 111 and an n-type doped region. That is, the length L, the first width W1, and the second width W2 satisfy the following relationship: a (W1+ W2) > L > (a (W1+ W2) -W2), wherein a is a positive integer. The main annular field plate 13 covers the second end portion 114b of the lightly doped region 114, which helps to relieve the electric field intensity that would otherwise concentrate at the second end portion 114 b. This is to extend the depletion region extending outward from the lightly doped region 114 by applying the field plate principle to reduce the interface electric field strength of the PN junction at the first terminal portion 114a and the second terminal portion 114b, so as to make the breakdown voltage of the super junction semiconductor device 1 meet the requirement.
Referring to fig. 1 again, the p-type doped regions 110 and 111 extend along a first direction D1 on the surface 11 a. The main annular field plate 13 has a top view shape having a first straight line segment 13a, a second straight line segment 13b, and a turn 13 c. The first straight line segment 13a is parallel to the first direction D1, and the second straight line segment 13b is substantially parallel to the second direction D2, wherein the first direction D1 is perpendicular to the second direction D2. That is, the second straight line segment 13b is substantially perpendicular to the first straight line segment 13 a.
The turning portion 13c is connected between the first straight line segment 13a and the second straight line segment 13b, and is disposed corresponding to a corner of the component area a 1. In the embodiment of the present invention, the turning portion 13c may be an arc-shaped turning portion or a right-angle turning portion, and the present invention is not limited thereto.
The plurality of transistor structures 15 are located in the device region a1 and include a body region 150, a source region 151, a gate insulating layer 152, a gate electrode 153, a dielectric layer 154, and a source layer 155.
The body region 150 has a conductivity type opposite to that of the substrate 10 and the drift layer 11, and has the same conductivity type as the lightly doped region 114. For example, the substrate 10 and the drift layer 11 are doped n-type, and the body region 150 and the lightly doped region 114 are doped p-type, in one embodiment, the body region 150 and the lightly doped region 114 can be designed to be doped simultaneously. Also, each body region 150 is connected to each p-doped region 110 located within assembly region a 1. In detail, the body region 150 is connected to one end of the p-type doped region 110 near the surface 11a of the drift layer 11.
At least one source region 151 is formed in each body region 150, and the source region 151 has a conductivity type opposite to that of the body region 150 and the same conductivity type as the drift layer 11 and the substrate 10. In the embodiment shown in fig. 2, two source regions 151 are disposed in each body region 150, which are separated from each other. Each source region 151 is isolated from each other by the body region 150 and the n-type doped region 112 in the assembly region a 1.
The gate insulating layer 152 and the gate electrode 153 are disposed on the surface 11a of the drift layer 11, and the gate electrode 153 is electrically insulated from the drift layer 11 by the gate insulating layer 152. Further, in the present embodiment, the gate electrode 153 is disposed on the gate insulating layer 152 at a position corresponding to the n-type doped region 112 in the device region. In addition, the gate electrode 153 overlaps the source region 151 in the body region 150.
The dielectric layer 154 covers the gate 153 and has a plurality of contact holes h1 (2 shown in FIG. 2). The plurality of contact windows h1 are located to correspond to the base regions 150, respectively. That is, before the source layer 155 is formed, a portion of the source region 151 and a portion of the body region 150 are exposed on the surface 11a of the drift layer 11 through the contact window h 1.
A source layer 155 overlies the dielectric layer 154. Source layer 155 is electrically connected to each source region 151 through contact h 1. In addition, the source layer 155 is electrically connected to the lightly doped region 114 in the termination region a 2.
Note that the source layer 155 and the main annular field plate 13 are separated from each other, as shown in fig. 2. In detail, an end surface 155e of the source layer 155 is opposite to and spaced apart from the first end surface 131 of the main annular field plate 13 by a predetermined distance d, and the predetermined distance d is at least greater than the first width W1 of one of the p-type doped regions 111 or greater than the second width W2 of one of the n-type doped regions 113. In one embodiment, the source layer 155 may be selected from one of the group consisting of titanium, platinum, tungsten, nickel, chromium, molybdenum, tin, and metal silicides thereof.
In addition, the super junction semiconductor device 1 of the present embodiment further includes a closed seal ring 16(closed seal ring) surrounding the termination region a2 and the device region a 1. The seal ring 16 prevents the stress generated during dicing from damaging the super junction semiconductor device 1. In addition, the material of the seal ring 16 is usually a conductive material (e.g., metal) and can be electrically grounded, so as to prevent the electrostatic discharge (ESD) generated during the dicing process from being concentrated on the seal ring 16 and damaging the super junction semiconductor device 1.
Referring to fig. 3A, fig. 3B and fig. 4, fig. 3A is a schematic top view of a super junction semiconductor device according to another embodiment of the present invention, fig. 3B is an enlarged view of a region a in fig. 3A, and fig. 4 is a schematic cross-sectional view taken along a line IV-IV in fig. 3A. In the super junction semiconductor device 1' of the present embodiment and the super junction semiconductor device 1 of the previous embodiment, the same components have the same reference numerals, and the description of the same parts is omitted. The superjunction semiconductor assembly 1 'of the present embodiment includes at least one auxiliary annular field plate 14 (a plurality are shown in fig. 3A) in addition to the main annular field plate 13'.
Referring to fig. 4, the main annular field plate 13' of the present embodiment also covers the second end portion 114b of the lightly doped region 114 to reduce the electric field intensity of the second end portion 114 b. In the present embodiment, the length L1 of the protrusion of the main annular field plate 13 ' from the second end portion 114b, i.e. the shortest distance from the second end face 131' of the main annular field plate 13 ' to the second end portion 114b, and the first width W1 of the p-type doped regions 110 and 111 satisfy the following relation: (a (W1+ W2) > L1> (a (W1+ W2) -W2)), wherein L1 is the length, W1 is the first width, W2 is the second width, and a is a positive integer.
In the embodiment of the present invention, the width of the main annular field plate 13' is larger than the width of any one of the auxiliary annular field plates 14, and in one embodiment, the auxiliary annular field plates 14 may be designed to have the same width w, as shown in fig. 4. In addition, the material of the main annular field plate 13' and the auxiliary annular field plate 14 is a conductive material, such as metal or heavily doped polysilicon. In addition, in the present embodiment, the main annular field plate 13' is floating.
Referring to fig. 3A, the auxiliary annular field plate 14 is located outside the main annular field plate 13 'and surrounds the main annular field plate 13'. Each auxiliary annular field plate 14 has a first straight portion 14a substantially parallel to the first direction D1, a second straight portion 14b substantially parallel to the second direction D2, and a turning portion 14c connected between the first straight portion 14a and the second straight portion 14 b.
As shown in fig. 3B and fig. 4, the first linear portion 14a covers a boundary between two adjacent n-type doped regions 113 and p-type doped regions 111. That is, the auxiliary annular field plates 14 cross the n-type doped regions 113 and the p-type doped regions 111. Also, one end of the auxiliary annular field plate 14 closer to the assembly region a1 is a p-type doped region 111, and the opposite end is an n-type doped region 113. In other words, the inner edge of each auxiliary annular field plate 14 is located on the p-type doped region 111, and the outer edge of the auxiliary annular field plate 14 is located on the n-type doped region 113.
In an embodiment, the width W of the auxiliary annular field plate 14 (i.e., the width of the first linear portion 14 a), the width W1 of the p-type doped region 111, and the width W2 of the n-type doped region 113 satisfy the following relationship: w ≧ 0.5(W1+ W2).
It should be noted that the electric field intensity near the surface 11a and the boundary between the n-type doped region 113 and the p-type doped region 111 is larger. Therefore, the auxiliary ring-shaped field plate 14 covers the boundary between the n-type doped region 113 and the p-type doped region 111, which helps to improve the electric field concentration at the boundary between the n-type doped region 113 and the p-type doped region 111 and optimize the surface electric field distribution, so as to increase the breakdown voltage of the super junction semiconductor device 1'. Further, by applying the field plate principle, the depletion region extending outward from the lightly doped region can be expanded to reduce the electric field strength at the PN junction of the n-type doped region 113 and the p-type doped region 111.
Referring to fig. 3B, the turning portion 14c of the auxiliary annular field plate 14 and the turning portion 13c of the main annular field plate 13 are both arc-shaped. In the present embodiment, the width of the auxiliary ring-shaped field plate 14 located at the outermost side is larger than the width of the other auxiliary ring-shaped field plates 14, and the turning portion 14c covers the end portion 111a of each p-type doped region 111. As shown in fig. 3B, the connection line formed between the end portions 111a of each p-type doped region 111 is an arc line, and the turning portion 14c of the outermost auxiliary ring-shaped field plate 14 is overlapped with the arc line.
Referring to fig. 3A and 3B, similar to the embodiment of fig. 1, a portion of the p-type doped region 110 extends from the device region a1 to the opposite sides of the device region a1 and extends into the termination region a 2. However, in the present embodiment, two opposite ends 110a of each p-type doped region 110 are located below the inner portion 14 of the outermost auxiliary annular field plate. That is, the auxiliary annular field plate 14 located outermost in termination region a2 covers opposite ends of the p-type doped region 110. In addition, as can also be seen from fig. 3B, the auxiliary annular field plate 14 located at the outermost side also covers two opposite end portions 111a of another part of the p-type doped region 111.
Please continue to refer to fig. 5. Fig. 5 is a partial top view of a super junction semiconductor device according to another embodiment of the present invention. In this embodiment, the main annular field plate 23 has a right-angled turn 23 c. Similarly, the auxiliary annular field plate 24 also has a turning portion 24c at a right angle. In addition, similar to the embodiment of fig. 3B, the auxiliary annular field plate 24 located at the outermost side covers the end portions 110a, 111a of each p-type doped region 110, 111. Thus, the depletion region extending outward from the lightly doped region 11 can be expanded to reduce the electric field strength at the PN junctions at the ends 110a, 111a of the p-type doped regions 110, 111.
In other embodiments, the auxiliary annular field plates located at the outermost sides do not necessarily cover the end portions 110a, 111a of the p-type doped regions 110, 111. Referring to fig. 6, a top view of a super junction semiconductor device according to another embodiment of the invention is shown. In the present embodiment, a plurality of auxiliary annular field plates 34a, 34b are disposed on the termination region a2 in sequence from inside to outside.
A plurality of p-type doped regions extend from the assembly region a1 to the outside of the outermost auxiliary annular field plate 34b of termination region a 2. That is, a portion of the p-type doped regions 111 and 110 extends beyond the area enclosed by the auxiliary annular field plate 34 b. The end 110a, 111a of each p-type doped region 110, 111 is located between the seal ring 36 and the outermost auxiliary annular field plate 34b in top view.
In summary, in the super junction semiconductor device according to the embodiment of the invention, a plurality of p-type doped regions span the device region and the termination region. Compared with the conventional super junction transistor device, when the p-type doped regions are formed by the epitaxial process, the p-type doped regions do not have arc corners, so that the problem of matching lattice planes is not required to be considered, the process difficulty is reduced, and the epitaxial quality is improved. Secondly, when the p-type doped region is formed, the p-type doped region can have more uniform impurity doping concentration, so that the reduction of the withstand voltage of the super junction semiconductor component due to the non-uniform p-type impurity doping concentration can be avoided.
In addition, the super junction semiconductor assembly provided by the invention is matched with the main annular field plate and the auxiliary annular field plate, so that the electric field distribution in the drift layer can be improved, and the integral breakdown voltage of the super junction semiconductor assembly meets the requirement. In detail, the main ring-shaped field plate covers the second end portion of the lightly doped region, so that the electric field intensity at the second end portion can be reduced, and the breakdown voltage of the whole super junction semiconductor assembly can be improved.
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and those skilled in the art can make various changes and modifications without departing from the scope of the invention, so that all the equivalent technical changes made by using the contents of the specification and the drawings of the present invention are included in the scope of the present invention.
Claims (12)
1. A superjunction semiconductor device, comprising: a substrate;
a drift layer disposed on the substrate and having a surface opposite to the substrate, wherein the drift layer has a plurality of n-type doped regions and a plurality of p-type doped regions therein, the plurality of n-type doped regions and the plurality of p-type doped regions extend from the surface toward the substrate and are alternately arranged to form a super junction structure, wherein the drift layer defines a device region and a terminal region surrounding the device region;
at least one transistor structure located in the device region, wherein the transistor structure includes a source layer disposed on the drift layer;
a lightly doped region located within the drift layer and connected to the surface, the lightly doped region having a first end portion proximate to the device region and a second end portion distal from the device region; an insulating layer disposed on the surface covering the termination region; and
a main annular field plate disposed on the insulating layer such that the main annular field plate covers the second end portion,
the source layer and the main annular field plate are isolated from each other and do not overlap up and down.
2. The superjunction semiconductor device of claim 1, wherein each of the p-type doped regions has a first width W1 and a first concentration p1, each of the n-type doped regions has a second width W2 and a second concentration n1, and the following relationships are satisfied: p 1W 1 n 1W 2.
3. The superjunction semiconductor device of claim 1, wherein the termination region has at least six sets of alternating p-type and n-type doped regions.
4. The superjunction semiconductor device of claim 1, wherein the main annular field plate protrudes from the second end portion by a length L, each of the p-type doped regions has a first width W1, each of the n-type doped regions has a second width W2, and the following relationship is satisfied: a (W1+ W2) > L > (a (W1+ W2) -W2), wherein a is a positive integer.
5. The superjunction semiconductor device of claim 4, further comprising: at least one auxiliary annular field plate is located in the termination region and surrounds the primary annular field plate, wherein the width of the primary annular field plate is greater than the width of either of the auxiliary annular field plates.
6. The superjunction semiconductor device of claim 5, wherein the widths of the auxiliary annular field plates are all the same as w, satisfying the following relation: w ≧ 0.5(W1+ W2).
7. The superjunction semiconductor device of claim 5, wherein the auxiliary annular field plates cross the p-doped region and the n-doped region, wherein the auxiliary annular field plates are p-doped regions at one end closer to the device region and n-doped regions at the opposite end.
8. The superjunction semiconductor assembly of claim 5, wherein a plurality of said p-type doped regions extend from said assembly region to inside said auxiliary annular field plate outermost of said termination region.
9. The superjunction semiconductor device of claim 5, wherein the p-type doped region extends from the device region to an outer portion of the auxiliary annular field plate outermost of the termination region.
10. The superjunction semiconductor device of claim 1, wherein the primary annular field plate has an end surface adjacent to the device region, the end surface being opposite to an end surface of the source layer and separated by a predetermined distance, and the predetermined distance being at least greater than a first width of the p-type doped region.
11. The superjunction semiconductor device of claim 1, wherein the p-type doped regions have substantially the same extension direction on the surface, the main annular field plate has a first straight line segment parallel to the extension direction, a second straight line segment perpendicular to the extension direction, and a turn portion connected between the first straight line segment and the second straight line segment, wherein the turn portion is an arc turn portion or a straight corner turn portion.
12. The superjunction semiconductor device of claim 1, further comprising a seal ring surrounding the periphery of the termination region for preventing electrostatic discharge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610250234.0A CN107305910B (en) | 2016-04-21 | 2016-04-21 | Super junction semiconductor assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610250234.0A CN107305910B (en) | 2016-04-21 | 2016-04-21 | Super junction semiconductor assembly |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107305910A CN107305910A (en) | 2017-10-31 |
| CN107305910B true CN107305910B (en) | 2019-12-31 |
Family
ID=60151809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610250234.0A Active CN107305910B (en) | 2016-04-21 | 2016-04-21 | Super junction semiconductor assembly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107305910B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445860A (en) * | 2002-03-18 | 2003-10-01 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| CN103794640A (en) * | 2012-10-31 | 2014-05-14 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device comprising a cell area and an edge area |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006005275A (en) * | 2004-06-21 | 2006-01-05 | Toshiba Corp | Semiconductor device for electric power |
-
2016
- 2016-04-21 CN CN201610250234.0A patent/CN107305910B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445860A (en) * | 2002-03-18 | 2003-10-01 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| CN103794640A (en) * | 2012-10-31 | 2014-05-14 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device comprising a cell area and an edge area |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107305910A (en) | 2017-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7655975B2 (en) | Power trench transistor | |
| US8759938B2 (en) | Semiconductor device | |
| TWI455307B (en) | Charge balance techniques for power devices | |
| US11031479B2 (en) | Semiconductor device with different gate trenches | |
| JP5701802B2 (en) | Power semiconductor device | |
| JP5517688B2 (en) | Semiconductor device | |
| US7859076B2 (en) | Edge termination for semiconductor device | |
| US9941354B2 (en) | Semiconductor device comprising a first gate trench and a second gate trench | |
| US20150041889A1 (en) | Multi-gate vdmos transistor and method for forming the same | |
| TWI567978B (en) | Super-junction semiconductor device | |
| JP5685991B2 (en) | Semiconductor device | |
| US9704954B2 (en) | Semiconductor device and a method for forming a semiconductor device | |
| CN111295763A (en) | Wide band gap semiconductor device | |
| WO2017090183A1 (en) | Semiconductor device | |
| US20230420555A1 (en) | Semiconductor device | |
| CN107305910B (en) | Super junction semiconductor assembly | |
| US9711636B2 (en) | Super-junction semiconductor device | |
| US9882043B2 (en) | Semiconductor device with trench termination structure | |
| US10374076B2 (en) | Shield indent trench termination for shielded gate MOSFETs | |
| KR20160111307A (en) | Semiconductor device | |
| CN107710408B (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN111164764A (en) | Schottky barrier diode with improved schottky contact for high voltage | |
| JP7404601B2 (en) | semiconductor integrated circuit | |
| US10847610B2 (en) | Semiconductor device | |
| JP2024009372A (en) | Super-junction semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |