CN107305910B - Superjunction Semiconductor Components - Google Patents

Abstract

A superjunction semiconductor component comprises a substrate, a drift layer disposed on the substrate, a lightly doped region, an insulating layer and a main annular field plate. The drift layer has a plurality of n-type doped regions and a plurality of p-type doped regions, and the plurality of n-type doped regions and the plurality of p-type doped regions are alternately arranged to form a superjunction structure. The drift layer defines a component region and a terminal region surrounding the component region. The lightly doped region is located inside the drift layer and connected to the surface, and the lightly doped region has a first terminal portion close to the component region and a second terminal portion away from the component region. The insulating layer is disposed on the surface and at least covers the terminal region. The main annular field plate is disposed on the insulating layer, wherein the main annular field plate covers the second terminal portion.

Description

Superjunction Semiconductor Components

technical field

The present invention relates to a semiconductor component, and in particular to a metal-oxide-semiconductor field-effect transistor (MOSFET, referred to as “metal-oxide semiconductor field-effect transistor”) component with a superjunction structure.

Background technique

In super-junction transistor assemblies, the increase in on-resistance (Rds-on) is proportional to the increase in breakdown voltage (BV), which increases more slowly than in conventional semiconductor structures. Therefore, the superjunction transistor device can maintain a high breakdown voltage (breakdown voltage, BV) in an off state, and at the same time have a low on-resistance (R ds-on).

A superjunction transistor device typically has an active region and a termination region surrounding the active region. When the superjunction device is in the off state, there is an electric field distribution in both the vertical direction and the horizontal direction of the termination region.

In a conventional super junction transistor assembly, the top view shape of the p-type doped region in the terminal region is ring. However, when the p-type doped region is formed by an epitaxial process, a special lattice plane needs to be formed at the corner so that the p-type doped region has a better lattice arrangement at the corner. In this way, the difficulty of the manufacturing process will be increased. In addition, the impurity doping concentration at the corner is not easy to control, which may also reduce the withstand voltage of the super junction transistor device in the termination region.

Contents of the invention

The invention provides a super-junction semiconductor component. A plurality of p-type doped regions of the super-junction semiconductor component extend from the component region toward two opposite sides of the component region to the terminal region, and cooperate with the design of the annular field plate, so that The breakdown voltage of the superjunction semiconductor component in the off state (OFF-state) meets the requirements.

One embodiment of the present invention provides a superjunction semiconductor device, which includes a substrate, a drift layer, a lightly doped region, an insulating layer, and a main annular field plate. The drift layer is disposed on the substrate and has a surface opposite to the substrate, wherein a plurality of n-type doped regions and a plurality of p-type doped regions are formed in the drift layer, and the plurality of n-type doped regions and the plurality of p-type doped regions The doping regions extend from the surface toward the substrate and are arranged alternately to form a super junction structure. The drift layer defines a device area and a termination area surrounding the device area. The lightly doped region is located inside the drift layer and connected to the surface, and the lightly doped region has a first end close to the device region and a second end far away from the device region. The insulating layer is disposed on the surface to cover the terminal area. The main annular field plate is disposed on the insulating layer so that the main annular field plate covers the second end portion.

In summary, the super junction semiconductor component provided by the present invention can reduce the electric field intensity at the second end by making the main annular field plate cover the second end of the lightly doped region, thereby improving the super junction semiconductor The breakdown voltage of the module as a whole. In addition, in the super-junction semiconductor device according to the embodiment of the present invention, the plurality of p-type doped regions extend from the device region toward two opposite sides of the device region into the terminal region. Compared with conventional super junction transistor components, when these p-type doped regions are formed by epitaxy process, since the p-type doped regions do not have corners, the uniformity of epitaxy can be improved and the process complexity can be reduced .

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of a superjunction semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view along line II-II in FIG. 1 .

FIG. 3A is a schematic top view of a superjunction semiconductor device according to another embodiment of the present invention.

FIG. 3B is an enlarged view of area A in FIG. 3A.

FIG. 4 is a schematic cross-sectional view along line IV-IV in FIG. 3A.

FIG. 5 is a schematic partial top view of a superjunction semiconductor device according to another embodiment of the present invention.

FIG. 6 is a schematic top view of a superjunction semiconductor device according to another embodiment of the present invention.

Reference signs:

Super junction semiconductor components 1, 1 ', 3; Substrate 10; Upper surface 10a; Back side 10b;

Drift layer 11; surface 11a; insulating layer 12; main annular field plate 13, 13', 23;

The first straight section 13a, 13'a, 23a; The second straight section 13b, 13'b, 23b;

Turning portion 13c, 13'c, 23c; first end surface 131, 131'; second end surface 132, 132';

Length L, L1; Transistor structure 15; Assembly area A1; Termination area A2;

n-type doped regions 112, 113; second width W2; p-type doped regions 110, 111;

end portions 110a, 111a; first width W1; lightly doped region 114; first end portion 114a;

The second end portion 114b; the first direction D1; the second direction D2; the contact window h1;

Base region 150; source region 151; gate insulating layer 152; gate 153; dielectric layer 154;

source layer 155; end face 155e; predetermined distance d; sealing rings 16, 26, 36;

Auxiliary annular field plate 14, 24, 34a, 34b; first rectilinear portion 14a, 24a;

Second straight line portion 14b, 24b; turning portion 14c, 24c; width w

Detailed ways

1 and 2 are described below, wherein FIG. 1 is a schematic top view of a superjunction semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view along line II-II in FIG. 1 .

The superjunction semiconductor device 1 of the embodiment of the present invention includes a substrate 10 , a drift layer 11 , a lightly doped region 114 , an insulating layer 12 , a main annular field plate 13 and at least one transistor structure 15 .

In FIG. 2 , the substrate 10 is a semiconductor substrate and has an upper surface 10 a and a back surface 10 b opposite to the upper surface 10 a. The substrate 10 has a high concentration of impurities of the first conductivity type. The impurities of the first conductivity type can be distributed in a local area of the substrate 100 or distributed in the entire substrate 10 to be used as a drain contact layer. In this embodiment, the impurities of the first conductivity type are distributed throughout the substrate 10 , but this is only for example rather than limiting the present invention. Drain contact pads (not shown) are formed on the back surface 10 b of the substrate 10 to be electrically connected to an external control circuit.

The aforementioned impurities of the first conductivity type may be impurities of N-type or P-type conductivity. Assuming that the substrate 10 is a silicon substrate, the N-type conductive impurities are pentavalent element ions, such as phosphorus ions or arsenic ions, and the P-type conductive impurities are trivalent element ions, such as boron ions, aluminum ions or gallium ions.

A drift layer 11 is located on the upper surface 10 a of the substrate 10 and has a low concentration of impurities of the first type conductivity. In this embodiment, the substrate 10 is N-type doped with high concentration (N+), and the drift layer 11 is N-type doped with low concentration (N−). One side of the drift layer 11 is connected to the upper surface 10 a of the substrate 10 and has a surface 11 a opposite to the other side of the substrate 10 .

As shown in FIG. 1 and FIG. 2 , in this embodiment, the drift layer 11 defines a device area A1 and a termination area A2 surrounding the device area A1 . As shown in FIG. 1 , the device area A1 is located in the central area of the super-junction semiconductor device 1 , and the termination area A2 surrounds the device area A1 and is located in the peripheral area of the super-junction semiconductor device 1 .

Referring to FIG. 2 , the drift layer 11 has a plurality of n-type doped regions 112 , 113 and a plurality of p-type doped regions 110 , 111 . These n-type doped regions 112, 113 and p-type doped regions 110, 111 are juxtaposed alternately to form a super junction structure. In addition, the n-type doped regions 112 , 113 and the p-type doped regions 110 , 111 extend along the current flow direction, that is, extend from the surface 11 a of the drift layer 11 toward the substrate 10 .

Please refer to FIG. 1 , in the present embodiment, a part of the p-type doped region 110 extends from the device region A1 toward both sides of the device region A1 to the termination region A2 . That is to say, the middle part of each p-type doped region 110 is located in the device area A1, and the front part and the rear part are located in the termination area A2.

In addition, in the embodiment of FIG. 2, these p-type doped regions 110, 111 are columnar (pylon), and n-type doped regions 112, 113 are p-type doped regions 110 that are respectively staggered and surround these columns. , 111. Furthermore, a plurality of parallel trenches are firstly formed in the drift layer 11 , and then p-type epitaxial material is filled into these trenches to form the p-type doped regions 110 , 111 .

When the super junction semiconductor component 1 is in the on state (On state), these n-type doped regions 112, 113 and p-type doped regions 110, 111 can provide charges, and when the super junction semiconductor component 1 is in the off state (Off state), these n-type doped regions 112 , 113 and p-type doped regions 110 , 111 will be depleted (or depleted) in the horizontal direction, so as to achieve charge balance in the drift layer 11 . Therefore, the superjunction semiconductor device 1 can have a relatively high breakdown voltage with a relatively low on-resistance.

If the impurity doping concentration in the p-type doped regions 110 and 111 is not uniform, it is very likely that the charge in the drift layer 11 cannot be depleted, and the breakdown voltage of the superjunction semiconductor device 1 is reduced. Therefore, in the embodiment of the present invention, the p-type doped regions 110 and 111 are parallel to each other and arranged in the drift layer 11 , and each p-type doped region 110 and 111 does not have a turning section. When forming the p-type doped regions 110, 111, the p-type doped regions 110, 111 can be made to have a more uniform impurity doping concentration, thereby avoiding the breakdown of the withstand voltage of the superjunction semiconductor component 1 due to the p-type impurity doping concentration. unevenly reduced.

Since the p-type doped regions 110 and 111 are parallel to each other and arranged in the drift layer 11 , and each p-type doped region 110 and 111 does not have a turning section. Therefore, when filling the p-type epitaxial material to form these p-type doped regions 110, 111, there is no need to consider whether the lattice planes match, which can reduce the difficulty of the process and improve the epitaxy of the p-type doped regions 110, 111. crystal quality.

In the embodiment of the present invention, each p-type doped region 110, 111 has a first width W1 and a first concentration of p1, and each n-type doped region has a second width W2 and its concentration is n1. Furthermore, two adjacent p-type doped regions 110 and 111 are separated from each other by a predetermined distance, and the predetermined distance is the second width W2 of the n-type doped regions 112 and 113 . In one embodiment, the relationship between the first width W1 , the second width W2 , the first concentration p1 and the second concentration n1 satisfies the following relationship: p1*W1≒n1*W2.

It should be noted that the area of the termination region A2 will also affect the breakdown voltage of the superjunction semiconductor device 1 . Generally, the breakdown voltage increases with the area of the terminal region A2 increasing. In the embodiment shown in FIG. 2 , there are at least six sets of p-type doped regions 111 and n-type doped regions 113 in the terminal region A2, so as to extend the distribution range of the electric field, thereby improving the overall breakdown of the superjunction semiconductor device 1 Voltage.

Please refer to FIG. 2, in this embodiment, the drift layer 11 further has a lightly doped region 114 adjacent to the surface 11a of the drift layer 11 in the terminal region A2, and the lightly doped region 114 is connected to the p-type doped region 111 and 11 between surfaces. Further, the lightly doped region 114 is located on the side of the p-type doped region 111 close to the surface 11 a of the drift layer 11 and connected to the surface 11 a. In addition, the conductivity type of the lightly doped region 114 is opposite to that of the drift layer 11 . In this embodiment, the lightly doped region 114 extends from the device region A1 to the terminal region A2, and has a first end portion 114a located in the device region A1 and a second end portion 114b located in the terminal region A2.

The insulating layer 12 is disposed on the surface 11 a of the drift layer 11 to cover the terminal area A2 . In one embodiment, the insulating layer 12 is an oxide layer or a nitride layer. Referring to FIG. 1 and FIG. 2 , the main annular field plate 13 is disposed on the insulating layer 12 to extend the range of the electric field in the drift layer 11 and improve the withstand voltage of the superjunction semiconductor device 1 in the terminal region A2 . As shown in FIG. 1 , the main annular field plate 13 is located in the peripheral area of the super junction semiconductor device 1 and surrounds the central area of the super junction semiconductor device 1 .

Referring to FIG. 2 , in the embodiment of the present invention, the main annular field plate 13 covers the second end portion 114 b of the lightly doped region 114 such that the second end portion 114 b is located below the main annular field plate 13 . In detail, the main annular field plate 13 has a first end surface 131 close to the component area A1 and a second end surface 132 away from the component area A1 , wherein the first end surface 131 and the second end surface 132 are opposite to different sides. In this embodiment, the position of the main annular field plate 13 and the lightly doped region 114 at least partially overlap, and the main annular field plate 13 exceeds the second end portion 114b by a length L, that is, the second end of the main annular field plate 13 The distance between the end surface 132 and the second end portion 114 b of the lightly doped region 114 .

It should be noted that the simulation test results show that the location of the main annular field plate 13 and the length L extending beyond the second end portion 114 b will affect the breakdown voltage of the superjunction semiconductor device 1 . In this embodiment, the portion of the main annular field plate 13 extending beyond the second end portion 114 b covers at least two p-type doped regions 111 and an n-type doped region. That is to say, the length L, the first width W1 and the second width W2 satisfy the following relationship: a*(W1+W2)>L>(a*(W1+W2)-W2), where a is a positive integer. The main ring-shaped field plate 13 covers the second end portion 114b of the lightly doped region 114 , which helps to relax the electric field intensity originally concentrated on the second end portion 114b. This is to apply the field plate principle to expand the depletion region extending outward from the lightly doped region 114, so as to reduce the interface electric field intensity of the PN junction at the first end portion 114a and the second end portion 114b, so that the super junction semiconductor component A breakdown voltage of 1 meets the requirements.

Referring to FIG. 1 again, the p-type doped regions 110 , 111 extend along a first direction D1 on the surface 11 a. The plan view shape of the main annular field plate 13 has a first straight line segment 13a, a second straight line segment 13b and a turning portion 13c. The first straight line segment 13a is parallel to the first direction D1, and the second straight line segment 13b is roughly parallel to the second direction D2, wherein the first direction D1 is perpendicular to the second direction D2. That is to say, the second straight line segment 13b is substantially perpendicular to the first straight line segment 13a.

The turning portion 13c is connected between the first straight line segment 13a and the second straight line segment 13b, and is disposed corresponding to a corner of the component area A1. In the embodiment of the present invention, the turning portion 13c may be an arc turning portion or a right-angle turning portion, which is not limited in the present invention.

A plurality of transistor structures 15 are located in the device area A1 and include a body area 150 , a source area 151 , a gate insulating layer 152 , a gate 153 , a dielectric layer 154 and a source layer 155 .

The base region 150 has a conductivity type opposite to that of the substrate 10 and the drift layer 11 , and has the same conductivity type as the lightly doped region 114 . For example, if the substrate 10 and the drift layer 11 are n-type doped, both the base region 150 and the lightly doped region 114 are p-type doped. In one embodiment, the base region 150 and the lightly doped region 114 can be designed simultaneously Doped. Moreover, each base region 150 is connected to each p-type doped region 110 located in the component region A1. In detail, the base region 150 is connected to an end of the p-type doped region 110 close to the surface 11 a of the drift layer 11 .

At least one source region 151 is formed in each base region 150 , and the source region 151 has a conductivity type opposite to that of the base region 150 and has the same conductivity type as that of the drift layer 11 and the substrate 10 . In the embodiment shown in FIG. 2 , each base region 150 is provided with two source regions 151 separated from each other. Each source region 151 is isolated from each other by the base region 150 and the n-type doped region 112 in the device region A1 .

Both the gate insulating layer 152 and the gate 153 are disposed on the surface 11 a of the drift layer 11 , and the gate 153 is electrically insulated by the gate insulating layer 152 and the drift layer 11 . Further, in this embodiment, the gate 153 is disposed on the gate insulating layer 152 at a position corresponding to the n-type doped region 112 in the component region. In addition, the gate 153 partially overlaps the source region 151 located in the base region 150 .

The dielectric layer 154 covers the gate 153 and has a plurality of contact windows h1 (two are shown in FIG. 2 ). The plurality of contact windows h1 respectively correspond to positions of the body region 150 . That is to say, before the source layer 155 is formed, part of the source region 151 and part of the base region 150 will be exposed on the surface 11 a of the drift layer 11 through the contact window h1 .

The source layer 155 covers the dielectric layer 154 . The source layer 155 is electrically connected to each source region 151 through the contact window h1. In addition, the source layer 155 is electrically connected to the lightly doped region 114 located in the termination region A2.

It should be noted that the source layer 155 and the main annular field plate 13 are separated from each other, as shown in FIG. 2 . In detail, one end surface 155e of the source layer 155 is opposite to the first end surface 131 of the main annular field plate 13 and separated by a predetermined distance d, and the aforementioned predetermined distance d is at least greater than the first end surface 131 of one of the p-type doped regions 111. The width W1 is greater than the second width W2 of one of the n-type doped regions 113 . In one embodiment, the source layer 155 may be selected from one of the group consisting of titanium, platinum, tungsten, nickel, chromium, molybdenum, tin and metal silicides thereof.

In addition, the superjunction semiconductor device 1 of the present embodiment further includes a closed sealing ring 16 (closed seal ring) to surround the termination area A2 and the device area A1 . The sealing ring 16 can prevent the superjunction semiconductor component 1 from being damaged by the stress generated during cutting. In addition, the material of the sealing ring 16 is usually a conductive material (such as: metal) and can be electrically grounded, so as to avoid the static electricity generated during the cutting process from concentrating on the sealing ring 16 and causing electrostatic discharge (electrostatic discharge, ESD) to damage the superconnector. surface semiconductor components 1.

Please refer to FIG. 3A, FIG. 3B and FIG. 4, wherein FIG. 3A shows a schematic top view of a superjunction semiconductor component according to another embodiment of the present invention, FIG. 3B is an enlarged view of area A in FIG. 3A, and FIG. Schematic cross-section along line IV-IV. In the super-junction semiconductor component 1' of this embodiment and the super-junction semiconductor component 1 of the previous embodiment, the same components have the same reference numerals, and the same parts will not be repeated. In addition to the main annular field plate 13', the superjunction semiconductor component 1' of this embodiment also includes at least one auxiliary annular field plate 14 (multiple are shown in Fig. 3A).

Referring to FIG. 4 first, the main annular field plate 13' of this embodiment also covers the second end portion 114b of the lightly doped region 114 to reduce the electric field intensity of the second end portion 114b. In this embodiment, the length L1 of the main annular field plate 13 ′ protruding from the second end portion 114b is the shortest distance from the second end surface 131 ′ of the main annular field plate 13 ′ to the second end portion 114b, and p Between the first width W1 of the type doped regions 110 and 111, the following relationship is satisfied: (a*(W1+W2)>L1>(a*(W1+W2)-W2)), wherein L1 is the length , W1 is the first width, W2 is the second width, and a is a positive integer.

In the embodiment of the present invention, the width of the main annular field plate 13' is greater than that of any auxiliary annular field plate 14. In one embodiment, the auxiliary annular field plates 14 can be designed with the same width w, as shown in FIG. 4 . In addition, the materials constituting the main annular field plate 13' and the auxiliary annular field plate 14 are conductive materials, such as metal or heavily doped polysilicon. In addition, in the embodiment of the present invention, the main annular field plate 13' is floating.

Referring to FIG. 3A, the auxiliary annular field plate 14 is located outside the main annular field plate 13' and surrounds the main annular field plate 13'. Each auxiliary annular field plate 14 has a first straight portion 14a substantially parallel to the first direction D1, a second straight portion 14b substantially parallel to the second direction D2, and a second straight portion 14b connected to the first straight portion 14a and the second A turning portion 14c between the straight portions 14b.

As shown in FIG. 3B and FIG. 4 , the first straight portion 14 a covers a junction between two adjacent n-type doped regions 113 and p-type doped regions 111 . That is to say, the auxiliary annular field plate 14 straddles the n-type doped region 113 and alternates with the p-type doped region 111 . In addition, one end of the auxiliary annular field plate 14 closer to the device region A1 is a p-type doped region 111 , and the opposite end is an n-type doped region 113 . In other words, the inner edge of each auxiliary annular field plate 14 is located on the p-type doped region 111 , and the outer edge of each auxiliary annular field plate 14 is located on the n-type doped region 113 .

In one embodiment, the width w of the auxiliary annular field plate 14 (that is, the width of the first straight portion 14a), the width W1 of the p-type doped region 111, and the width W2 of the n-type doped region 113 satisfy the following relationship Formula: w≧0.5(W1+W2).

It should be noted that, near the surface 11 a and at the junction of the n-type doped region 113 and the p-type doped region 111 , there will be a larger electric field intensity. Therefore, the auxiliary annular field plate 14 covers the junction of the n-type doped region 113 and the p-type doped region 111, which helps to improve the concentration of the electric field at the junction of the n-type doped region 113 and the p-type doped region 111. phenomenon, and optimize the surface electric field distribution to increase the breakdown voltage of the superjunction semiconductor component 1'. Furthermore, applying the field plate principle, the depletion region extending outward from the lightly doped region can be extended to reduce the electric field intensity at the PN junction between the n-type doped region 113 and the p-type doped region 111 .

Referring to FIG. 3B , the turning portion 14 c of the auxiliary annular field plate 14 and the turning portion 13 c of the main annular field plate 13 are both arc-shaped. In this embodiment, the outermost auxiliary annular field plate 14 is wider than the other auxiliary annular field plates 14 , and the turning portion 14 c covers the end portion 111 a of each p-type doped region 111 . As shown in FIG. 3B, the connection formed between the ends 111a of each p-type doped region 111 is an arc line, and the turning portion 14c of the outermost auxiliary annular field plate 14 is in line with the aforementioned arc line. coincide.

In addition, please refer to FIG. 3A and FIG. 3B , similar to the embodiment in FIG. 1 , a part of the p-type doped region 110 extends outward from the device region A1 toward opposite sides of the device region A1 to the terminal region A2 . But in this embodiment, the two opposite end portions 110 a of each p-type doped region 110 are located below the outermost auxiliary annular field plate interior 14 . That is to say, the auxiliary annular field plate 14 located on the outermost side of the terminal region A2 covers two opposite ends of the p-type doped region 110 . In addition, it can also be seen from FIG. 3B that the outermost auxiliary annular field plate 14 also covers two opposite ends 111 a of another part of the p-type doped region 111 .

Please continue to refer to Figure 5. FIG. 5 is a schematic partial top view of a superjunction semiconductor device according to another embodiment of the present invention. In this embodiment, the main annular field plate 23 has a right-angled turning portion 23c. Similarly, the auxiliary annular field plate 24 also has a right-angled turning portion 24c. In addition, similar to the embodiment in FIG. 3B , the outermost auxiliary annular field plate 24 covers the ends 110 a , 111 a of each p-type doped region 110 , 111 . In this way, the depletion region extending outward from the lightly doped region 11 can be expanded to reduce the electric field intensity at the PN junctions at the ends 110 a , 111 a of the p-type doped regions 110 , 111 .

In other embodiments, the outermost auxiliary annular field plate does not have to cover the ends 110 a , 111 a of the p-type doped regions 110 , 111 . Please refer to FIG. 6 , which shows a schematic top view of a superjunction semiconductor device according to another embodiment of the present invention. In this embodiment, a plurality of auxiliary annular field plates 34a, 34b are sequentially disposed on the termination area A2 from inside to outside.

A plurality of p-type doped regions extend from the component region A1 to the outermost auxiliary annular field plate 34b of the termination region A2. That is to say, a part of the p-type doped regions 111 and 110 will extend beyond the range surrounded by the auxiliary annular field plate 34b. From the top view, the ends 110a, 111a of each p-type doped region 110, 111 are located between the sealing ring 36 and the outermost auxiliary annular field plate 34b.

To sum up, in the super-junction semiconductor device according to the embodiment of the present invention, a plurality of p-type doped regions straddle the device region and the terminal region. Compared with conventional superjunction transistor components, when these p-type doped regions are formed by epitaxy, since the p-type doped regions do not have arc corners, there is no need to consider whether the lattice planes match. It can reduce the process difficulty and improve the epitaxy quality. Secondly, when forming the p-type doped region, the p-type doped region can also have a more uniform impurity doping concentration, thereby avoiding the reduction of the withstand voltage of the superjunction semiconductor component due to the uneven p-type impurity doping concentration .

In addition, the superjunction semiconductor component provided by the present invention can improve the electric field distribution in the drift layer by cooperating with the main annular field plate and the auxiliary annular field plate, so that the overall breakdown voltage of the superjunction semiconductor component meets the requirements. Specifically, the main annular field plate covers the second end of the lightly doped region, which can reduce the electric field intensity at the second end, thereby increasing the overall breakdown voltage of the superjunction semiconductor component.

Although the embodiments of the present invention have been disclosed above, the present invention is not limited to the above embodiments, and anyone with ordinary knowledge in the technical field can make some changes without departing from the disclosed scope of the present invention. Therefore, all equivalent technical changes made by using the contents of the description and drawings of the present invention are included in the protection scope of the present invention.

Claims (12)

1. A super junction semiconductor component, characterized in that, the super junction semiconductor component comprises: a substrate; A drift layer is arranged on the substrate and has a surface opposite to the substrate, wherein the drift layer has a plurality of n-type doped regions and a plurality of p-type doped regions inside, and the plurality of n-type doped regions Type doped regions and a plurality of p-type doped regions extend from the surface toward the substrate and are alternately arranged to form a super junction structure, wherein the drift layer defines a device region and surrounds the a terminal area of the component area; at least one transistor structure located in the component region, wherein the transistor structure includes a source layer disposed on the drift layer; a lightly doped region, located inside the drift layer and connected to the surface, and the lightly doped region has a first end portion close to the component region and a second end portion away from the component region; an insulating layer disposed on the surface covering the termination area; and a main annular field plate disposed on the insulating layer such that the main annular field plate covers the second end portion, Wherein, the source layer is isolated from the main annular field plate and does not overlap up and down. 2. The superjunction semiconductor device as claimed in claim 1, wherein each of the p-type doped regions has a first width W1 and a first concentration p1, and each of the n-type doped regions has a first Two widths W2 and one second concentration n1 satisfy the following relationship: p1*W1≈n1*W2. 3. The super junction semiconductor device as claimed in claim 1, wherein the terminal region has at least six groups of p-type doped regions and n-type doped regions arranged alternately. 4. The super junction semiconductor device as claimed in claim 1, wherein said main annular field plate protrudes from said second end portion by a length L, and each of said p-type doped regions has a first width W1 , each n-type doped region has a second width W2, and satisfies the following relationship: a*(W1+W2)>L>(a*(W1+W2)-W2), where a is a positive integer . 5. The superjunction semiconductor device as claimed in claim 4, further comprising: at least one auxiliary annular field plate located in the termination region and surrounding the main annular field plate, wherein the width of the main annular field plate is greater than any a width of the auxiliary annular field plate. 6 . The superjunction semiconductor device as claimed in claim 5 , wherein the auxiliary annular field plates have the same width as w, which satisfies the following relationship: w≧0.5(W1+W2). 7. The superjunction semiconductor device as claimed in claim 5, wherein said auxiliary annular field plate is interleaved with said n-type doped region across said p-type doped region, wherein said auxiliary annular field plate is closer to One end of the component region is a p-type doped region, and the other end is an n-type doped region. 8 . The superjunction semiconductor device as claimed in claim 5 , wherein a plurality of the p-type doped regions extend from the device region to the inside of the outermost auxiliary annular field plate of the terminal region. 9. The super-junction semiconductor device as claimed in claim 5, wherein the p-type doped region extends from the device region to the outside of the auxiliary annular field plate at the outermost side of the termination region. 10. The superjunction semiconductor device according to claim 1, wherein the main annular field plate has an end face close to the device region, the end face is opposite to an end face of the source layer and is separated by a predetermined distance, And the predetermined distance is at least greater than a first width of the p-type doped region. 11. The superjunction semiconductor component as claimed in claim 1, wherein a plurality of said p-type doped regions have an extension direction substantially the same on said surface, and said main annular field plate has an extension direction equal to said extension direction. A first straight line segment parallel to the direction, a second straight line segment perpendicular to the extending direction, and a turning portion connected between the first straight line segment and the second straight line segment, wherein the turning portion is A curved turning portion or a right-angled turning portion. 12 . The superjunction semiconductor device as claimed in claim 1 , further comprising a sealing ring surrounding the periphery of the terminal area to avoid electrostatic discharge. 13 .