CN107293590B

CN107293590B - Fin field effect transistor and manufacturing method thereof

Info

Publication number: CN107293590B
Application number: CN201610227093.0A
Authority: CN
Inventors: 叶达勋; 罗正玮; 颜孝璁; 简育生
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2016-04-13
Filing date: 2016-04-13
Publication date: 2020-08-18
Anticipated expiration: 2036-04-13
Also published as: CN107293590A

Abstract

The invention discloses a fin field effect transistor and a manufacturing method thereof. The fin field effect transistor comprises a substrate, a fin structure, a gate stack structure and an isolation structure. The fin structure is disposed on the substrate and has a plurality of trenches, and the gate stack structure covers the fin structure. The isolation structure is configured on the substrate to isolate the grid stack structure from the substrate, wherein the isolation structure has different thicknesses. According to the fin field effect transistor and the manufacturing method thereof, the equivalent channel width of the fin field effect transistor can be finely adjusted by changing the thicknesses of the isolation structures in different areas, so that the fin field effect transistor and the manufacturing method thereof can be applied to different integrated circuit designs.

Description

Fin field effect transistor and manufacturing method thereof

Technical Field

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a fin field effect transistor and a method of fabricating the same.

Background

A conventional fin field effect transistor (FinFET) has a plurality of fins formed on a substrate, a gate layer covering two side walls and a top surface of each fin, and a gate dielectric layer between the gate layer and the fin. In addition, the fin is doped to form a source region and a drain region on opposite sides of the gate. When a bias is applied to the finfet, an inversion channel is formed on both sidewalls and top of the fin.

It should be noted that the equivalent channel width of the finfet is related to the height of the fin protruding from the Shallow Trench Isolation (STI), the thickness of the fin, and the number of fins.

Since the threshold current (threshold current) of a finfet is proportional to the channel width, designers typically vary the threshold current of a finfet by adjusting the equivalent channel width of the finfet based on the integrated circuit design requirements. However, based on process constraints, the designer can only adjust the equivalent channel width by increasing or decreasing the number of fins. In this case, the equivalent channel width of the finfet is difficult to be fine-tuned to meet the design requirements of the actual integrated circuit.

Disclosure of Invention

The invention provides a fin field effect transistor, which changes the height of a fin protruding from an isolation layer by changing the thickness of the isolation layer so as to finely adjust the effective channel width of the fin field effect transistor.

One embodiment of the present invention provides a fin field effect transistor, which includes a substrate, a fin structure, an isolation structure, and a gate stack structure. The fin structure is disposed on the substrate and has a plurality of trenches. The isolation structures are arranged on the substrate and in the trenches, and the isolation structures have different thicknesses. The gate stack structure covers the fin structure and the isolation structure.

Another embodiment of the present invention provides a method of fabricating a fin field effect transistor, comprising forming a fin structure on a substrate, wherein the fin structure has a plurality of trenches; forming an isolation structure disposed on the substrate and between the trenches, wherein the isolation structure has different thicknesses; and forming a gate stack structure to cover the fin structure and the isolation structure.

In summary, the fin field effect transistor and the method for manufacturing the same provided by the invention can be applied to different integrated circuit designs by changing the thicknesses of the isolation structures in different regions to finely adjust the equivalent channel width of the fin field effect transistor.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a partial perspective view of a finfet in accordance with an embodiment of the invention.

Fig. 1A illustrates a partial top view of the finfet of fig. 1.

Fig. 1B illustrates a cross-sectional view of the finfet of fig. 1.

Fig. 2 is a partial cross-sectional view of a finfet in accordance with another embodiment of the invention.

Fig. 3 is a partial cross-sectional view of a finfet in accordance with another embodiment of the invention.

Fig. 4 is a partial perspective view of a finfet in accordance with another embodiment of the invention.

Fig. 5 is a flow chart illustrating a method of fabricating a finfet in accordance with an embodiment of the present invention.

Fig. 6A to 6J are schematic partial cross-sectional views illustrating a finfet in various process steps according to an embodiment of the invention.

Fig. 7A-7F are schematic partial cross-sectional views of a finfet in accordance with another embodiment of the invention in various processing steps.

Description of reference numerals:

fin

field effect transistors

1, 1', 2

Substrates

10, 20

First element region A1

Second component area A2

Fin structures

11, 11', 21

Separating fins 110, 110'

Spacer fin top surface 110t

First side wall surface S1

Second side wall surface S2

Trench 213

First trenches 113, 113'

Second trenches 114, 114'

First fin 111

Second fin 112

First fin top surface 111t

Second fin top surface 112t

Fin 210

Fin top surface 210t

Source regions

111S, 110S, 112S

Drain

regions

111D, 110D, 112D

Isolation structures 12, 22

First isolation part 121

Isolation part 221

Front section 221a

Front section top surface 2210

Rear section 221b

Rear section top surface 2211

First spacer top surface 121s

Gate stack structures

13, 23

Gate stack bar 130

First gate stack bar 231

Second gate stack bar 232

The gate insulating layer 130a

The first gate insulating layer 231a

Second gate insulating layer 232a

Gate conductive layer 130b

First gate conductive layer 231b

Second gate conductive layer 232b

First stacking portion 131

Second stacking portion 132

Second isolation portion 122

Second separator top surface 122s

Reversing

channels

115a, 115b, 115c

First height H1, H1

Second height H2, H2

First thickness t1

Second thickness t2

Fin width T

First trench width w1

Second trench width w2

Front section thickness T1

Posterior segment partial thickness T2

Predetermined height difference d

Initial hard film layer 3

Hard film openings 30

Hard film layer 3'

A photoresist layer 4

Photoresist opening 40

Initial substrate 10'

Initial isolation material 12a

Spacer materials

12b, 12 b'

Mask pattern layer 5

Process steps S100, S102, S104

Detailed Description

Please refer to fig. 1, fig. 1A and fig. 1B. The finfet 1 of the present embodiment includes a substrate 10, a fin structure 11, an isolation structure 12, and a gate stack structure 13, wherein the fin structure 11 is disposed on the substrate 10, and the gate stack structure 13 covers the fin structure 11 and is isolated from the substrate 10 by the isolation structure 12. The fin field effect transistor 1 according to the embodiment of the invention can modulate the equivalent channel width according to the integrated circuit design, and can be applied to a ring oscillator or a memory element.

In the present embodiment, the substrate 10 is a semiconductor material, and may be silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), silicon carbide (SiC), indium phosphide (InP), zinc selenide (ZnSe), or other group VI, III-V, or II-VI semiconductor materials. The substrate 10 has a first type conductivity impurity, which may be an N-type or P-type conductivity impurity. The substrate 10 can be divided into at least a first device region a1 and a second device region a 2.

As shown in fig. 1, a fin structure 11 is disposed on a substrate 10. In detail, the fin structure 11 includes a plurality of first fins 111 located in the first element region a1, a plurality of second fins 112 located in the second element region a2, and a separation fin 110 located between the first element region a1 and the second element region a 2. The first fins 111, the second fins 112 and the separating fins 110 are disposed on the substrate 10 in parallel and have substantially the same extending direction.

Referring to fig. 1A, in the present embodiment, each of the first fins 111, the second fins 112 and the separating fins 110 is partially doped with a second conductive type impurity, so that at least one

source region

111S, 110S, 112S and at least one

drain region

111D, 110D, 112D are formed on each of the first fins 111, the second fins 112 and the separating fins 110, respectively. The

source regions

111S, 110S, 112S and the

drain regions

111D, 110D, 112D have opposite conductivity types to the substrate 10. In one embodiment, the

source regions

111S, 110S, 112S and the

drain regions

111D, 110D, 112D of each of the first fin 111, the second fin 112 and the separating fin 110 are electrically connected to a source contact pad and a drain contact pad, respectively, and then electrically connected to an external control circuit.

Referring to fig. 1 again, the partition fin 110 has a first sidewall S1 and a second sidewall S2 opposite to the first sidewall S1, wherein the first sidewall S1 is close to the first device region a1 and the second sidewall S2 is close to the second device region a 2.

In addition, in the present embodiment, the fin structure 11 further has a plurality of first trenches 113 located in the first device region a1 and a plurality of second trenches 114 located in the second device region a2, and the first trenches 113 and the second trenches 114 have the same width. In the embodiment of fig. 1, a first trench 113 is defined between the first fin 111, the separating fin 110 and the substrate 10, and a second trench 114 is defined between the second fin 112, the separating fin 110 and the substrate 10.

The isolation structure 12 is located in the first trench 113 and the second trench 114, wherein the isolation structure 12 has different thicknesses for isolating the gate stack 13 from the substrate 10. The isolation structure 12 is formed of a dielectric material, such as silicon oxide, silicon nitride, or other insulating material.

In detail, referring to fig. 1, the isolation structure 12 includes a first isolation portion 121 located in the first device region a1 and a second isolation portion 122 located in the second device region a 2. The first isolation portion 121 is located in the first trench 113, and the second isolation portion 122 is located in the second trench 114. As shown in fig. 1, the first sidewall surface S1 and the second sidewall surface S2 of the partition fin 110 are respectively connected to the first isolation portion 121 and the second isolation portion 122.

In addition, the first isolation portion 121 has a first thickness t1, and the second isolation portion 122 has a second thickness t2, wherein the first thickness t2 is less than the second thickness t 2. That is, the isolation structure 12 may have different thicknesses in the first element region a1 and in the second element region a 2.

Referring to fig. 1B, in the present embodiment, the minimum distance between the top surface 110t of the spacer fin 110 and the top surface 121s of the first isolation portion 121 is the first height h1 at which the first fin 111 protrudes from the top surface 121s of the first isolation portion 121. In addition, the minimum distance between the top surface 110t of the spacer fin 110 and the top surface 122s of the second spacer 122 is the second height h2 at which the second fin 112 protrudes from the top surface 122s of the second spacer 122.

As can be seen in fig. 1B, the minimum distance h1 between the top surface 110t of the spacer fin 110 and the top surface 121s of the first spacer 121 is greater than the minimum distance h2 between the top surface 110t of the spacer fin 110 and the top surface 122s of the second spacer 122. Therefore, the first height h1 is greater than the second height h 2.

Referring to fig. 1 again, the gate stack structure 13 covers the fin structure 11 and the isolation structure 12, and can be electrically connected to an external control circuit. When the gate stack structure 13 is biased, an inversion channel may be created within the fin structure 11.

In detail, the gate stack structure 13 includes a plurality of gate stack bars 130 (1 is shown in fig. 1 as an example), and an extending direction of each gate stack bar 130 is staggered with an extending direction of the first fin 111, the second fin 112 and the separating fin 110. In one embodiment, the extending direction of each gate stack stripe 130 is substantially perpendicular to the extending direction of the first fin 111, the second fin 112 and the separating fin 110.

Referring to fig. 1, in the present embodiment, the gate stack stripe 130 extends from the first device region a1 to the second device region a 2. In detail, the gate stack stripe 130 surrounds two sidewalls and the top surface 111t of each first fin 111, two sidewalls and the top surface 112t of each second fin 112, and the first and second sidewalls S1, S2 and the top surface 110t of the separation fin 110. In addition, the gate stack bar 130 covers the

top surfaces

121s and 122s of the first and

second isolation portions

121 and 122.

Each gate stack stripe 130 includes a gate insulating layer 130a and a gate conductive layer 130b, wherein the gate insulating layer 130a is located between the gate conductive layer 130b and the first fin 111, the second fin 112 and the separating fin 110. The gate insulating layer 130a may be a high dielectric constant dielectric material, such as Ta₂O₅、HfSiO、HfSiON、HfO₂、ZrO₂ZrSiO, ZrSiON, TaSiO, etc. The gate conductive layer 130b is formed on the gate insulating layer 130a, and may be a conductive material such as heavily doped polysilicon, metal silicide, etc.

Referring to fig. 1A, the gate stack stripe 130 is located between the first fin 111, the second fin 112 and the

source regions

111S, 110S, 112S and the

drain regions

111D, 110D, 112D of the separation fin 110.

Referring to fig. 1A and 1B, when the gate stack bar 130, the

source regions

111S, 110S, and 112S, and the

drain regions

111D, 110D, and 112D are biased, the first fin 111, the second fin 112, and the portion of the spacer fin 110 surrounded by the gate stack bar 130 generate inversion channels (inversion channels) 115a to 115 c.

As can be seen from fig. 1B, the width W of the inverted channel of each first fin 111_eff1Equal to twice the first height h1 plus the width T of the first fin 111, i.e., W_eff12h1+ T. Similarly, the width W of the inverted channel of each second fin 112_eff2At twice the second height h2 plus the width T of the second fin 112, i.e., W_eff22h2+ T. Similarly, the width W of the inverted channel created in the spacer fin 110_eff0＝h1+h2+T。

As mentioned above, the first height h1 (or the second height h2) is positively correlated with the width of the inverted channel of each of the first fins 111 (or the second fins 112), and the first height h1 is greater than the second height h2, so that the width W of the inverted channel of each of the first fins 111 is greater than the second height h2_eff1Is greater than the width W of the inverted channel of each second fin 112_eff2。

In other embodiments, the second thickness t2 of the second isolation portion 122 may also be less thanThe first thickness t1 of the first spacer 121, thereby making the width W of the inverted channel of the first fin 111_eff1Is smaller than the width W of the reversal channel of the second fin 112_eff2. Therefore, by adjusting the thickness of the isolation structure 12 in different device regions, the equivalent channel width of the finfet 1 can be fine-tuned to adapt to different integrated circuit designs.

Referring to fig. 2, a finfet 1 ' according to another embodiment of the present invention is different from the finfet 1 of fig. 1 in that the separation fin 110 ' of the finfet 1 ' is a dummy fin. That is, only the

source regions

111S, 112S and the

drain regions

111D, 112D of the first fin 111 and the second fin 112 are electrically connected to the external control line, and the source region 110S and the drain region 110D of the separation fin 110 are not electrically connected to the external control line.

In addition, in this case, the gate stack bar 130 may have a first stack portion 131 covering the at least one first fin 111 and a second stack portion 132 covering the at least one second fin 112. The first stacking portion 131 and the second stacking portion 132 are separated from each other to expose the gate insulating layer 130a on the top surface 110t of the spacer fin 110'. Therefore, when the finfet 1' is biased, the

inversion channels

115a and 115b are formed only in the first fin 111 and the second fin 112, but not in the spacer fin 110. In another embodiment, the

source regions

111S and 112S and the

drain regions

111D and 112D may be formed only in the first fin 111 and the second fin 112, and the source region 110S and the drain region 110D are not formed in the spacer fin 110.

Please refer to fig. 3. The finfet 1 ″ of fig. 3 differs from the finfet 1 ' of fig. 1 in that the first trench 113 ' and the second trench 114 ' have different widths, respectively. In the embodiment of fig. 3, the width w1 of the first trench 113 'is greater than the width w2 of the second trench 114'. In addition, the thickness t1 of the first isolation portion 121 in the first trench 113 'is smaller than the thickness t2 of the second isolation portion 122 in the second trench 114', and the width W of the inverted channel of the first fin 111_eff1Greater than the width W of the reversal path of the second fin 112_eff2。

Referring to fig. 4, a finfet 2 according to another embodiment of the invention is shown. In the present embodiment, the finfet 2 includes a substrate 20, a fin structure 21, an isolation structure 22, and a gate stack structure 23.

The fin structure 21 also includes a plurality of fins 210 having the same extension direction and disposed in parallel on the substrate 20, and a plurality of trenches 213, wherein the trenches 213 are respectively located between any two adjacent fins 210. In addition, the isolation structure 22 includes a plurality of isolation portions 221, and the isolation portions 221 are respectively disposed in the trenches 213. Therefore, the sidewall surface of each fin 210 is connected to at least one spacer 221.

As shown in fig. 4, each of the isolation portions 221 is divided into a front portion 221a and a rear portion 221b connected to the front portion 221a along the extending direction of the trench 213 (or the fin 210), and a predetermined height difference d is formed between the front portion 221a and the rear portion 221 b. In detail, in the present embodiment, the thickness T1 of the front section 221a with respect to the substrate 20 is smaller than the thickness T2 of the rear section 221b with respect to the substrate 20, so that the front section 221a and the rear section 221b have a predetermined height difference d therebetween.

Therefore, the minimum distance between the top surface 210t of the fin 210 and the top surface 2210 of the front section 221a is greater than the minimum distance between the top surface 210t of the fin 210 and the top surface 2211 of the rear section 221 b. That is, for the same fin 210, a first height H1 of the fin 210 protruding from the front section 221a is greater than a second height H2 of the fin 210 protruding from the rear section 221 b.

In addition, the gate stack structure 23 of the present embodiment includes a first gate stack stripe 231 and a second gate stack stripe 232 covering the fin 210, wherein the extending directions of the first and second

gate stack stripes

231, 232 and the extending direction of the fin 210 are staggered. In addition, the first gate stack stripe 231 has a first gate insulating layer 231a and a first gate conductive layer 231b on the first gate insulating layer 231 a. Similarly, the second gate stack stripe 232 has a second gate insulating layer 232a and a second gate conductive layer 232b on the second gate insulating layer 232 a.

In the present embodiment, the first gate stack stripe 231 covers the front portion 221a of the at least one isolation portion 221, and the second gate stack stripe 232 covers the rear portion 221b of the at least one isolation portion 221.

That is, when the finfet 2 is biased, the width of the inversion channel generated at the overlapping portion of the fin 210 and the first gate stack stripe 231 is greater than the width of the inversion channel generated at the overlapping portion of the fin 210 and the second gate stack stripe 232. That is, the equivalent channel width of the finfet 2 can be adjusted by adjusting the thickness of the isolation portion 221 in the same trench 213 in different regions.

Referring to fig. 5, a method for fabricating a finfet is provided. In step S100, a fin structure having a plurality of trenches is formed on a substrate. In step S102, an isolation structure disposed on the substrate and between the trenches is formed, wherein the isolation structure has different thicknesses. Next, in step S104, a gate stack structure is formed to cover the fin structure and the isolation structure.

Next, referring to fig. 6A to 6J, a manufacturing method for forming the field effect transistor 1 shown in fig. 1 is further described. Referring to fig. 6A to 6C, a detailed flow of step S100 of fig. 5 is shown. As shown in fig. 6A, an initial hard film layer 3 is formed on an initial substrate 10', and a photoresist layer 4 is formed on the initial hard film layer 3, wherein the photoresist layer 4 has a plurality of photoresist openings 40 to define a plurality of trench locations.

Referring to fig. 6B, the initial hard film layer 3 is etched through the photoresist layer 4 to form a hard film layer 3' having a plurality of hard film openings 30, wherein the plurality of hard film openings 30 are respectively connected to the plurality of photoresist openings 40. Next, as shown in fig. 6C, the initial substrate 10 'is continuously etched through the photoresist layer 4 and the hard film layer 3' to form a substrate 10 and a fin structure 11 having a plurality of trenches on the substrate 10. Then, the photoresist layer 4 is removed.

In one embodiment, the step of etching the initial substrate 10 'through the photoresist layer 4 and the hard film layer 3' to form the fin structure 11 having a plurality of trenches may be performed by a dry etching or wet etching process.

In one embodiment, the wet etching solution may include tetramethylammonium hydroxide (TMAH), Hydrogen Fluoride (HF)/nitric acid (HNO 3)/acetic acid (CH 3COOH), and ammonium hydroxide (NH)₄OH), potassium hydroxide (KOH), combinations of the above materials, or other suitable wet etching solutions. The dry etching process includes a bias plasma etching process using chlorine-based chemistry, and the dry etching gas may include carbon tetrafluoride (CF 4), nitrogen trifluoride (NF 3), sulfur hexafluoride (SF 6), and helium (He). The dry etching may be performed in an anisotropic method using a mechanism such as deep reactive-ion etching (DRIE).

In addition, at least a first device region a1 and a second device region a2 are defined on the substrate 10, wherein a portion of the trench in the first device region a1 is defined as a first trench 113, and another portion of the trench in the second device region a2 is defined as a second trench 114. The fin structure 11 has a plurality of first fins 111 located in the first element region a1, a plurality of second fins 112 located in the second element region a2, and at least one spacer fin 110 located between the first element region a1 and the second element region a 2.

Referring to fig. 6D to 6E, a detailed flow of step S102 in fig. 5 is shown. As shown in fig. 6D, an initial isolation material 12a is formed to fill the trenches (including the first and second trenches 113, 114) and the hard film openings 30 communicating with the trenches and cover the fin structures 11. The initial isolation material is an insulating material and may be formed by physical or chemical vapor deposition. Referring to fig. 6E, a portion of the initial isolation material 12a is removed to expose the top surface of the hard film layer 3'.

Next, a two-stage etching process is used to etch the isolation material 12b in the first trench 113 and the second trench 114. As shown in fig. 6F, a mask pattern layer 5 is formed to cover the isolation material 12b in the second element region a2 and expose the isolation material 12b in the first element region a 1. Next, as shown in fig. 6G, a first etching step is performed through the mask pattern layer 5 to remove a portion of the isolation material 12b located in the first device region a1, so that the thickness of the isolation material 12b in the second device region a2 is greater than the thickness of the isolation material 12 b' in the first device region a 1.

Referring to fig. 6H and 6I, after removing the mask pattern layer 5, a second etching step is performed to simultaneously remove a portion of the isolation material 12 b' located in the first device region a1 and a portion of the isolation material 12b located in the second device region a2, so as to form the isolation structure 12.

The isolation structure 12 has a first isolation portion 121 and a second isolation portion 122 located in the first element region a1 and the second element region a2, and the first isolation portion 121 and the second isolation portion 122 have different thicknesses. Next, referring to fig. 6J, a gate insulating layer 130a and a gate conductive layer 130b are sequentially formed to cover the fin structure 11, so as to form the finfet 1 shown in fig. 1.

It should be noted that, by changing the pattern of the mask pattern layer 5 in fig. 6F, the thickness of the isolation portion in the same trench can be different between the front portion and the back portion. Therefore, the above-described manufacturing method can also be applied to manufacture the finfet 2 shown in fig. 4.

Next, please refer to fig. 7A to 7F. A method of fabricating a finfet in accordance with another embodiment of the present invention will be described with reference to the formation of the finfet 1 ″ shown in fig. 3.

Referring to fig. 7A, similar to fig. 6C, a fin structure 11 'is formed on a substrate 10, and the fin structure 11' has a plurality of trenches with different widths. In detail, the substrate 10 is divided into a first device region a1 and a second device region a2, wherein a portion of the trench in the first device region a1 is defined as a first trench 113 ', another portion of the trench in the second device region a2 is defined as a second trench 114', and the first trench 113 'and the second trench 114' have different widths, respectively. Fin structure 11' has a plurality of first fins 111 located within first element region a1, a plurality of second fins 112 located within second element region a2, and at least one spacer fin 110 located between first element region a1 and second element region a 2. The hard film layer 3' remains on each of the first fin 111, the second fin 112 and the separating fin 110.

Referring to fig. 7B to 7E, a detailed flow of step S102 in fig. 5 according to another embodiment is shown. As shown in fig. 7B, the initial isolation material 12a is formed to fill the trenches (including the first and second trenches 113 ', 114 ') and the hardmask film openings 30 in communication with the trenches, and to cover the fin structures 11 '. Referring to fig. 7C, a portion of the initial isolation material 12a is removed to expose the top surface of the hard film layer 3'.

Next, referring to fig. 7D and 7E, the isolation materials 12 b' and 12b in the first trench 113 and the second trench 114 are etched at different etching rates to form the isolation structure 12. The isolation structure 12 includes a first isolation portion 121 and a second isolation portion 122, wherein the first isolation portion 121 and the second isolation portion 122 are formed with different thicknesses by different etching rates.

In this step, the isolation materials 12b ', 12b in the first trench 113 ' and the second trench 114 ' are removed directly by a wet etching process without using any photoresist layer or mask pattern layer. In the wet etching process, since the width w1 of the first trench 113 ' is greater than the width w2 of the second trench 114 ', the contact area between the isolation material 12b ' in the first trench 113 ' and the etching solution is greater than the contact area between the isolation material 12b in the second trench 114 ' and the etching solution. Therefore, the etching rate of the isolation material 12b 'in the first trench 113' is greater than that of the isolation material 12b in the second trench 114 ', so that a thinner first isolation portion 121 and a thicker second isolation portion 122 are formed in the first trench 113' and the second trench 114, respectively.

It should be noted that, although wet etching is taken as an example in the embodiment, in other embodiments, dry etching may be used in combination with the mask pattern layer to achieve the same technical effect.

Next, referring to fig. 7E and 7F, after removing the hard film layer 3 ', a gate stack structure 13 is formed to cover the fin structure 11' and the substrate 10. The details of forming the gate stack structure 13 are similar to those of fig. 6J, and are not repeated herein.

In summary, the fin field effect transistor and the method for manufacturing the same provided by the invention adjust the width of the inversion channel of the fin by making the isolation structure have different thicknesses in different regions. Therefore, the equivalent channel width of the finfet in the embodiments of the present invention can be adjusted according to the design of the actual integrated circuit.

Although the present invention has been described with reference to the above embodiments, it should be understood that the scope of the present invention is not limited to the above embodiments, and those skilled in the art can make various changes and modifications without departing from the scope of the present invention.

Claims

1. A fin field effect transistor, comprising:

a substrate;

a fin structure disposed on the substrate, wherein the fin structure has a plurality of trenches;

an isolation structure disposed on the substrate and within the plurality of trenches, wherein the isolation structure has different thicknesses; and

a gate stack structure covering the fin structure and the isolation structure;

the isolation structure comprises a plurality of isolation parts, wherein the isolation parts are respectively positioned in the ditches, each isolation part is divided into a front section part and a rear section part connected with the front section part along the extending direction of the ditch, and a preset height difference is formed between the front section part and the rear section part.

2. The finfet of claim 1, wherein the substrate is divided into a first device region and a second device region, the isolation structure comprises a first isolation portion in the first device region and a second isolation portion in the second device region, and the first isolation portion and the second isolation portion have different thicknesses.

3. The finfet of claim 2, wherein the fin structure comprises at least one first fin in the first device region, at least one second fin in the second device region, and a spacer fin between the first and second device regions, opposite sidewalls of the spacer fin respectively connecting the first and second spacers, the first spacer having a thickness relative to the substrate that is less than a thickness of the second spacer relative to the substrate.

4. The fin-type field effect transistor of claim 3, wherein a minimum distance between the top surface of the spacer fin and the top surface of the first isolation portion is greater than a minimum distance between the top surface of the spacer fin and the top surface of the second isolation portion.

5. The FinFET of claim 3, wherein one of the trenches is a first trench formed between at least one of the first fins and the spacer fin and the other of the trenches is a second trench formed between at least one of the second fins and the spacer fin, the first trench having a width greater than a width of the second trench.

6. The FinFET of claim 3, wherein the gate stack structure comprises a plurality of gate stack strips extending in a direction that is staggered with respect to the extension of at least one of the first fin, the second fin, and the spacer fin, wherein a gate stack strip comprises a first stack portion covering at least one of the first fins and a second stack portion covering at least one of the second fins, the first stack portion and the second stack portion being separated from each other to expose the top surface of the spacer fin.

7. The FinFET of claim 3 or 6, wherein the first fin and the second fin are electrically connected to an external control circuit, and the spacer fin is not electrically connected to the external control circuit.

8. A method of fabricating a fin field effect transistor, comprising:

forming a fin structure on a substrate, wherein the fin structure has a plurality of trenches;

forming an isolation structure disposed on the substrate and between the trenches, wherein the isolation structure has different thicknesses; and

forming a gate stack structure to cover the fin structure and the isolation structure;

9. The method of manufacturing a fin field effect transistor as recited in claim 8, wherein forming the fin structure further comprises:

forming an initial hard film layer on an initial substrate;

forming a photoresist layer on the initial hard film layer, wherein the photoresist layer has a plurality of photoresist openings to define the positions of a plurality of trenches;

etching the initial hard film layer through the light resistance layer to form a hard film layer with a plurality of hard film openings, wherein the hard film openings are respectively communicated with the light resistance openings;

etching the initial substrate through the photoresist layer and the hard film layer to form the fin structure with a plurality of trenches; and

removing the photoresist layer.