CN108461402A - The preparation method of fin transistor - Google Patents
The preparation method of fin transistor Download PDFInfo
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- CN108461402A CN108461402A CN201810330520.7A CN201810330520A CN108461402A CN 108461402 A CN108461402 A CN 108461402A CN 201810330520 A CN201810330520 A CN 201810330520A CN 108461402 A CN108461402 A CN 108461402A
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- China
- Prior art keywords
- fin
- area
- height
- transistor
- silicide layer
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- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 58
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of preparation methods of fin transistor, are related to ic manufacturing technology, and the manufacturing method of the fin transistor includes：Step 110 provides an original fin transistor, and the original fin transistor includes at least a first area and a second area, includes at least one first fin on the first area, includes at least one second fin on the second area；Step 120, in described one layer of silicide layer of original fin transistor disposed thereon；Step 130, first time etching technics is carried out, makes to form a step between the first area and the second area；And step 140, second of etching technics is carried out, so that the height of first fin is different from the height of the second fin；To obtain the high fin transistor of different fins, meet demand of the integrated circuit to the transistor of different characteristics.
Description
Technical field
The present invention relates to the preparations of a kind of ic manufacturing technology more particularly to a kind of high fin transistor of different fins
Method.
Background technology
With the development of ic manufacturing technology, the process node of integrated circuit constantly reduces, semiconductor technology feature
Size constantly reduces, and traditional Planar transistors can no longer meet demand, fin transistor (such as fin field effect crystal
Pipe) it is given birth to because of fortune, and be used widely.
In addition, with the raising that integrated circuit requires integrated level, need to integrate multiple fin crystal on one substrate
Pipe, however, integrated circuit is often different to the performance requirement of different crystal pipe, such as transistor driving current, these parameters
It is usually related with the fin height of fin transistor.
Therefore in integrated circuit fabrication, need to manufacture the high transistor of different fins, to meet the crystal to different characteristics
The demand of pipe.
Invention content
The purpose of the present invention is to provide a kind of preparation methods of fin transistor, to obtain the high fin crystal of different fins
Pipe, meets demand of the integrated circuit to the transistor of different characteristics.
The preparation method of fin transistor provided by the invention, including：Step 110, an original fin transistor is provided, it is former
Beginning fin transistor includes at least a first area and a second area, includes at least one first fin on first area, and second
It include at least one second fin on region；Step 120, in one layer of silicide layer of original fin transistor disposed thereon；Step
130, first time etching technics is carried out, makes to form a step and step 140 between first area and second area, carries out the
Secondarily etched technique, so that the height of the first fin is different from the height of the second fin.
Further, step 130 further includes step 1301, forms photoresist on silicide layer, removes second later
The photoresist on silicide layer on region, and carried out for the first time by mask of the photoresist on the silicide layer on first area
Etching technics.
Further, step 130 further includes step 1302, after completing first time etching technics, removes on first area
Silicide layer on photoresist.
Further, step is a step declined.
Further, the height of the second fin is more than the height of the first fin.
Further, the height of the second fin is equal to the height of step with the difference in height of the first fin.
Further, original fin transistor further includes substrate, between the first fin, between the second fin and the first fin with
Between second fin, and there are silicide isolated area, the material identical of silicide isolated area and silicide layer in substrate deposition.
Further, silicide layer and the material of silicide isolated area are silica.
Further, original fin transistor further includes substrate, between the first fin, between the second fin and the first fin with
Between second fin, and it is the bottom of the substrate of first area to have silicide isolated area, the height of step in substrate deposition
To the height and second area at the top of the silicide layer of first area substrate bottom to second area silicide layer
The difference of the height at top.
Further, original fin transistor further includes substrate, between the first fin, between the second fin and the first fin with
Between second fin, and it is the bottom of the substrate of first area to have silicide isolated area, the height of step in substrate deposition
Silicide to bottom to the second area of the substrate of the height and second area at the top of the silicide layer of first area is isolated
The difference of the height at the top in area.
The preparation method of fin transistor provided by the invention, by the one layer of silication of original fin transistor disposed thereon
Nitride layer, and the fin transistor for having different fins high is obtained by twice etching technique, integrated circuit is met to different characteristics
Transistor demand.
Description of the drawings
Fig. 1 is the preparation method flow chart for the fin transistor for inventing an embodiment.
Fig. 2 to Fig. 5 is the schematic diagram of the preparation process of the fin transistor of one embodiment of the invention.
The reference numerals are as follows for main element in figure：
230, first area；240, second area；232, the first fin；242, the second fin；260, step；250, silicide
Layer；220, silicide isolated area；210, substrate.
Specific implementation mode
Referring to Fig. 1, Fig. 1 is the preparation method flow chart for the fin transistor for inventing an embodiment.And please refer to Fig. 2 extremely
Fig. 5, Fig. 2 to Fig. 5 be one embodiment of the invention fin transistor preparation process schematic diagram.The fin transistor of the present invention
Preparation method include：Step 110, an original fin transistor 200 is provided, a first area 230 and one second is included at least
Region 240 includes at least one first fin 232 on first area 230, includes at least one second fin 242 on second area；Step
Rapid 120, in original fin transistor 200 disposed thereon, one layer of silicide layer 250；Step 130, first time etching technics is carried out,
Make to form a step 260 between first area 230 and second area 240；Step 140, second of etching technics is carried out, so that the
The height of first fin 232 in one region 230 is different from the height of the second fin 242 of second area 240.
In this way, by original fin transistor 200 disposed thereon, one layer of silicide layer 250, and pass through twice etching work
Skill obtains the fin transistor for having different fins high, meets demand of the integrated circuit to the transistor of different characteristics.
Specifically, referring to Fig. 2, the original fin transistor 200 that step 110 provides, further includes substrate 210, the first fin
Between 232, between the second fin 242 and between the first fin 232 and the second fin 242, and deposition has silication on substrate 210
Object isolated area 220, the silicide isolated area 220 between substrate 210,232 and first fin 232 of at least one first fin constitute the firstth area
Domain 230；Silicide isolated area 220 between substrate 210,242 and first fin 242 of at least one second fin constitutes second area 240.
Certainly, in an embodiment of the present invention, it more may include that third region, third region include an at least third fin, the present invention is to original
The areal of beginning fin transistor does not limit.In the present embodiment, the first fin 232 and the second fin 242 include three,
Certainly the present invention does not limit the number of fin, as long as each region includes at least one fin.
Specifically, refering to Fig. 3, step 120, in original fin transistor 200 disposed thereon, one layer of silicide layer 250, more
Specifically, silicide layer 250 is formed by depositing technics, such as chemical vapor deposition or physical vapor deposition, the present invention is to deposition
The concrete technology of silicide layer 250 does not limit.
Specifically, refering to Fig. 4 A, step 130, first time etching technics is carried out, first area 230 and second area 240 are made
Between form a step 260, i.e., between first area 230 and second area 240 have a difference in height.More specifically, including step
Rapid 1301, photoresist (not shown) is formed on silicide layer 250, removes the silicide layer on second area 240 later
Photoresist (as removed using photoetching development mode) on 250, and with the photoetching on the silicide layer 250 on first area 230
Glue is that mask carries out first time etching technics.To make the first area 230 and the secondth area of fin transistor after etching for the first time
The step 260 of decline, the i.e. silication of bottom 211 to the first area 230 of the substrate 210 of first area 230 are formed between domain 240
The height H1 at the top 251 of nitride layer 250 is more than the bottom 211 of the substrate 210 of second area 240 to the silication of second area 240
The height H2 at the top 252 of nitride layer 250, the height H3 of step 260 are the bottom 211 of the substrate 210 of first area 230 to
The bottom 211 to the second of the height H1 at the top 251 of the silicide layer 250 in one region 230 and the substrate 210 of second area 240
The difference of the height H2 at the top 252 of the silicide layer 250 in region 240, i.e. H3=H1-H2.As shown in Figure 4 A, it is carved by first time
Still there are one layer of silicide layer 250, i.e. the second fin 242 not to expose after etching technique, on second area 240, i.e. the height H3 of step
Less than the height of silicide layer 250, but present invention comparison does not limit；As shown in Figure 4 B, after by first time etching technics,
Second fin 242 exposes, and the height H3 of step is more than the height of silicide layer 250, i.e. H2 is the substrate 210 of second area 240
The height at bottom 211 to the top 222 of the silicide isolated area 220 of second area 240.More specifically, step 130 further includes step
Rapid 1302, after completing first time etching technics, remove the photoresist on the silicide layer 250 on first area 230.The present invention couple
The size of the height H3 of step does not limit, and the height H3 of step can be configured according to the property requirements of transistor, and be led to
The parameter of adjustment first time etching technics is crossed to reach.And the present invention does not limit first time etching technics, in the art
Dry etch process and wet-etching technology be suitable for the present invention.
Specifically, refering to Fig. 5, step 140, second of etching technics is carried out, so that the first fin 232 of first area 230
Height it is different from the height of the second fin 242 of second area 240.More specifically, the height of the first fin 232 of fin transistor
H4 is less than the height H5 of the second fin 242, wherein the height H4 of the first fin 232 is the silicide isolated area in first area 230
The height at the top 2321 of 220 223 to the first fin 232 of top, the height H5 of the second fin 242 are the silicon in second area 240
The height at the top 2421 of 222 to the second fin 242 of top of compound isolated area 220.In an embodiment of the present invention, silicide layer
250 and silicide isolated area 220 material identical, be such as silica, such silicide layer 250 and silicide isolated area
The difference in height of the height H4 of 220 etching speeds having the same, the height H5 of the second fin 242 and the first fin 232 is equal to step 260
Height H3.In this way, can the high transistor of different fins only be formed by the setting to first time etch process parameters, meet
Demand of the integrated circuit to the transistor of different characteristics.
The technique for forming and removing photoresist (not shown) in the present embodiment, in step 1301 and step 1302 exists
It is handled on silicide layer 250, namely forms photoresist and do not pollute fin with the technique for removing photoresist, therefore improve transistor
Performance.
Certainly, the relative terms such as " top " mentioned above, " top " and " bottom " are only used for orientation shown in the drawings, this
A little directional terminologies are merely for convenience of describing, without requiring with specific azimuth configuration or operating device.
In conclusion by one layer of silicide layer of original fin transistor disposed thereon, and pass through twice etching technique
The fin transistor for having different fins high is obtained, demand of the integrated circuit to the transistor of different characteristics is met.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (10)
1. a kind of preparation method of fin transistor, which is characterized in that including：
Step 110, an original fin transistor is provided, the original fin transistor includes at least a first area and one second
Region includes at least one first fin on the first area, includes at least one second fin on the second area；
Step 120, in described one layer of silicide layer of original fin transistor disposed thereon；
Step 130, first time etching technics is carried out, makes to form a step between the first area and the second area；With
And
Step 140, second of etching technics is carried out, so that the height of first fin is different from the height of the second fin.
2. the preparation method of fin transistor according to claim 1, which is characterized in that step 130 further includes step
1301, photoresist is formed on the silicide layer, removes the photoetching on the silicide layer on the second area later
Glue, and carry out the first time etching technics by mask of the photoresist on the silicide layer on the first area.
3. the preparation method of fin transistor according to claim 2, which is characterized in that step 130 further includes step
1302, after completing the first time etching technics, remove the photoresist on the silicide layer on the first area.
4. the preparation method of fin transistor according to claim 2, which is characterized in that the step is a platform declined
Rank.
5. the preparation method of fin transistor according to claim 4, which is characterized in that the height of second fin is more than
The height of first fin.
6. the preparation method of fin transistor according to claim 5, which is characterized in that the height of second fin and institute
The difference in height for stating the first fin is equal to the height of the step.
7. according to claim 1 or the preparation method of 6 any one of them fin transistors, which is characterized in that the original fin
Formula transistor further includes substrate, between first fin, between second fin and first fin and second fin it
Between, and have silicide isolated area, the material of the silicide isolated area and the silicide layer in substrate deposition
It is identical.
8. the preparation method of fin transistor according to claim 7, which is characterized in that the silicide layer and the silicon
The material of compound isolated area is silica.
9. according to claim 1,4 or the preparation method of 6 any one of them fin transistors, which is characterized in that described original
Fin transistor further includes substrate, between first fin, between second fin and first fin and second fin
Between, and having silicide isolated area in substrate deposition, the height of the step is the described of the first area
The height at the top of the silicide layer of the bottom of substrate to the first area and the substrate of the second area
Bottom to the height at the top of the silicide layer of the second area difference.
10. according to claim 1,4 or the preparation method of 6 any one of them fin transistors, which is characterized in that described original
Fin transistor further includes substrate, between first fin, between second fin and first fin and second fin
Between, and it is the substrate of the first area to have silicide isolated area, the height of the step in substrate deposition
Bottom to the first area the silicide layer top height and the second area the substrate bottom
To the difference of the height at the top of the silicide isolated area of the second area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810330520.7A CN108461402A (en) | 2018-04-13 | 2018-04-13 | The preparation method of fin transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810330520.7A CN108461402A (en) | 2018-04-13 | 2018-04-13 | The preparation method of fin transistor |
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| Publication Number | Publication Date |
|---|---|
| CN108461402A true CN108461402A (en) | 2018-08-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810330520.7A Pending CN108461402A (en) | 2018-04-13 | 2018-04-13 | The preparation method of fin transistor |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090057780A1 (en) * | 2007-08-27 | 2009-03-05 | International Business Machines Corporation | Finfet structure including multiple semiconductor fin channel heights |
| US20100163971A1 (en) * | 2008-12-31 | 2010-07-01 | Shih-Ting Hung | Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights |
| CN104347414A (en) * | 2013-08-05 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming finned field-effect transistor (FET) |
| CN104733325A (en) * | 2015-03-31 | 2015-06-24 | 上海华力微电子有限公司 | Method for manufacturing fin field effect transistors |
| CN107293590A (en) * | 2016-04-13 | 2017-10-24 | 瑞昱半导体股份有限公司 | Fin formula field effect transistor and its manufacture method |
-
2018
- 2018-04-13 CN CN201810330520.7A patent/CN108461402A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090057780A1 (en) * | 2007-08-27 | 2009-03-05 | International Business Machines Corporation | Finfet structure including multiple semiconductor fin channel heights |
| US20100163971A1 (en) * | 2008-12-31 | 2010-07-01 | Shih-Ting Hung | Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights |
| CN104347414A (en) * | 2013-08-05 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming finned field-effect transistor (FET) |
| CN104733325A (en) * | 2015-03-31 | 2015-06-24 | 上海华力微电子有限公司 | Method for manufacturing fin field effect transistors |
| CN107293590A (en) * | 2016-04-13 | 2017-10-24 | 瑞昱半导体股份有限公司 | Fin formula field effect transistor and its manufacture method |
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Application publication date: 20180828 |