CN104347414A - Method for forming finned field-effect transistor (FET) - Google Patents
Method for forming finned field-effect transistor (FET) Download PDFInfo
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- CN104347414A CN104347414A CN201310338252.0A CN201310338252A CN104347414A CN 104347414 A CN104347414 A CN 104347414A CN 201310338252 A CN201310338252 A CN 201310338252A CN 104347414 A CN104347414 A CN 104347414A
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- 230000005669 field effect Effects 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000005530 etching Methods 0.000 claims abstract description 37
- 230000015572 biosynthetic process Effects 0.000 claims description 50
- 239000007789 gas Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 21
- 230000008021 deposition Effects 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 238000000926 separation method Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 239000000428 dust Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 4
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000010790 dilution Methods 0.000 claims description 3
- 239000012895 dilution Substances 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 22
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- 238000004904 shortening Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 206010020843 Hyperthermia Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- 229910052734 helium Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Abstract
The invention relates to a method for forming a finned field-effect transistor (FET). The method comprises the steps: providing a semiconductor substrate which is provided with a first area and a second area, wherein first initial fin parts are formed on the surface of the semiconductor substrate of the first area, and second initial fin parts are formed on the surface of the semiconductor substrate of the second area; depositing first isolating layers on the surface of the semiconductor substrate and the surfaces of the first and second initial fin parts in an orientated manner; etching the first isolating layers of the second area until the surface of the semiconductor substrate of the second area and the surfaces of the second initial fin parts are exposed; depositing second isolating layers on the surfaces of the first isolating layers of the first area, the surface of the semiconductor substrate of the second area and the surfaces of the second initial fin parts in the orientated manner. The fin parts of the finned FET formed by the method are different in height, the height of the fin parts can be accurately controlled and is not affected by poor processes, and the formed finned FET can meet the requirements of different devices.
Description
Technical field
The present invention relates to semiconductor fabrication techniques field, particularly the formation method of fin field effect pipe.
Background technology
Along with the development of semiconductor process techniques, the development trend that semiconductor technology node follows Moore's Law constantly reduces.In order to adapt to the reduction of process node, have to constantly to shorten the channel length of MOSFET field effect transistor.The shortening of channel length has the tube core density increasing chip, increases the benefits such as the switching speed of MOSFET field effect transistor.
But, along with the shortening of device channel length, distance between device source electrode and drain electrode also shortens thereupon, so grid is deteriorated to the control ability of raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove is also increasing, make sub-threshold leakage (subthreshold leakage) phenomenon, namely so-called short-channel effect (SCE:short-channel effects) more easily occurs.
Therefore, in order to better adapt to the scaled requirement of device size, semiconductor technology starts from planar MOSFET transistor to the transistor transient of three-dimensional with higher effect gradually, as fin field effect pipe (Fin FET).In Fin FET, grid at least can control from both sides to ultra-thin body (fin), have the grid more much better than than planar MOSFET devices to the control ability of raceway groove, can be good at suppressing short-channel effect; And Fin FET is relative to other devices, there is the compatibility of better existing production of integrated circuits technology.
But the current fin needing fin field effect pipe to have differing heights, to meet the demand of different components performance.Such as, the requirement for the transistor of logic and memory is different, and logic transistor requires the fin of larger height, and memory transistor then requires the fin of relatively low height.
How on same wafer, to manufacture the fin with differing heights, become the problem needing solution badly.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method at same semiconductor substrate surface with the fin field effect pipe of differing heights fin, and accurately can control the height of each fin.
For solving the problem, the invention provides a kind of formation method of fin field effect pipe, comprise: the Semiconductor substrate with first area and second area is provided, described first area semiconductor substrate surface is formed with the first initial fin, described second area semiconductor substrate surface is formed with the second initial fin, and the described first initial fin and the second initial fin have phase co-altitude; At described semiconductor substrate surface, the first initial fin portion surface and the second initial fin portion surface first orientated deposition first separator, described first separation layer thickness is less than the first initial fin or the second initial fin height; Form the mask layer covering described first area Semiconductor substrate and the first initial fin portion surface first separator; First separator of etching second area, to exposing the second initial fin and second area semiconductor substrate surface; Second orientated deposition second separator, described second separator is positioned at the first insulation surface of first area Semiconductor substrate and the first fin portion surface, described second separator is also positioned at second area semiconductor substrate surface and the second initial fin portion surface, and described second separator height and the first separator height sum are less than the first initial fin or the second initial fin height; Form sacrifice layer in the second insulation surface, described sacrifice layer top at least exposes second area second insulation surface; Remove the first separator and second separator of the first initial fin portion surface, remove the second separator of the second initial fin portion surface simultaneously; Remove sacrifice layer, form first fin with the first height and second fin with the second height.
Optionally, described second height is the first separation layer thickness with the difference of the first height.
Optionally, the material of described first separator or the second separator is SiO
2.
Optionally, the technique of described first orientated deposition or the second orientated deposition is gas cluster ion beam technique.
Optionally, described gas cluster ion beam technique adopts silicon-containing material and oxygen carrier as predecessor.
Optionally, described silicon-containing material is SiH
4, Si
2h
6, SiH
2cl
2, SiHCl
3or SiCl
4.
Optionally, described oxygen carrier is oxygen.
Optionally, the thickness of described first separator is 500 dust to 1000 dusts.
Optionally, the thickness of described second separator is 200 dust to 1000 dusts.
Optionally, remove the first separator and second separator of the first initial fin portion surface, the technique simultaneously removing the second separator of the second initial fin portion surface is wet etching.
Optionally, the chemical substance that described wet-etching technology adopts is the hydrofluoric acid of dilution.
Optionally, the technique removing sacrifice layer is wet etching.
Optionally, the chemical substance that described wet-etching technology adopts is phosphoric acid.
Compared with prior art, technical scheme of the present invention has the following advantages:
Embodiment provided by the invention, not only makes the first fin and the second fin have differing heights, and second highly can accurately the controlling of first of the first fin the height and the second fin, the first fin of formation and the non-off-design target of the height of the second fin.This be due to:
First adopt directional deposition process to form the first separator in semiconductor substrate surface, the first initial fin portion surface and the second initial fin portion surface, the thickness of described first separator can accurately control.
Secondly, first separator of etching second area semiconductor substrate surface and the second initial fin portion surface, the stop position of described etching technics is for exposing second area Semiconductor substrate and the second initial fin top, therefore do not exist due to etching technics complete after second area semiconductor substrate surface there is the separator that uneven thickness or thickness departs from, so far, described first separation layer thickness is the first fin of follow-up formation and the difference in height of the second fin.
Thirdly, at described first area first insulation surface, second area semiconductor substrate surface and the second initial fin portion surface orientated deposition second separator, described second separation layer thickness can accurately control and homogeneity is good; And all without to the first separator of semiconductor substrate surface or the etching technics of the second separator in follow-up technique, subsequent technique on the first separator of semiconductor substrate surface or the second separation layer thickness without impact, therefore, first of first fin of follow-up formation is highly the height of the first initial fin top to second area second insulation surface, and second of the second fin is highly the height of the second initial fin top to second area second insulation surface.
Again; in first fin and the second fin forming process of FinFET; first initial fin and the second initial fin portion surface are formed with separator; described separator is the first separator or the second separator; described separator plays the effect of the initial fin of protection first or the second initial fin portion surface, makes the impact of the techniques such as its surface is not etched.
Further, in the embodiment of the present invention, described first separator or the second separator adopt gas cluster ion beam technique to be formed.Cluster gas in described gas cluster ion beam technique has extremely strong directivity, the conduct direction of cluster gas is the direction perpendicular to semiconductor substrate surface, therefore when deposition first separator or the second separator, only can in semiconductor substrate surface, the first initial fin portion surface and the second initial fin portion surface deposition, at the sidewall of the first initial fin and the second initial fin all without the material of the first separator or the second separator, improve the first fin of follow-up formation and the quality of the second fin.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the cross-sectional view of prior art Fin FET forming process;
Fig. 5 to Figure 12 is the cross-sectional view of one embodiment of the invention Fin FET forming process.
Embodiment
From background technology, prior art is identical at the height of the upper Fin FET fin formed of same wafer (i.e. Semiconductor substrate), is unfavorable for the performance requirement meeting different components.
For this reason, the fin formation process for Fin FET is studied.
Fig. 1 to Fig. 4 is the cross-sectional view of prior art Fin FET forming process.
Please refer to Fig. 1, provide Semiconductor substrate 100, described Semiconductor substrate 100 surface is formed with multiple initial fin 101.
Please refer to Fig. 2, form the separator 102 covering Semiconductor substrate 100 surface and initial fin 101.
Please refer to Fig. 3, adopt CMP planarization separator 102, make the top of separator 102 concordant with initial fin 101 top.
Please refer to Fig. 4, adopt back the separator 102 of etching technics etch semiconductor substrates 100 surface portion thickness, form multiple fin 103, the height h of described fin 103 is the height on separator 102 surface behind fin 103 top to etching.
The high level of homogeneity of the Fin FET fin 103 that above-mentioned processing step is formed is poor, and formation process controls fin 103 ability highly, the former design object of fin 103 highly deviated of formation.
Fin formation process for Fin FET studies discovery further, and the high level of homogeneity of fin 103 difference is mainly by CMP and return that etching technics causes.
Concrete, in CMP planarization separator 102 technical process, CMP also can create chemico-mechanical polishing to a certain degree to initial fin 101 top; And after CMP, the height of separator 102 is also difficult to keep highly consistent, even if the follow-up control of etching technics to height of returning reaches perfect condition, because the caliper uniformity of separator after CMP 102 is poor, return the rear remaining uneven thickness of separator 102 of etching, thus, the fin that CMP is good to height of formation homogeneity has harmful effect.
After CMP completes, adopt back etching technics, the separator 102 of etch semiconductor substrates 100 surface portion thickness, there is the problems such as process variation owing to returning etching technics, after adopting back etching technics to remove the separator 102 of segment thickness, remaining separator 102 each area thickness consistency is poor.
To form the fin with differing heights at same semiconductor substrate surface, then slightly change in above-mentioned Fin FET formation process step, namely to when between the height of follow-up formation different fin, semiconductor substrate surface separator carries out back etching technics, the technological parameter returning etching is different, to reach back after etching technics completes, the object that between fin, semiconductor substrate surface separation layer thickness is different, namely forms the object with differing heights fin.
Same, forming in the technical process of differing heights fin time etching technics that also there is CMP and etched portions separator, also there is the problem departing from former design object height in the fin height of formation.
For this reason, the invention provides a kind of formation method of fin field effect pipe of optimization, after semiconductor substrate surface, the first initial fin portion surface and the second initial fin portion surface form the first separator, remove the first separator of second area, form the second separator in first area first insulation surface, second area semiconductor substrate surface and the second initial fin portion surface.Present invention, avoiding the harmful effect of the technique such as CMP and etching to fin height, the fin of the fin field effect pipe of formation has differing heights, and the fin height of fin field effect pipe can accurately control.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 5 to Figure 12 is the cross-sectional view of one embodiment of the invention Fin FET forming process.
Please refer to Fig. 5, the Semiconductor substrate 200 with first area I and second area II is provided, I Semiconductor substrate 200 surface, described first area is formed with the first initial fin 201, described second area II Semiconductor substrate 200 surface is formed with the second initial fin 202, and the described first initial fin 201 and the second initial fin 202 have phase co-altitude.
The effect of described Semiconductor substrate 200 is for follow-up formation semiconductor device provides workbench.
The material of described Semiconductor substrate 200 is silicon, germanium, SiGe, GaAs, carborundum or isolate supports.
In the present embodiment, the material of described Semiconductor substrate 200 is silicon.
Described first area I has the workbench region at the first fin place of the first height for defining follow-up formation, described second area II has the workbench region at the second fin place of the second height for defining follow-up formation.
In embodiments of the invention, be highly less than second of the second fin with first of the first fin formed and highly do exemplary illustrated.
Described first initial fin 201 and the second initial fin 202 are adopt reactive ion etching method (RIE:Reactive Ion Etching) to etch an initial semiconductor substrate to be formed.
As an embodiment, the forming step of the described first initial fin 201 and the described second initial fin 202 is: provide initial semiconductor substrate, patterned mask plate is formed at described initial semiconductor substrate surface, described mask plate defines the position of the initial fin 201 of follow-up formation first and the second initial fin 202, with patterned mask plate for mask, adopt reactive ion etching process, the initial semiconductor substrate of etched portions thickness is to forming Semiconductor substrate 200, the first initial fin 201 is formed on first area I Semiconductor substrate 200 surface, the second initial fin 202 is formed on second area II Semiconductor substrate 200 surface.
Described first initial fin 201 and the second initial fin 202 have identical height.
Height is now the height of the initial semiconductor substrate surface of top surface after etching of the initial fin 202 of the first initial fin 201, second.
Please refer to Fig. 6,, first initial fin 201 surface and second initial fin 202 surperficial first orientated deposition first separator 211 surperficial in described Semiconductor substrate 200, described first separator 211 thickness is less than the first initial fin 201 or the second initial fin 202 height.
First separator 211 on I Semiconductor substrate 200 surface, described first area as portions of isolation structure, isolates the fin of adjacent area for follow-up.
First separator 211 on the described first initial fin 201 surface has initial fin 201 top of protection first not by the effect that subsequent technique affects.
The thickness of described first separator 211 defines the difference in height of follow-up formation first fin and the second fin.The thickness of described first separator 211 can need to regulate according to technique.
The technique of the first orientated deposition first separator 211 is gas cluster ion beam technique (GCIB:gas cluster ion beam).
Cluster gas in GCIB technique has very strong directivity, and to reach above-mentioned zone surface perpendicular to Semiconductor substrate 200 surface, the first initial fin 201 direction that is surperficial and the second initial fin 202 surface, forms the first separator 211.
Because cluster gas is that tool is directive, therefore only minority or do not have the material of the first separator 211 to appear at the surface being parallel to cluster gas conduct direction, namely there is not the material of the first separator 211 in the first initial fin 201 and the second initial fin 202 higher than the sidewall surfaces of the first separator 211, improve the quality of follow-up formation first fin or the second fin.
Described gas cluster ion beam technique adopts the material containing object element as predecessor, described predecessor is passed in reaction chamber, by predecessor cluster ions or filtered, make the conduct direction of cluster gas for surperficial perpendicular to Semiconductor substrate 200, also can in reaction chamber electric field in addition, described electric field promotes that cluster gas accelerates, kinetic energy required for acquisition, the kinetic energy that cluster gas can have is that 1kev such as, to tens of kev, 1kev, 10kev, 30kev, 50kev, 70kev, 90kev; When gas-cluster impact Semiconductor substrate 200 surface, the first initial fin 201 surface or the second initial fin 202 are surperficial, described kinetic energy converts localized hyperthermia to, helps lend some impetus to reacted residual gas and leaves deposit.
When described predecessor is at room temperature gaseous state, can directly described gaseous precursors be passed in reaction chamber; When described predecessor is at room temperature liquid, by vector gas, predecessor can be converted into gas and pass in reaction chamber, described vector gas is one or more in He, Ne, Ar, Kr, Xe or Rn.
In the present embodiment, the material of described first separator 211 is silica, and the thickness of described first separator 211 is 500 dust to 1000 dusts.
Described GCIB technique adopts silicon-containing material and oxygen carrier as predecessor, and described silicon-containing material is SiH
4, Si
2h
6, SiH
2cl
2, SiHCl
3or SiCl
4in one or more, described oxygen carrier is oxygen.
Please refer to Fig. 7, form the mask layer 210 covering described first area I Semiconductor substrate 200 and surperficial first separator 211 of the first initial fin 201.
In the present embodiment, be highly less than the second highly presenting a demonstration property explanation of the second fin with first of the first fin of follow-up formation.For realizing above-mentioned target, form mask layer 210 on first separator 211 surface of first area I, follow-up etches further to first separator 211 of second area II.
Described mask layer 210, for the protection of first separator 211 of the first initial fin 201 and first area I, makes it by the destruction of first separator 211 technique of subsequent etching second area II.
In the present embodiment, the material of described mask layer 210 is photoresist, adopts the techniques such as exposure, development to be formed.
Please refer to Fig. 8, the first separator 211(of etching second area II please refer to Fig. 7), until expose the second initial fin 201 and second area II Semiconductor substrate 200 surface.
Concrete, please refer to Fig. 7 with mask layer 210() be mask, adopt first separator 211 of dry etch process etching second area II, until all removed by first separator 211 of second area II.
As an embodiment, the technique of first separator 211 of described etching second area II is reactive ion etching, and the gas that reactive ion etching process adopts is SF
6, CF
4, CHF
3, CH
2f
2, CH
3f, NH
3in one or more.
In the present embodiment, first separator 211 of second area II is all etched, avoid etching complete after remaining first separator 211 uneven thickness of second area II or thickness parameter off-design target.As can be seen here, the first height of the first fin of follow-up formation and the second difference in height of the second fin be not by the impact of etching technics, and described difference in height is still the thickness of first area I first separator 211.
After etching technics completes; remove mask layer 210; the technique removing mask layer 210 can be cineration technics or wet clean process; because all there is separator on the first initial fin 201 and the second initial fin 202 surface; described separator is the first separator 211 or the second separator 222, and described separator protection the first initial fin 201 and the second initial fin 202 surface be not by the destruction of removing mask layer 210 technique.
Please refer to Fig. 9, second orientated deposition second separator 222, described second separator 222 is positioned at first separator 211 surface of first area I, described second separator 222 is also positioned at second area II Semiconductor substrate 200 surface and the second initial fin 202 surface, and described second separator 222 height and the first separator 211 height sum are less than the first initial fin 201 or the second initial fin 202 height.
Second separator 222 on described second area II Semiconductor substrate 200 surface as isolation structure, isolates the fin of adjacent area for follow-up.
Second separator 222 on the described second initial fin 202 surface has the initial fin 202 of protection second not by the effect that subsequent technique affects.
First separator 211 on I Semiconductor substrate 200 surface, described first area and the second separator 222 form the separator of first area I jointly, for follow-up as isolation structure, and the fin of isolation adjacent area.
First separator 211 on the described first initial fin 201 surface and the second separator 222 are not subject to the impact of subsequent technique for the protection of the first initial fin 201.
The technique that described second orientated deposition forms the second separator 222 is GCIB technique.
In the present embodiment, the material of described second separator 222 is silica, and the thickness of described second separator 222 is 200 dust to 1000 dusts.
In the present embodiment, the formation process of described second separator 222 is: described GCIB technique adopts silicon-containing material and oxygen carrier as presoma, and described silicon-containing material is SiH
4, Si
2h
6, SiH
2cl
2, SiHCl
3or SiCl
4in one or more, described oxygen carrier is oxygen.
Please refer to Figure 10, form sacrifice layer 203 on the second separator 222 surface, described sacrifice layer 203 top at least exposes second area II second separator 222 surface.
The formation of described sacrifice layer 203 is used for first separator 211 and second separator 222 on initial fin 201 surface of follow-up removal first, removes second separator 222 on the second initial fin 202 surface.
The material of described sacrifice layer 203 is silicon nitride or silicon oxynitride.
The formation process of described sacrifice layer 203 is chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald.
As an embodiment, the forming step of described sacrifice layer 203 is: adopt chemical vapor deposition method to form the second separator 222 covering I Semiconductor substrate 200 surface, first area, first initial fin 201, second separator 222 on second area II Semiconductor substrate 200 surface and the sacrifice layer of the second initial fin 202, etching technics is adopted back to remove partial sacrificial layer 203, return after etching technics completes, described sacrifice layer 203 top at least exposes second area II second separator 222 surface, so that initial surperficial second separator 222 of fin 202 of follow-up removal second.
Due to time etching technics removal is partial sacrificial layer 203; the height of sacrifice layer 203 thickness and follow-up formation first fin and the second fin has nothing to do; therefore; return etching technics and remove the height of partial sacrificial layer 203 on the first fin and the second fin without impact; and due to the protection of the first separator 211 or the second separator 222, the first initial fin and the second initial fin are not subject to back the impact of etching technics.
In the present embodiment, after time etching technics completes, described sacrifice layer 203 top is concordant with the first initial fin 201 or the second initial fin 202 surface.
In other embodiments of the present invention, described sacrifice layer 203 top is higher than the first initial fin 201 or the second initial fin 202 surface, and described sacrifice layer 203 top exposes second area II second separator 222 surface.
Please refer to Figure 11, remove the first separator 211(on the first initial fin 201 surface and please refer to Figure 10) and the second separator 222(please refer to Figure 10), the second separator 222(on removal the second initial fin 202 surface please refer to Figure 10 simultaneously).
Remove first separator 211 and second separator 222 on the first initial fin 201 surface, the technique simultaneously removing second separator 222 on the second initial fin 202 surface is dry etching or wet etching.
Preferably, wet etching is adopted to remove described first separator 211 and the second separator 222.
In the present embodiment, the chemical substance that described wet etching adopts is the hydrofluoric acid (DHF:Diluted HF) of dilution.
Please refer to Figure 12, remove sacrifice layer 203(and please refer to Figure 11), form first fin 210 with the first height h1 and second fin 220 with the second height h2.
First height h1 of described first fin 210 is the height of the first initial fin 201 top to second separator 222 surface of first area I.
Second height h2 of described second fin 220 is the height of the second initial fin 202 top to second separator 222 surface of second area II.
The difference of described second height h2 and first height h1 is the first separation layer thickness.
Because the thickness of the first separator 211 or the second separator 222 all can accurately be controlled by the first orientated deposition or the second orientated deposition; And first area I first separator 211 and the second separator 222 such as all to be etched after its formation at the destruction of technique, the thickness sum of the first separator 211 and the second separator 222 does not depart from former design object, second area II second separator 222 does not experience etching technics after its formation, therefore also can not there is deviation in the thickness of the second separator 222, and caliper uniformity is good.
The technique removing sacrifice layer 203 is wet etching.
In the present embodiment, the chemical substance that described wet etching adopts is phosphoric acid (H
3pO
4).
So far, complete the formation process that Fin FET has the fin of differing heights, the follow-up first grid structure that can be formed across first fin with the first height, described first grid structure covers top and the sidewall of the first fin, form the second grid structure across second fin with the second height, described second grid structure covers top and the sidewall of the second fin.
It should be noted that, in other embodiments of the invention, more region can also be formed, copy said method to form the fin with more differing heights, such as, Semiconductor substrate is divided into three regions, form the fin with three differing heights.
To sum up, technical scheme of the present invention has the following advantages:
The formation method of Fin FET provided by the invention, not only can form the fin with differing heights, and the fin height formed can accurately control, and the fin field effect pipe with differing heights fin can meet the demand of different components.
First; directional deposition process is adopted to form the first separator in semiconductor substrate surface, the first initial fin portion surface and the second initial fin portion surface; the thickness of described first separator accurately can be controlled by technique, and the first separator of the first initial fin portion surface has the initial fin of protection first not by the effect that subsequent technique destroys.
Secondly, etching removes the first separator of second area completely, and namely the thickness of described first separator define the first fin of follow-up formation and the difference in height of the second fin; Form the second separator in first area first insulation surface, second area semiconductor substrate surface and the second initial fin portion surface, described second separation layer thickness accurately can be controlled by technique.
Again, in FinFET forming process, be formed with the first separator or the second separator at the first initial fin or the second initial fin portion surface, described first separator or the second separator have the effect of the initial fin of protection first or the second initial fin portion surface.
In embodiments of the invention, there is not the technical process of partial etching first separator or the second separator, the first separator or the second separation layer thickness by the destruction of technique, and the first separator or the second separation layer thickness controlled, homogeneity is good.
First of the first fin formed highly is the height of the first initial fin top to first area second separator, second of second fin is highly the height of the second initial fin top to second area second separator, first fin or second fin of visible formation have differing heights, and the height of the first fin or the second fin can accurately control.
And adopt gas cluster ion beam technique to form the first separator or the second separator, because cluster gas has the direct of travel perpendicular to semiconductor substrate surface, the first initial fin portion surface and the second initial fin portion surface, therefore, the sidewall of the first initial fin and the second initial fin all can not be formed the material of the first separator or the second separator, be conducive to improving the first fin of follow-up formation or the quality of the second fin, and then improve the performance of the fin field effect pipe formed.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (13)
1. a formation method for fin field effect pipe, is characterized in that, comprising:
The Semiconductor substrate with first area and second area is provided, described first area semiconductor substrate surface is formed with the first initial fin, described second area semiconductor substrate surface is formed with the second initial fin, and the described first initial fin and the second initial fin have phase co-altitude;
At described semiconductor substrate surface, the first initial fin portion surface and the second initial fin portion surface first orientated deposition first separator, described first separation layer thickness is less than the first initial fin or the second initial fin height;
Form the mask layer covering described first area Semiconductor substrate and the first initial fin portion surface first separator;
First separator of etching second area, until expose the second initial fin and second area semiconductor substrate surface;
Second orientated deposition second separator, described second separator is positioned at the first insulation surface of first area, described second separator is also positioned at second area semiconductor substrate surface and the second initial fin portion surface, and described second separator height and the first separator height sum are less than the first initial fin or the second initial fin height;
Form sacrifice layer in the second insulation surface, described sacrifice layer top at least exposes second area second insulation surface;
Remove the first separator and second separator of the first initial fin portion surface, remove the second separator of the second initial fin portion surface simultaneously;
Remove sacrifice layer, form first fin with the first height and second fin with the second height.
2. the formation method of fin field effect pipe according to claim 1, is characterized in that, described second height is the first separation layer thickness with the difference of the first height.
3. the formation method of fin field effect pipe according to claim 1, is characterized in that, the material of described first separator or the second separator is SiO
2.
4. the formation method of fin field effect pipe according to claim 1, is characterized in that, the technique of described first orientated deposition or the second orientated deposition is gas cluster ion beam technique.
5. the formation method of fin field effect pipe according to claim 4, is characterized in that, described gas cluster ion beam technique adopts silicon-containing material and oxygen carrier as predecessor.
6. the formation method of fin field effect pipe according to claim 5, is characterized in that, described silicon-containing material is SiH
4, Si
2h
6, SiH
2cl
2, SiHCl
3or SiCl
4.
7. the formation method of fin field effect pipe according to claim 5, is characterized in that, described oxygen carrier is oxygen.
8. the formation method of fin field effect pipe according to claim 1, is characterized in that, the thickness of described first separator is 500 dust to 1000 dusts.
9. the formation method of fin field effect pipe according to claim 1, is characterized in that, the thickness of described second separator is 200 dust to 1000 dusts.
10. the formation method of fin field effect pipe according to claim 1, is characterized in that, remove the first separator and second separator of the first initial fin portion surface, the technique simultaneously removing the second separator of the second initial fin portion surface is wet etching.
The formation method of 11. fin field effect pipes according to claim 10, is characterized in that, the chemical substance that described wet etching adopts is the hydrofluoric acid of dilution.
The formation method of 12. fin field effect pipes according to claim 1, is characterized in that, the technique removing sacrifice layer is wet etching.
The formation method of 13. fin field effect pipes according to claim 12, is characterized in that, the chemical substance that described wet etching adopts is phosphoric acid.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039275A (en) * | 2016-02-04 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN107293590A (en) * | 2016-04-13 | 2017-10-24 | 瑞昱半导体股份有限公司 | Fin formula field effect transistor and its manufacture method |
| CN108461402A (en) * | 2018-04-13 | 2018-08-28 | 上海华力集成电路制造有限公司 | The preparation method of fin transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992185A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating a fin field effect transistor in a semiconductor device |
| US20100163971A1 (en) * | 2008-12-31 | 2010-07-01 | Shih-Ting Hung | Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights |
-
2013
- 2013-08-05 CN CN201310338252.0A patent/CN104347414B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992185A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating a fin field effect transistor in a semiconductor device |
| US20100163971A1 (en) * | 2008-12-31 | 2010-07-01 | Shih-Ting Hung | Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039275A (en) * | 2016-02-04 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN107293590A (en) * | 2016-04-13 | 2017-10-24 | 瑞昱半导体股份有限公司 | Fin formula field effect transistor and its manufacture method |
| CN107293590B (en) * | 2016-04-13 | 2020-08-18 | 瑞昱半导体股份有限公司 | Fin field effect transistor and manufacturing method thereof |
| CN108461402A (en) * | 2018-04-13 | 2018-08-28 | 上海华力集成电路制造有限公司 | The preparation method of fin transistor |
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|---|---|
| CN104347414B (en) | 2017-07-14 |
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