CN104037122B - Multiple layer metal contact - Google Patents
Multiple layer metal contact Download PDFInfo
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- CN104037122B CN104037122B CN201310451248.5A CN201310451248A CN104037122B CN 104037122 B CN104037122 B CN 104037122B CN 201310451248 A CN201310451248 A CN 201310451248A CN 104037122 B CN104037122 B CN 104037122B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a kind of method for being used to form metal contact element in semiconductor devices, methods described is included in the formation first layer contact in the first dielectric layer of at least one gate electrode, and first layer contact extends to the doped region of base substrate.Methods described further comprises in the first dielectric layer the second dielectric layer of formation, and formation extends through the second dielectric layer to the second layer contact of first layer contact.
Description
The cross reference of related application
This application claims the U.S. Patent Application No. submitted on March 10th, 2013 priority of 61/775, No. 642, its
Content is hereby expressly incorporated by reference.
Technical field
Present invention relates generally to semiconductor applications, more particularly, to multiple layer metal contact.
Background technology
Semiconductor integrated circuit can include the various parts containing transistor.This kind of circuit can also include with desired side
The metal wire and contact of formula connection member, to form functionalization, interconnection and integrated circuit.The manufacture of this kind of circuit is usual
By forming lamination on a semiconductor substrate（For example start from semiconductor crystal wafer）To realize.
For example, can be on a semiconductor substrate with middle formation transistor with including in the grid structure and substrate on substrate
Doped source and drain electrode structure.Then, covered by interlayer dielectric layer and surround structure.Form hole and pass through interlayer dielectric layer simultaneously
Extend downward into grid structure and impure source and drain electrode structure.Then, fill this some holes to be formed using conductive material
Required is used for the cross tie part that other one or more circuit blocks are connected（Also referred to as contact or through hole）.
The hole of the use conductive material filling of formation does not generate straight cylindrical hole.Opposite, with its extension
It is deeper, hole becomes narrower.Because grid and doped region are located at different height, for doped region hole and be used for
The hole of grid can be of different sizes.Specifically, due to extending to the Kong Yueshen of doped region, it is with extending to gate electrode
Hole compared to can be wider on top.
The different of hole size have influence to patterning schemes.Specifically, the critical dimension in the hole of doped region is extended to
（The amount of space allowed between hole is related）Different from the critical dimension in the hole for extending to grid.Expect to reduce it is this it is different so as to
Allow more preferable alignment budget（overlay budget）And critical dimension control.
The content of the invention
To solve the above problems, the present invention relates to a kind of method for being used to form metal contact element in semiconductor devices,
This method includes：First layer contact is formed in the first dielectric layer around gate electrode, first layer contact extends to bottom
Impure source/drain region of substrate；In the first dielectric layer the second dielectric layer of formation；Formation is prolonged through the second dielectric layer
Extend the second layer contact of first layer contact.
This method further comprises：Form the second layer of the gate electrode extended to through the second dielectric layer in the first dielectric layer
Contact.
This method further comprises：Formed through the second dielectric layer and extend to connecing for gate electrode and first layer metal contact
Contact element.
Wherein, second layer contact is formed, step is formed between first layer contact and second layer contact.
Wherein, the critical dimension of first layer contact is substantially similar to the critical dimension of second layer contact.
Wherein, gate electrode includes high-K metal gate electrode.
This method further comprises：Second layer contact is formed, second layer contact extends through the second dielectric layer and hard
Mask layer, hard mask layer surrounds gate electrode to be connected with gate electrode.
Wherein, hard mask layer relative to the first dielectric layer there is selectivity to be used to etch purpose.
In addition, a kind of semiconductor devices is additionally provided, including：Substrate, including doped region；First dielectric layer, around shape
Into at least one gate electrode on substrate, the first dielectric layer includes the first layer contact for extending to doped region；Second is situated between
Electric layer, is formed in the first dielectric layer, and the second dielectric layer includes extending to the of first layer contact through the second dielectric layer
Two layers of contact.
The device further comprises the second layer contact of the gate electrode extended to through the second dielectric layer in the first dielectric layer
Part.
The device further comprises：Step, between first layer contact and second layer contact.
Wherein, the critical dimension of first layer contact is substantially similar to the critical dimension of second layer contact.
Wherein, gate electrode includes high-K metal gate electrode.
Wherein, using hard mask layer covering grid electrode.
The device further comprises the gate electrode extended to through the second dielectric layer and hard mask layer in the first dielectric layer
Second layer contact.
Wherein, hard mask layer relative to the first dielectric layer there is selectivity to be used to etch purpose.
In addition, additionally providing a kind of method for being used to form metal contact element in semiconductor devices, this method includes：
Depositing gate electrode on substrate；The region of neighbouring gate electrode in substrate is doped to form doped region；Above gate electrode
Depositing first dielectric layer；First layer contact is formed in the first dielectric layer；In the first dielectric layer the second dielectric layer of formation；
Form the second layer contact that first layer contact is extended to through the second dielectric layer so that in first layer contact and the second layer
There is step between contact.
This method further comprises：Form the second layer of the gate electrode extended to through the second dielectric layer in the first dielectric layer
Contact.
Wherein, the critical dimension of first layer contact is substantially similar to the critical dimension of second layer contact.
Wherein, gate electrode includes high-K metal gate electrode.
Brief description of the drawings
Combined according to specific descriptions hereafter and each aspect of the present invention may be better understood by reference to the accompanying drawings.It should be emphasized that
Standard practices in industry, all parts are not drawn to scale.In fact, in order to clearly discuss, the chi of all parts
It is very little arbitrarily to increase or reduce.
Figure 1A to Fig. 1 E is to be used for the shape in semiconductor devices according to an example of principles described in this document
Into the diagram of the illustrative processes of metal contact element.
Fig. 2A to Fig. 2 B is the example with multilayer contact part according to an example of principles described in this document
The diagram of property semiconductor devices.
Fig. 3 is being used for according to an example of principles described in this document multilayer gold to be formed in semiconductor devices
Belong to the flow chart of the illustrative methods of contact.
Embodiment
It should be understood that disclosure below provide many not be the same as Examples for being used to implement disclosed different characteristic or
Example.The instantiation of part and configuration is described below to simplify the present invention.Certainly, this is only example, is not limited to
The present invention.Moreover, in the following description, implementing the first technique before the second technique of implementation can be included in after the first technique
Directly implement the embodiment of the second technique, can also include can implementing extra between the first technique and the second technique
The embodiment of technique.For simplification and clearly purpose, all parts can be arbitrarily drawn in varing proportions.In addition, following
In description, first component formation is direct in the first component and second component that second component can include being formed over or on
The embodiment of contact, and can also be included between first component and second component and can form extra part, so that
The embodiment that first component and second component can be not directly contacted with.
Moreover, for the ease of description, such as " in ... lower section ", " ... under ", " bottom ", " ... on ", " top "
It can be used for a description element as depicted or part and another etc. relative space position term（Or other）Element
Or the relation of part.It should be understood that in addition to the orientation described in figure, these relative space position terms are intended to include device to exist
Using or operation in different azimuth.If for example, the device in upset accompanying drawing, be described as other elements or part " under "
Or the element of " lower section " will be oriented in other elements or part " on ".Therefore, exemplary term " ... under " can wrap
Include up and in two kinds of lower section orientation.Device can be orientated other directions（It is rotated by 90 ° or in other orientation）, and phase
Should the descriptor of ground explanation herein for relative space position.
Figure 1A to Fig. 1 E shows the diagram of the illustrative processes for forming metal contact element in semiconductor devices.Figure
The every width of 1A to Fig. 1 E shows three different views of the identity unit of instantiation in technique.In every width diagram, left-hand line
102 show along first（x）The sectional view in direction, middle column 104 shows top view, and right-hand column 106 is shown along second（y）
The sectional view in direction.
Figure 1A shows the formation of the first dielectric layer 108 around multiple gate electrodes 112.Gate electrode 112 is formed in substrate
On 101 top.In addition, hard mask layer 110 is formed in the top of gate electrode 112.Substrate 101 includes mixing for neighbouring gate electrode 112
Miscellaneous region, in order to simplify description, the not shown such regions of this paper.
According to some illustrative examples, substrate 101 can also include Silicon Wafer.Alternatively, or in addition, substrate 101 can be with
Include the elemental semiconductor of another such as germanium；Including carborundum, GaAs, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide
Compound semiconductor；Or the alloy including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP
Semiconductor.In another alternative embodiment, substrate 101 can also include dielectric layer, conductive layer or combinations thereof.
According to some illustrative examples, the non-low k dielectric that the first dielectric layer 108 can be more than 3.9 by k values is formed,
Such as silica（SiO2）, silicon nitride（SiN）Or silicon oxynitride（SiON）.In embodiment, the first dielectric layer 108 is by such as non-
Doped silicate glasses（USG）, boron-doping silicon silicate glass（BSG）, phosphorous doped silicon silicate glass（PSG）, boron doping phosphorus silicic acid
Salt glass（BPSG）Deng oxide formed.First dielectric layer 108 can also be by the nitridation on silicon oxide layer and silicon oxide layer
Silicon layer is formed.Alternatively, the low k dielectric that the first dielectric layer 108 can be less than 3.9 by k values is formed, and for example Fluorin doped is aoxidized
Silicon, carbon doped silicon oxide, porous silica, porous carbon doped silicon oxide, organic polymer or silicone-based polymers.At this
In a little embodiments, chemical vapor deposition can be used（CVD）Or PVD（PVD）Technique the first dielectric layer 108 of formation.
According to some illustrative examples, gate electrode 112 can be high-k/metal gate.Some grids are by such as polysilicon
Material is made, and other grids can be made of metal.Such metal gates include the high k dielectric material being located between grid and substrate
Material.To form such grid, dummy grid need to be formed on substrate.After dummy grid formation hard mask layer, puppet can be removed
Grid, it is possible to fill high-k dielectric material and metal material to the space by removing dummy grid and leaving.
Figure 1A, which also show, such as to be chemically-mechanicapolish polished（CMP）First after the use of flatening process 111 of technique is situated between
Electric layer.Flatening process 111 can remove unnecessary dielectric material to expose the hard mask material formed in the top of grid 112
110 top.
According to this example, gate electrode 112 is fin-shaped.Specifically, it is formed as the shape of elongation.Can by top view 104
To find out, the hard mask material 110 of the circular gate electrode 112 exposed is extended with two parallels, and each corresponds to one
Individual gate electrode 112.In y directions diagram 106, dielectric layer 108 is illustrate only in this specific sectional view.Show in x directions
In Figure 102, two gate electrodes 112 and the hard mask material 110 surrounded are shown.
Figure 1B is shown forms etching stopping layer 114 on the top of the first dielectric layer 108, at the top of etching stopping layer 114
It is upper to form interim dielectric layer 116, and form Other substrate materials 118 on the interim top of dielectric layer 116.Etching stopping layer 114
For the metal contact element for helping to form the gate electrode 112 being connected in substrate 101 or doped region in the etch process.According to
Some illustrative examples, etching stopping layer 114 can include silicon nitride or silicon oxynitride.
According to some illustrative examples, Other substrate materials 118 can be eurymeric material or minus material.Other substrate materials
118 are used in first layer contact patterning to the first dielectric layer 108.First dielectric layer 108 is patterned by photoetching process.
The process step of exemplary light carving technology is dried after can including coating photoresist 118, soft baking, mask registration, exposure, exposure
Roasting, lithographic glue and hard baking.Photoetching process can apply KrF（KrF）Excimer laser, argon fluoride（ArF）It is accurate
Molecular laser, ArF liquid immersion lithographies, extreme ultraviolet（EUV）Or electron beam write-in（e-beam）.Photolithographic exposure technique can also
Write by such as maskless lithography, ion beam and other suitable methods of molecular imprint are implemented or substituted.When to exposure
When photoresist layer 118 applies developing solution, the photoresist region of exposure（For positive photo glue）Following sacrifice layer also part
Or all remove.
In this example, first layer contact is perpendicular to fin-shaped gate electrode 112.
Fig. 1 C show etch process and remove the device after Other substrate materials 118.Etch process influences photoetching glue material
The region that material 118 exposes.Specifically, hole 113 is etched down to hard mask layer 110.Therefore, the material of hard mask layer 110 is formed
With the selectivity being etched relative to the material for forming dielectric layer 108,116.
Because hole 113 is perpendicular to gate electrode 112, therefore hole 113 can not be observed in the diagram 102 in x directions.But,
In a top view, it is observed that hard mask layer 110 is exposed in hole 113.Specifically, etch process is etched down to around gate electrode
112 hard mask material 110, and the hard mask material 110 deposited along substrate 101.Y directions diagram 106, which is shown, to be extended downwardly
To the hole 113 of gate electrode 112 and the hard mask layer 110 along substrate 101.Due to the etch process of standard, hole 113 will not be vertical
Downwards.On the contrary, hole 113 more becomes narrower to depths extension.
Fig. 1 D, which are shown, is filling the CMP 122 after hole forms metal contact element 120 using metal material.Metal connects
Contact element can include the various materials comprising barrier layer and crystal seed layer.For example, metal contact element 120 can include titanium nitride
（TiN）, tantalum nitride（TaN）Or platinum（Pt）.In addition, metal contact element can include each of such as tungsten, copper, aluminium or combinations thereof
Plant packing material.Ald can be passed through（ALD）, PVD（PVD or sputtering）Or optionally other are suitable
Technique formation metal contact element 120.
According to this example, the downward grinding elements of CMP 122 is until exposing the hard mask layer on the top of gate electrode 112
110.This grinding eliminates interim dielectric layer 116, etching stopping layer 114 and any metal positioned at the top of gate electrode 112
Material.Desired region of this grinding in semiconductor devices retains first layer metal contact 120.
From x directions diagram 102 not it is observed that metal contact element 120.From top view 104, it is observed that positioned at grid
Metal contact element between electrode 112.Metal contact element 120 can also be observed from y directions diagram 106.
Fig. 1 E are shown forms second layer contact in the second dielectric layer 124 for being formed at the top of the first dielectric layer 108
126、128、130.Second layer metal contact can include similar to those first layer metal contacts discussed herein above
Or different materials.According to this example, second layer metal contact 126 is made only in above first layer metal contact.Therefore,
First layer metal contact 120 and collectively form for second layer metal contact extend downward into the complete of substrate doped region
Contact.This kind of metal contact element 126 can be used for source electrode or the drain terminal for being connected to transistor.
According to this example, formation is passed down through the second dielectric layer 124 to the second layer metal contact 128 of gate electrode 112.
Contact extends through hard mask layer 110 to contact actual grid 112.Place this contact so that it can not with it is any
First layer metal contact 120 is contacted.This can cause the short circuit between grid and doped region.
In addition, second layer metal contact 130 is formed in gate electrode 112 and the top of first layer metal contact 120.One
In a little circuits, the cross tie part between the source terminal or drain electrode end of transistor and the grid of transistor is desirably formed.It is as shown here,
Second layer metal contact 130 can be used to effectively form this cross tie part.
X directions diagram 120 shows each in second layer metal contact 126,128,130.Due in sectional view
It is interior they set it is relatively deep, so contact is shown in broken lines.Top view be also shown for second layer metal contact 126,128,
Each in 130.Y directions diagram shows the second layer metal contact 128 for extending only to gate electrode 112 and extension
To gate electrode 112 and the second layer metal contact 130 of first layer metal contact 120.
Can be by each in standard photolithography process formation second layer metal contact 126,128,130.For example, light
Photoresist material can be used for patterning the second dielectric layer 124.Photoresist layer by the light source through photomask be exposed with
And after photoresist layer development, hole can be formed at the region for removing photoresist layer.It is then possible to fill this using metal material
Some holes is to form second layer metal contact 126,128,130.
Fig. 2A and Fig. 2 B are the diagrams for showing the example semiconductor device with multilayer contact part.Fig. 2A shows reality
Apply the multiple layer metal contact of principles described in this document.On the contrary, Fig. 2 B are shown forms different height in identical technique
Metal contact element conventional method.
Fig. 2A shows the doped region 204 to be formed in substrate 202.Doped region 204 is adjacent to gate electrode 208 with formation
Complete transistor.Similar to the structure shown in Figure 1A to Fig. 1 E, hard mask material 210 surrounds grid 208.In addition, first is situated between
Electric layer 212 surrounds gate electrode.First layer metal contact 204 is formed in the first dielectric layer 212.First layer metal contact to
Under extend to doped region 204.
Second dielectric layer 214 is formed on the top in the first dielectric layer 212.The formation of second layer metal contact 216,218
In the second dielectric layer 214.One second layer contact 216 extends downward into gate electrode 208.Another second layer contact 218
Extend downward into first layer metal contact 206.
In this example, using identical Patternized technique formation second layer metal contact 216,218.Further, since
Doped region 204 need not be extended downward into always by being connected to the second layer metal contact 218 of doped region 204, therefore it can be with
It is fabricated to and retains small size at top.So allow for more preferable alignment budget.Specifically, due to extending downward into doping
The hole in region 204 need not be wider at top, so close part can be formed by implementing the patterning of the device of this paper principles.
Due to extending downward into the complete contact of doped region 204 using two separated technique formation, so
Step 224 is formed between first layer contact 206 and second layer contact 218.But, this step is in first layer contact
Do not have substantial effect on electrical interconnection between 206 and second layer contact 218.
The contact that Fig. 2 B showed and be connected to gate electrode 208 is connected to doped region using the formation of same process
The conventional method of contact.Due to there is no first layer metal contact above doped region, and because Kong Yuexiang depths is prolonged
Stretching becomes narrower, so the second layer contact 220 of single technique has wider hole on top.Because contact 220 compares
Be connected to gate electrode 208 contact 216 extend it is deeper, so hole is wider on top.If contact 216,220 that
The enough of this placement closely can then form electrical connection, and this may cause short circuit 222.
Stated differently, since the depth of contact 220, the critical dimension at the top of contact 220 is substantially different from contact
The critical dimension of 220 bottoms.But, in fig. 2, critical dimension and the first layer contact top at the top of metal contact element 218
Critical dimension it is substantially similar.
Fig. 3 is the flow chart for showing the illustrative methods for forming multiple layer metal contact in semiconductor devices.
According to this example, the method comprising the steps of 302, and first layer contact is formed in the first dielectric layer around at least one gate electrode
Part, first layer contact extends to the doped region of underlying substrate.This method further comprises step 304, in the first dielectric layer
Top forms the second dielectric layer.This method further comprises step 306, is formed through the second dielectric layer and extends to first layer contact
The second layer contact of part.
According to some illustrative examples, a kind of method that metal contact element is formed in semiconductor devices is included in around extremely
First layer contact is formed in first dielectric layer of a few gate electrode, first layer contact extends to the doped region of underlying substrate
Domain, in the first dielectric layer the second dielectric layer of formation, and forms the of first layer contact is extended to through the second dielectric layer
Two layers of contact.
According to some illustrative examples, semiconductor devices includes the substrate with doped region, around at least one in lining
First dielectric layer of the gate electrode formed on bottom, first layer contact of first dielectric layer including extending to doped region, and
First dielectric layer the second dielectric layer of formation, the second dielectric layer includes extending to first layer contact through the second dielectric layer
Second layer contact.
A kind of method that metal contact element is formed in semiconductor devices, which is included on substrate, forms gate electrode, in the substrate
The position of neighbouring gate electrode forms doped region, and the first dielectric layer is formed above gate electrode, and the is formed in the first dielectric layer
One layer of contact, the second dielectric layer is extended through to first layer in the first dielectric layer the second dielectric layer of formation, and formation
The second layer contact of contact so that there is step between first layer contact and second layer contact.
It should be understood that a variety of combinations of the embodiment and step listed by this paper can use in a different order or
It is used in parallel, and is crucial or necessary without special step.Although in addition, term used herein " electrode ", is answered
This recognizes that this term includes the concept of " electrode contact ".In addition, herein in connection with described by some embodiments and being begged for
The part of opinion can be combined with herein in connection with the part described and discussed in other embodiment.Therefore, all such implementations
Example is included within the scope of the present invention.
The part of multiple embodiments is discussed above, it will be understood by those skilled in the art that can easily make
With based on the present invention come design or change other be used for perform and embodiment identical purpose defined herein and/or realization
The processing of same advantage and structure.Those of ordinary skill in the art should also be appreciated that this equivalent constructions without departing from this hair
Bright spirit and scope, and without departing from the spirit and scope of the present invention, can carry out a variety of changes, replace with
And change.
Claims (20)
1. a kind of method for being used to form metal contact element in semiconductor devices, methods described includes：
Hard mask layer is directly formed in the opposing sidewalls and top surface of square gate electrode on a semiconductor substrate, wherein, the top surface
Extend between the opposing sidewalls, and the opposing sidewalls and top surface of the hard mask layer and the gate electrode are physically contacted；
It is square into the first dielectric layer on the semiconductor substrate so that first dielectric layer surrounds the gate electrode；
Interim dielectric layer is formed in the hard mask layer and first dielectric layer；
The hole for extending through the interim dielectric layer, the hard mask layer and first dielectric layer is formed, wherein, it is described to cover firmly
Mold layer limits the side wall in the hole, while being physically contacted with the opposing sidewalls of the gate electrode；
First layer contact is formed in the hole, and the first layer contact extends to the source of the doping of the Semiconductor substrate
Pole/drain region；
Formed in the hole after first layer contact, remove the interim dielectric layer with hard mask layer described in expose portion；
In first dielectric layer the second dielectric layer of formation；
Form the second layer contact that the first layer contact is extended to through second dielectric layer.
2. according to the method described in claim 1, further comprise：Formation extends to described first through second dielectric layer
The second layer contact of the gate electrode in dielectric layer.
3. according to the method described in claim 1, further comprise：Formed through second dielectric layer and extend to the grid electricity
Pole and the contact of the first layer contact.
4. according to the method described in claim 1, wherein, form the second layer contact, in the first layer contact and
Step is formed between the second layer contact.
5. according to the method described in claim 1, wherein, the critical dimension of the first layer contact is contacted with the second layer
The critical dimension of part is similar.
6. according to the method described in claim 1, wherein, the gate electrode include high-K metal gate electrode.
7. according to the method described in claim 1, further comprise：Second layer contact is formed, the second layer contact prolongs
Second dielectric layer and hard mask layer are extended through, the hard mask layer surrounds the gate electrode to be connected with the gate electrode.
8. method according to claim 6, wherein, the hard mask layer has selectivity relative to first dielectric layer
To be used to etch purpose.
9. a kind of semiconductor devices, including：
Substrate, including doped region；
First dielectric layer, around at least one gate electrode formed over the substrate, first dielectric layer includes extending to
The first layer contact of the doped region；
Second dielectric layer, is formed in first dielectric layer, second dielectric layer is included through second dielectric layer
Extend to the second layer contact of the first layer contact；And
Hard mask layer, in the opposing sidewalls and top surface of the gate electrode, the top surface extends in the opposing sidewalls
Between, the opposing sidewalls and top surface of the hard mask layer and the gate electrode are physically contacted.
10. device according to claim 9, further comprises extending to first dielectric through second dielectric layer
The second layer contact of the gate electrode in layer.
11. device according to claim 9, further comprises：Step, positioned at the first layer contact and described second
Between layer contact.
12. device according to claim 9, wherein, critical dimension and the second layer of the first layer contact connect
The critical dimension of contact element is similar.
13. device according to claim 9, wherein, the gate electrode includes high-K metal gate electrode.
14. device according to claim 9, wherein, cover the gate electrode using hard mask layer.
15. device according to claim 14, further comprises prolonging through second dielectric layer and the hard mask layer
Extend the second layer contact of the gate electrode in first dielectric layer.
16. device according to claim 14, wherein, the hard mask layer has selection relative to first dielectric layer
Property is used to etch purpose.
17. a kind of method for being used to form metal contact element in semiconductor devices, methods described includes：
The depositing gate electrode on substrate, the top surface that the gate electrode has opposing sidewalls and extended between opposing sidewalls；
The region of the neighbouring gate electrode in the substrate is doped to form doped region；
Hard mask layer is directly formed in the opposing sidewalls and top face of the gate electrode so that the hard mask layer and the grid
Opposing sidewalls and the top surface physical contact of electrode；
In the dielectric layer of gate electrode disposed thereon first；
Interim dielectric layer is formed in the hard mask layer and first dielectric layer；
The hole for extending through the interim dielectric layer, the hard mask layer and first dielectric layer is formed, wherein, it is described to cover firmly
Mold layer limits the side wall in the hole, while being physically contacted with the opposing sidewalls of the gate electrode；
First layer contact is formed in the hole；
Formed in the hole after first layer contact, remove the interim dielectric layer with hard mask layer described in expose portion；
In first dielectric layer the second dielectric layer of formation；
Form the second layer contact that the first layer contact is extended to through second dielectric layer so that described first
There is step between layer contact and the second layer contact.
18. method according to claim 17, further comprises：Formed through second dielectric layer and extend to described the
The second layer contact of the gate electrode in one dielectric layer.
19. method according to claim 17, wherein, critical dimension and the second layer of the first layer contact connect
The critical dimension of contact element is similar.
20. method according to claim 17, wherein, the gate electrode includes high-K metal gate electrode.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361775642P | 2013-03-10 | 2013-03-10 | |
| US61/775,642 | 2013-03-10 | ||
| US13/911,183 | 2013-06-06 | ||
| US13/911,183 US9337083B2 (en) | 2013-03-10 | 2013-06-06 | Multi-layer metal contacts |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104037122A CN104037122A (en) | 2014-09-10 |
| CN104037122B true CN104037122B (en) | 2017-08-15 |
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| CN101132008A (en) * | 2006-08-23 | 2008-02-27 | 三星电子株式会社 | Contact structure having a barrier layer containing noble metal, ferroelectric random access memory device employing the same and methods of fabricating the same |
| CN101345240A (en) * | 2007-07-09 | 2009-01-14 | 台湾积体电路制造股份有限公司 | Contact structure of MOS transistor, adjacent contact structure and semiconductor SRAM unit |
| CN101410967A (en) * | 2006-05-16 | 2009-04-15 | 国际商业机器公司 | Dual wired integrated circuit chips |
| CN101465346A (en) * | 2007-12-21 | 2009-06-24 | 东部高科股份有限公司 | Semiconductor device and method for manufacturing the device |
| CN102804387A (en) * | 2010-03-16 | 2012-11-28 | 国际商业机器公司 | Thin-BOX metal backgate extremely thin SOI device |
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| US8358012B2 (en) * | 2010-08-03 | 2013-01-22 | International Business Machines Corporation | Metal semiconductor alloy structure for low contact resistance |
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| CN101410967A (en) * | 2006-05-16 | 2009-04-15 | 国际商业机器公司 | Dual wired integrated circuit chips |
| CN101132008A (en) * | 2006-08-23 | 2008-02-27 | 三星电子株式会社 | Contact structure having a barrier layer containing noble metal, ferroelectric random access memory device employing the same and methods of fabricating the same |
| CN101345240A (en) * | 2007-07-09 | 2009-01-14 | 台湾积体电路制造股份有限公司 | Contact structure of MOS transistor, adjacent contact structure and semiconductor SRAM unit |
| CN101465346A (en) * | 2007-12-21 | 2009-06-24 | 东部高科股份有限公司 | Semiconductor device and method for manufacturing the device |
| CN102804387A (en) * | 2010-03-16 | 2012-11-28 | 国际商业机器公司 | Thin-BOX metal backgate extremely thin SOI device |
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