CN107293543A - Metal oxide semiconductor device and its manufacture method with double traps - Google Patents
Metal oxide semiconductor device and its manufacture method with double traps Download PDFInfo
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- CN107293543A CN107293543A CN201610200279.7A CN201610200279A CN107293543A CN 107293543 A CN107293543 A CN 107293543A CN 201610200279 A CN201610200279 A CN 201610200279A CN 107293543 A CN107293543 A CN 107293543A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 53
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 139
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 23
- 210000000746 body region Anatomy 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 100
- 238000009413 insulation Methods 0.000 claims description 37
- 239000003550 marker Substances 0.000 claims description 36
- 230000000295 complement effect Effects 0.000 claims description 22
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- 238000007254 oxidation reaction Methods 0.000 claims description 20
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- 238000005468 ion implantation Methods 0.000 description 41
- 238000002955 isolation Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention proposes a kind of metal oxide semiconductor device with double traps and its manufacture method.Wherein, the metal oxide semiconductor device with double traps is included：Semiconductor substrate, epitaxial layer, the first conductive type well, the first conductive type body region, the second conductive type well, grid, the first conductivity type are lightly doped diffusion region, the second conductivity type and diffusion region, the second conductivity type source electrode and the drain electrode of the second conductivity type are lightly doped.Wherein, the second conductive type well is in being adjacent to the first conductive type well in a transverse direction, and the second conductive type well and the first conductive type well formation PN junctions.Diffusion region is lightly doped in first conductivity type, with self-aligned processing step, is formed in the epitaxial layer in the first conductive type well.Diffusion region is lightly doped in second conductivity type, with self-aligned processing step, is formed in the epitaxial layer in the second conductive type well.Wherein, diffusion region is lightly doped positioned at the first conductivity type in PN junctions and the second conductivity type is lightly doped between diffusion region.
Description
Technical field
There are double traps the present invention relates to a kind of metal-oxide semiconductor (MOS) (metal oxide semiconductor,
MOS) element and its manufacture method, particularly relate to a kind of MOS elements for reducing conducting resistance and improving crash guard voltage and
Its manufacture method.
Background technology
Fig. 1 shows a kind of typical metal-oxide semiconductor (MOS) (metal oxide semiconductor, MOS) element
100 schematic cross-sectional view.As shown in figure 1, MOS elements 100 are included：P-type substrate 101, epitaxial layer 102, p-type trap 103a, insulation
Diffusion (lightly doped diffusion, LDD) area 105a and 105b, N-type source 106a, N-type is lightly doped in area 104, N-type
Drain 107a, p-type body zone 108a and grid 111a.Wherein, insulation layer 104 is zone oxidation (local oxidation of
Silicon, LOCOS) structure, to define NMOS element region 104a, main active region when being operated as MOS elements 100.NMOS
Element region 104a scope is in Fig. 1, the region shown in black solid line area marking arrow.MOS elements 100 are NMOS elements, its N
Type source electrode 106a is connected with the NLDD areas 105a of its homonymy, in addition, N-type drain 107a is connected with the NLDD areas 105b of its homonymy,
The region of both of the aforesaid connection, is separated by p-type trap 103a completely.Relatively, typical PMOS elements, that is, by NLDD areas
105a and 105b, N-type source 106a, it is changed to p-type with N-type drain 107a conductivity type, and p-type trap 103a and p-type body zone
108a conductivity type is changed to N-type.But because micro MOS component sizes are the trend of art technology progress, existing MOS elements
In the trend that channel shortens, it can produce and decline (drain-induced barrier comprising potential energy caused by drain electrode
Lowering, DIBL) with the short-channel effect (short of hot carrier's effect (hot carrier effect, HCE)
Channel effect, SCE), this is well known to those skilled in the art, and will not be described here.
Fig. 8 shows a kind of typical CMOS (complementary metal oxide
Semiconductor, CMOS) element 600 schematic cross-sectional view.As shown in figure 8, cmos element 600 is included：P-type semiconductor base
Diffusion (N-type lightly are lightly doped in plate 101, epitaxial layer 102, p-type trap 103a, N-type trap 103b, insulation layer 104, N-type
Doped diffusion, NLDD) diffusion (P-type lightly doped are lightly doped in area 105a and 105b, p-type
Diffusion, PLDD) area 105c and 105d, N-type source 106a, p-type source electrode 106b, N-type drain 107a, p-type drain electrode 107b, P
Type body zone 108a, N-type body zone 108b, grid 111a and grid 111b.Wherein, insulation layer 104 is zone oxidation (local
Oxidation of silicon, LOCOS) structure, to define NMOS element regions 104a and PMOS element region 104b, it is used as CMOS
The operating space main when operating of element 100.NMOS element regions 104a and PMOS element regions 104b scope is in Fig. 1, thick black arrow
Head is illustrated.Cmos element 600 includes NMOS element regions 104a and PMOS element regions 104b.In NMOS element regions 104a, its N
Type source electrode 106a is corresponding thereto in the NLDD areas 105a connections of grid 111a homonymies, in addition, N-type drain 107a is corresponding thereto in grid
The NLDD areas 105b connections of pole 111a homonymies, the region of both of the aforesaid connection, are separated by p-type trap 103a completely.Relatively, exist
In PMOS element regions 104b, its p-type source electrode 106b is corresponding thereto in the PLDD areas 105c connections of grid 111b homonymies, in addition, p-type
107b drain corresponding thereto in the PLDD areas 105d connections of grid 111b homonymies, the region of both of the aforesaid connection, completely by N-type trap
103b is separated.Because micro cmos element size is the trend of art technology progress, existing cmos element shortens in channel
Trend in, can produce comprising drain electrode caused by potential energy decline (drain-induced barrier lowering, DIBL) with
The short-channel effect (short channel effect, SCE) of hot carrier's effect (hot carrier effect, HCE), this
It is well known to those skilled in the art, will not be described here.
In general, so that gate operational voltage is 5V MOS element as an example, when the passage length that grid length is illustrated is low
When 0.6 micron (μm), it can start SCE occur, to avoid SCE, then grid length can not continue to shorten, and have at present certainly perhaps
Many others modes solve this SCE, still, if desired keep operating voltage in 5V or so, for example, are integrated with other power components
In a circuit, or when being used as power component with multiple MOS elements in parallel, then need to solve both to need gate operational voltage
The problem of maintaining such as 5V or so, avoid SCE again, and allow the MOS elements to continue micro.
In view of this, improvement of the present invention i.e. for above-mentioned prior art, propose a kind of MOS elements with double traps and its
Manufacture method, it can reduce conducting resistance and improve crash guard voltage.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art and defect, propose a kind of MOS elements with double traps and
Its manufacture method, it can reduce conducting resistance and improve crash guard voltage.
For up to above-mentioned purpose, just a wherein viewpoint is sayed, is partly led the invention provides a kind of metal oxide with double traps
Body (Metal Oxide Semiconductor, MOS) element, comprising：Semiconductor substrate, on a longitudinal direction, with relative
One upper surface and a lower surface；One epitaxial layer, is formed on the substrate, on the longitudinal direction, outside with respect to the one of the upper surface
Prolong layer surface, and the epitaxial layer is stacked and is connected on the upper surface；One first conductive type well, is formed in the epitaxial layer, and
In on the longitudinal direction, below the epi-layer surface；One first conductive type body region, this being formed in the epitaxial layer first is led
On electric type trap, and on the longitudinal direction, stacking and be connected between first conductive type well and the epi-layer surface；One second is conductive
Type trap, is formed in the epitaxial layer, and on the longitudinal direction, below the epi-layer surface, and in being adjacent to this in a transverse direction
First conductive type well, and second conductive type well and first conductive type well, one PN junctions of formation；One grid, is formed at the extension
In layer surface, on the longitudinal direction, the gate stack is simultaneously connected in the epi-layer surface；Diffusion is lightly doped in one first conductivity type
Area, with self-aligned processing step, is formed in the epitaxial layer in first conductive type well, and on the longitudinal direction, stacks simultaneously
It is connected between first conductive type well and the epi-layer surface；Diffusion region is lightly doped in one second conductivity type, with self-aligned work
Skill step, is formed in the epitaxial layer in second conductive type well, and second conductive on the longitudinal direction, stacking and being connected to this
Between type trap and the epi-layer surface；One second conductivity type source electrode, is formed in the epitaxial layer in first conductive type well, and
In on the longitudinal direction, stacking and be connected between first conductive type well and the epi-layer surface, and in the transverse direction, it is connected to this
First conductive type body region and first conductivity type are lightly doped between diffusion region；And one second conductivity type drain electrode, be formed at this
In the epitaxial layer in second conductive type well, and on the longitudinal direction, stacking and be connected to second conductive type well and the epitaxial layer
Between surface, and in the transverse direction, diffusion region is lightly doped with second conductivity type and is connected；Wherein, the PN junctions be located at this first
Diffusion region is lightly doped in conductivity type and second conductivity type is lightly doped between diffusion region.
Up to above-mentioned purpose, to be sayed with regard to another viewpoint, the invention provides a kind of metal-oxide semiconductor (MOS) with double traps
(Metal Oxide Semiconductor, MOS) manufacturing method, comprising：Semiconductor substrate is provided, it is in a longitudinal direction
On, with a relative upper surface and a lower surface；An epitaxial layer is formed on the semiconductor substrate, and on the longitudinal direction, tool
There is an epi-layer surface of the relative upper surface, and the epitaxial layer is stacked and is connected on the upper surface；Form one first conductive
Type trap is in the epitaxial layer, and on the longitudinal direction, below the epi-layer surface；One first conductive type body region is formed in this
In first conductive type well in epitaxial layer, and on the longitudinal direction, stacking and be connected to first conductive type well and the epitaxial layer
Between surface；One second conductive type well is formed in the epitaxial layer, and on the longitudinal direction, second conductive type well is located at the extension
Below layer surface, and in being adjacent to first conductive type well, and second conductive type well and first conductive type well in a transverse direction
Form a PN junctions；A grid is formed in the epi-layer surface, on the longitudinal direction, the gate stack is simultaneously connected to the epitaxial layer
On surface；With self-aligned processing step, form one first conductivity type and diffusion region is lightly doped in being somebody's turn to do in first conductive type well
In epitaxial layer, and on the longitudinal direction, stacking and be connected between first conductive type well and the epi-layer surface；With self-aligned
Processing step, forms one second conductivity type and diffusion region is lightly doped in the epitaxial layer in second conductive type well, and vertical in this
Upwards, stack and be connected between second conductive type well and the epi-layer surface；Formed one second conductivity type source electrode in this
In the epitaxial layer in one conductive type well, and on the longitudinal direction, stacking and be connected to first conductive type well and the epitaxial layer table
Between face, and in the transverse direction, being connected to first conductive type body region and first conductivity type is lightly doped between diffusion region；With
And one second conductivity type of formation drains in the epitaxial layer in second conductive type well, and on the longitudinal direction, stack and connect
Between second conductive type well and the epi-layer surface, and in the transverse direction, diffusion region is lightly doped with second conductivity type and connects
Connect；Wherein, diffusion region is lightly doped positioned at first conductivity type in the PN junctions and second conductivity type is lightly doped between diffusion region.
In wherein a kind of preferably implementation kenel, the metal oxide semiconductor device also includes an insulation layer, is formed
In on the epitaxial layer, to define a MOS element regions, and first conductive type body region, the grid, first conductivity type are lightly doped
Diffusion region, second conductivity type are lightly doped diffusion region, the second conductivity type source electrode, are located at the MOS with second conductivity type drain electrode
In element region.
In wherein a kind of preferably implementation kenel, the insulation layer is zone oxidation (local oxidation of
Silicon, LOCOS) structure or shallow trench isolation (shallow trench isolation, STI) structure.
The impurity doping concentration that diffusion region is lightly doped in first conductivity type in wherein a kind of preferably implementation kenel is higher than
The impurity doping concentration of first conductive type well, and second conductivity type be lightly doped the impurity doping concentration of diffusion region higher than this
The impurity doping concentration of two conductive type wells.
In wherein a kind of preferably implementation kenel, the metal oxide semiconductor device is also buried comprising one second conductivity type
Layer, is formed in the substrate and the epitaxial layer, and on the longitudinal direction, being connected to below first conductive type well.
Up to above-mentioned purpose, to be sayed with regard to another viewpoint, the invention provides a kind of complementary metal-oxide with double traps
Semiconductor (Complementary Metal Oxide Semiconductor, CMOS) element, comprising：Semiconductor substrate, in
On one longitudinal direction, with a relative upper surface and a lower surface；One epitaxial layer, is formed on the semiconductor substrate, in the longitudinal direction
On, the epi-layer surface with the relative upper surface, and the epitaxial layer stacks and is connected on the upper surface；One insulation layer,
It is formed on the epitaxial layer, the epi region is divided into a NMOS element regions and a PMOS element regions；One first p-type trap,
The NMOS element regions in the epitaxial layer are formed at, and on the longitudinal direction, below the epi-layer surface；One p-type body zone,
It is formed on the first p-type trap in the epitaxial layer, and on the longitudinal direction, stacking and be connected to the first p-type trap and the extension
Between layer surface；One first N-type trap, is formed at the NMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the extension
Below layer surface, and in being adjacent to the first p-type trap, and first N-type trap and the first p-type trap formation one first in a transverse direction
PN junctions；One first grid, is formed at the NMOS element regions in the epi-layer surface, on the longitudinal direction, the first grid heap
Fold and be connected in the epi-layer surface；Diffusion (lightly doped diffusion, LDD) area is lightly doped in one first p-type,
With self-aligned processing step, it is formed in the epitaxial layer on the first p-type trap, and on the longitudinal direction, stack and be connected to
Between the first p-type trap and the epi-layer surface；One first N-type be lightly doped diffusion (lightly doped diffusion,
LDD) area, with self-aligned processing step, is formed in the epitaxial layer in first N-type trap, and on the longitudinal direction, stacks simultaneously
It is connected between first N-type trap and the epi-layer surface；One N-type source, is formed at the epitaxial layer on the first p-type trap
In, and on the longitudinal direction, stacking and be connected between the first p-type trap and the epi-layer surface, and in the transverse direction, be connected to
The p-type body zone and first p-type are lightly doped between diffusion region；One N-type drain, is formed at the extension in first N-type trap
In layer, and on the longitudinal direction, stacking and be connected between first N-type trap and the epi-layer surface, and in the transverse direction, with this
Diffusion region connection is lightly doped in first N-type；One second N-type trap, is formed at the PMOS element regions in the epitaxial layer, and in the longitudinal direction
On, below the epi-layer surface；One N-type body zone, is formed in second N-type trap in the epitaxial layer, and vertical in this
Upwards, stack and be connected between second N-type trap and the epi-layer surface；One second p-type trap, is formed in the epitaxial layer
The PMOS element regions, and on the longitudinal direction, below the epi-layer surface, and in being adjacent to second N-type trap in the transverse direction,
And second N-type trap and the second p-type trap one the 2nd PN junctions of formation；One second grid, is formed in the epi-layer surface
The PMOS element regions, on the longitudinal direction, the second grid is stacked and is connected in the epi-layer surface；One second N-type is lightly doped
(lightly doped diffusion, LDD) area is spread, with self-aligned processing step, is formed in second N-type trap
In the epitaxial layer, and on the longitudinal direction, stacking and be connected between second N-type trap and the epi-layer surface；One second p-type is light
Doping diffusion (lightly doped diffusion, LDD) area, with self-aligned processing step, is formed at the second p-type trap
On the epitaxial layer in, and on the longitudinal direction, stacking and be connected between the second p-type trap and the epi-layer surface；One p-type source
Pole, is formed in the epitaxial layer in second N-type trap, and outer with this on the longitudinal direction, stacking and being connected to second N-type trap
Prolong between layer surface, and in the transverse direction, being connected to the N-type body zone and second N-type is lightly doped between diffusion region；One p-type
Drain electrode, be formed in the epitaxial layer on the second p-type trap, and on the longitudinal direction, stack and be connected to the second p-type trap with should
Between epi-layer surface, and in the transverse direction, diffusion region is lightly doped with second p-type and is connected；And a marker space, it is connected to this
Between NMOS element regions and the PMOS element regions, and its depth, calculate downwards, be not less than since the longitudinal direction the epi-layer surface
The first p-type trap, first N-type trap, second N-type trap, the depth with any region of the second p-type trap；Wherein, this first
Diffusion region is lightly doped positioned at first p-type for PN junctions and first N-type is lightly doped between diffusion region；Wherein, the 2nd PN junctions
Diffusion region is lightly doped positioned at second p-type and second N-type is lightly doped between diffusion region.
Up to above-mentioned purpose, to be sayed with regard to another viewpoint, the invention provides a kind of complementary metal-oxide with double traps
Semiconductor (Metal Oxide Semiconductor, MOS) manufacturing method, comprising：There is provided semiconductor substrate, its in
On one longitudinal direction, with a relative upper surface and a lower surface；An epitaxial layer is formed on the semiconductor substrate, and in the longitudinal direction
On, the epi-layer surface with the relative upper surface, and the epitaxial layer stacks and is connected on the upper surface；One is formed to insulate
On the Qu Yu epitaxial layers, the epi region is divided into a NMOS element regions and a PMOS element regions；Form one first p-type trap
The NMOS element regions in the epitaxial layer, and on the longitudinal direction, below the epi-layer surface；Form a p-type body zone
On the first p-type trap in the epitaxial layer, and on the longitudinal direction, stacking and be connected to the first p-type trap and the epitaxial layer table
Between face；The NMOS element regions of one first N-type trap in the epitaxial layer are formed, and on the longitudinal direction, positioned at the epitaxial layer table
Below face, and in being adjacent to the first p-type trap in a transverse direction, and first N-type trap forms one the oneth PN with the first p-type trap and connect
Face；A first grid is formed in the NMOS element regions in the epi-layer surface, on the longitudinal direction, the first grid is stacked and connected
It is connected in the epi-layer surface；With self-aligned processing step, form one first p-type and diffusion (lightly doped are lightly doped
Diffusion, LDD) area is in the epitaxial layer on the first p-type trap, and on the longitudinal direction, stacking and be connected to the first P
Between type trap and the epi-layer surface；With self-aligned processing step, form one first N-type and diffusion (lightly is lightly doped
Doped diffusion, LDD) area in the epitaxial layer in first N-type trap, and on the longitudinal direction, stacks and is connected to this
Between first N-type trap and the epi-layer surface；A N-type source is formed in the epitaxial layer on the first p-type trap, and it is vertical in this
Upwards, stack and be connected between the first p-type trap and the epi-layer surface, and in the transverse direction, being connected to the p-type body zone
It is lightly doped with first p-type between diffusion region；A N-type drain is formed in the epitaxial layer in first N-type trap, and it is vertical in this
Upwards, stack and be connected between first N-type trap and the epi-layer surface, and in the transverse direction, be lightly doped with first N-type
Diffusion region is connected；The PMOS element regions of one second N-type trap in the epitaxial layer are formed, and on the longitudinal direction, positioned at the extension
Below layer surface；A N-type body zone is formed in second N-type trap in the epitaxial layer, and on the longitudinal direction, stacks and connects
Between second N-type trap and the epi-layer surface；The PMOS element regions of one second p-type trap in the epitaxial layer are formed, and
In on the longitudinal direction, below the epi-layer surface, and in being adjacent to second N-type trap in the transverse direction, and second N-type trap with
The second p-type trap, one the 2nd PN junctions of formation；A second grid is formed in the PMOS element regions in the epi-layer surface, in this
On longitudinal direction, the second grid is stacked and is connected in the epi-layer surface；With self-aligned processing step, one second N-type is formed
Diffusion (lightly doped diffusion, LDD) area is lightly doped in the epitaxial layer in second N-type trap, and it is vertical in this
Upwards, stack and be connected between second N-type trap and the epi-layer surface；With self-aligned processing step, one the 2nd P is formed
Diffusion (lightly doped diffusion, LDD) area is lightly doped in the epitaxial layer on the second p-type trap in type, and in this
On longitudinal direction, stack and be connected between the second p-type trap and the epi-layer surface；A p-type source electrode is formed in second N-type trap
The epitaxial layer in, and on the longitudinal direction, stacking and be connected between second N-type trap and the epi-layer surface, and in the horizontal stroke
Upwards, it is connected to the N-type body zone and second N-type is lightly doped between diffusion region；P-type drain electrode is formed, in the second p-type trap
On the epitaxial layer in, and on the longitudinal direction, stacking and be connected between the second p-type trap and the epi-layer surface, and in this
In transverse direction, diffusion region is lightly doped with second p-type and is connected；And a marker space is formed, the NMOS element regions are connected to being somebody's turn to do
Between PMOS element regions, and its depth, calculated downwards since the longitudinal direction the epi-layer surface, be not less than the first p-type trap, be somebody's turn to do
First N-type trap, second N-type trap, the depth with any region of the second p-type trap；Wherein, the first PN junctions be located at this
Diffusion region is lightly doped in one p-type and first N-type is lightly doped between diffusion region；Wherein, the 2nd PN junctions are light positioned at second p-type
Doped diffusion region and second N-type are lightly doped between diffusion region.
In wherein a kind of preferably implementation kenel, the insulation layer is zone oxidation (local oxidation of
Silicon, LOCOS) structure or shallow trench isolation (shallow trench isolation, STI) structure.
In wherein a kind of preferably implementation kenel, the impurity doping concentration of diffusion region is lightly doped higher than this in first p-type
The impurity doping concentration of first p-type trap, and the impurity doping concentration of diffusion region is lightly doped higher than first N-type trap in first N-type
Impurity doping concentration.
In wherein a kind of preferably implementation kenel, the impurity doping concentration of diffusion region is lightly doped higher than this in second p-type
The impurity doping concentration of second p-type trap, and the impurity doping concentration of diffusion region is lightly doped higher than second N-type trap in second N-type
Impurity doping concentration.
In wherein a kind of preferably implementation kenel, there should be the complementary metal oxide semiconductor element of double traps, also
Comprising a n type buried layer, be formed in the substrate and the epitaxial layer, and positioned at its junction, and on the longitudinal direction, be connected to this second
Below p-type trap.
In wherein a kind of preferably implementation kenel, the marker space includes a deep trench insulated (deep trench
Isolation, DTI) structure.
In wherein a kind of preferably implementation kenel, the marker space includes：One p-type marker space, is formed in the epitaxial layer
The NMOS element regions, and on the longitudinal direction, below the epi-layer surface, and in being adjacent to first N-type in the transverse direction
Trap；And a N-type marker space, the PMOS element regions in the epitaxial layer are formed at, and on the longitudinal direction, positioned at the epitaxial layer table
Below face, and in being adjacent to the second p-type trap in the transverse direction.
Below by way of specific embodiment elaborate, when be easier to understand the purpose of the present invention, technology contents, feature and its
The effect reached.
Brief description of the drawings
Fig. 1 shows a kind of existing MOS elements 100；
One embodiment of Fig. 2 display present invention；
Second embodiment of Fig. 3 A-3H display present invention；
The 3rd embodiment of Fig. 4 display present invention；
The 4th embodiment of Fig. 5 display present invention；
The 5th embodiment of Fig. 6 display present invention；
Fig. 7 A-7C show the indicatrix ratio of prior art MOS elements and the element characteristic of the MOS elements according to the present invention
Relatively scheme；
Fig. 8 shows a kind of existing cmos element 600；
The 6th embodiment of Fig. 9 display present invention；
The 7th embodiment of Figure 10 A-10I display present invention；
The 8th embodiment of Figure 11 display present invention；
The 9th embodiment of Figure 12 display present invention；
The tenth embodiment of Figure 13 display present invention.
Symbol description in figure
100,200,300,400,500 MOS elements
101,201 semiconductor substrates
201a upper surfaces
201b lower surfaces
102,202 epitaxial layers
202a epi-layer surfaces
103a, 203a, 203d p-type trap
103b, 203b, 203c N-type trap
104,204 insulation layers
104a, 204a NMOS element regions
104b, 204b PMOS element regions
105c, 105d, 205a, 205d PLDD areas
105a, 105b, 205b, 205c NLDD areas
106a, 206a N-type source
106b, 206b p-type source electrode
107a, 207a N-type drain
107b, 207b p-type drain
108a, 208a p-type body zone
108b, 208b N-type body zone
111a, 111b, 211a, 211b grid
209,213 n type buried layers
212a, 212b PN junctions
213 ' n type buried layer ion implantation regions
214 marker spaces
214a p-types marker space
214b N-types marker space
400,500,600,700,800,900,1000 cmos elements
Di, di ' gate dielectric
Sp, sp ' gate spacer layer
St, st ' gate stack
Embodiment
Schema in the present invention belongs to signal, is mostly intended to represent that the order up and down between processing step and each layer is closed
System, as shape, thickness and width then and not according to ratio drafting.
One embodiment of Fig. 2 display present invention, shows and is partly led according to the metal oxide with double traps of the present invention
The schematic cross-sectional view of body (Metal Oxide Semiconductor, MOS) element 200.As shown in Fig. 2 MOS elements 200, bag
Contain：Diffusion (P-type is lightly doped in semiconductor substrate 201, epitaxial layer 202, p-type trap 203a, N-type trap 203c, insulation layer 204, p-type
Lightly doped diffusion, PLDD) diffusion (N-type lightly doped are lightly doped in area 205a, N-type
Diffusion, NLDD) area 205b, N-type source 206a, N-type drain 207a, p-type body zone 208a and with gate pole 211a.
Wherein, semiconductor substrate 201 is in longitudinally upper (direction as shown in thick black dotted line arrow in figure), with relative upper
Surface 201a and lower surface 201b.Epitaxial layer 202 is formed on semiconductor substrate 201, and on longitudinal direction, stacking and be connected to
On the 201a of surface, the epi-layer surface 202a with opposing upper 201a.P-type trap 203a is formed in epitaxial layer 202, and in
On longitudinal direction, below epi-layer surface 202a.
P-type body zone 208a is formed on the p-type trap 203a in epitaxial layer 202, and on longitudinal direction, stacking and be connected to P
Between type trap 203a and epi-layer surface 202a.N-type trap 203c is formed in epitaxial layer 202, and on longitudinal direction, positioned at epitaxial layer
Below the 202a of surface, and p-type trap 203a, and N-type trap are adjacent in laterally upper (direction as shown in thick black solid arrow in figure)
203c and p-type trap 203a is abutted and is formed PN junctions 212a.Grid 211a is formed on epi-layer surface 202a, on longitudinal direction,
Grid 211a is stacked and is connected on epi-layer surface 202a.Wherein, grid 211a comprising dielectric layer di, stack layer st and
Interlayer sp.Dielectric layer di is formed on epi-layer surface 202a, and is connected with epi-layer surface 202a.Stack layer st is formed at Jie
On electric layer di, comprising conductive material, to the electrical contact as grid 211a, it can act also as forming PLDD areas 205a, NLDD
Self-aligned shielding during area 205b.Wall sp is formed on the epi-layer surface 202a outside stack layer st side wall, cladding
Stack layer st side wall, comprising insulating materials, can act also as being formed self-aligned during N-type source 206a and N-type drain 207a
Shielding.
PLDD areas 205a, with self-aligned processing step, is formed in the epitaxial layer 202 on p-type trap 203a, and in longitudinal direction
On, stack and be connected between p-type trap 203a and epi-layer surface 202a.NLDD areas 205b, with self-aligned processing step, shape
Into in the epitaxial layer 202 on N-type trap 203c, and on longitudinal direction, stacking and be connected to N-type trap 203c and epi-layer surface 202a
Between.N-type source 206a is formed in the epitaxial layer 202 on p-type trap 203a, and on longitudinal direction, stacking and be connected to p-type trap
Between 203a and epi-layer surface 202a, and between p-type body zone 208a and PLDD area 205a in transverse direction, are connected to.N-type is leaked
Pole 207a is formed in the epitaxial layer 202 on N-type trap 203c, and on longitudinal direction, stacking and be connected to N-type trap 203c and epitaxial layer
Between the 202a of surface, and in transverse direction, it is connected with NLDD areas 205b.Wherein, PN junctions 212a is located at PLDD areas 205a and NLDD
Between area 205b, and PN junctions 212a is in the range of the operating space 204a of MOS elements 200, completely separated PLDD areas 205a with
NLDD areas 205b.
Wherein, insulation layer 204 is for example formed on epitaxial layer 202, with defining operation area 204a, and p-type body zone 208a,
Grid 211a, PLDD areas 205a, NLDD area 205b, N-type source 206a and N-type drain 207a are located in operating space 204a.This
Outside, it should be noted that, in a kind of preferably embodiment, PLDD areas 205a except with N-type source 206a and dielectric layer di adjoinings
Outside, only abutted with p-type trap 203a；And NLDD areas 205b except with N-type drain 207a and dielectric layer di adjoining in addition to, only and N
Type trap 203c is abutted.
A kind of preferably embodiment, for example, wherein PLDD areas 205a impurity doping concentration is higher than p-type trap 203a
Impurity doping concentration, and NLDD areas 205b impurity doping concentration be higher than N-type trap 203c impurity doping concentration.Citing and
Speech, PLDD areas 205a impurity doping concentration 2 to 10 times of the impurity doping concentration higher than p-type trap 203a, and NLDD areas 205b's
Impurity doping concentration is higher than N-type trap 203c 2 to 10 times of impurity doping concentration.Wherein, doping concentration is referred to for example in ion
It is implanted into processing step, performed plane doping concentration, it is however generally that, this plane doping concentration, numerical value can be higher than in conduct
Three-dimensional doping concentration after (anneal) thermal process step of annealing function, this is well known to those skilled in the art, herein
It will not go into details.So arrange, the HCE in SCE can be relaxed.
Second embodiment of Fig. 3 A-3H display present invention.Fig. 3 A-3H show the metal with double traps according to the present invention
The schematic cross-sectional view of the manufacture method of oxide-semiconductor devices 200.First, as shown in Figure 3A there is provided semiconductor substrate 201, its
In, semiconductor substrate 201 is such as, but not limited to P-type silicon substrate, can also be other semiconductor substrates certainly.Semiconductor substrate
201 in longitudinally upper (direction as shown in thick black dotted line arrow in figure), with relative upper surface 201a and lower surface 201b.Connect
As shown in Figure 3 B, form epitaxial layer 202 on semiconductor substrate 201, and on longitudinal direction, it is outer with opposing upper 201a
Prolong layer surface 202a, epitaxial layer 202 is stacked and is connected on the 201a of upper surface.
Next, please continue to refer to Fig. 3 B.As shown in Figure 3 B, p-type trap 203a is formed in epitaxial layer 202, and in longitudinal direction
On, stack and be connected on the upper surface 201a of semiconductor substrate 201.Then, N-type trap 203c is formed in epitaxial layer 202, and
In on longitudinal direction, N-type trap 203c is located at below epi-layer surface 202a, and in being adjacent to p-type trap 203a in transverse direction.N-type trap 203c
With p-type trap 203a formation PN junctions 212a.Wherein, PN junctions 212a is located at the PLDD areas formed in subsequent process steps
Between 205a and NLDD areas 205b.The method for forming p-type trap 203a and N-type trap 203c, such as, but not limited to photoetching process, from
Sub- implantation technique and thermal process formation (not shown), this is well known to those skilled in the art, and will not be described here.
Next, as shown in Figure 3 C, insulation layer 204 is formed on epitaxial layer 202, with defining operation area 204a, and rear
P-type body zone 208a, grid 211a, PLDD areas 205a, NLDD area 205b, N-type source 206a and N formed in continuous technique
Type drain electrode 207a is all located in operating space 204a.Wherein, insulation layer 204 is zone oxidation (local as depicted
Oxidation of silicon, LOCOS) structure or shallow trench isolation (shallow trench isolation, STI) knot
Structure.Next, as shown in Figure 3 D, dielectric layer di and stack layer st is formed on epi-layer surface 202a, and on longitudinal direction, dielectric
Layer di is stacked and is connected on epi-layer surface 202a, and stack layer st is stacked and is connected on dielectric layer di.
Next, as shown in FIGURE 3 E, using dielectric layer di and stack layer st and photoresist layer 205a ' as shielding, to define
PLDD areas 205a ion implantation region, and with ion implantation technology step, by p type impurity, in the form of accelerating ion, implantation is fixed
To form PLDD areas 205a ion implantation region in the region of justice.Next, as illustrated in Figure 3 F, with dielectric layer di, stack layer st
And photoresist layer 205b ' is as shielding, to define NLDD areas 205b ion implantation region, and with ion implantation technology step, by N
Type impurity, in the form of accelerating ion (in such as figure compared with thin dotted line arrow to be illustrated), is implanted into the region of definition to form NLDD
Area 205b ion implantation region.
Next, as shown in Figure 3 G, N-type source 206a is formed in the epitaxial layer 202 on p-type trap 203a, and it is vertical in this
Upwards, stack and be connected between p-type trap 203a and epi-layer surface 202a, and in transverse direction, being connected to p-type body zone 208a
Between PLDD areas 205a.It should be noted that, in the ion implantation technology step for forming N-type source 206a, as shown in Figure 3 G,
Using wall sp, stack layer st and photoresist layer 206a ' as shielding, to define N-type source 206a ion implantation region, and with
Ion implantation technology step, by N-type impurity, (to be illustrated in the form of accelerating ion in such as figure compared with thin dotted line arrow), implantation is fixed
To form N-type source 206a ion implantation region in the region of justice.It should be noted that, form being ion implanted for N-type source 206a
Processing step, such as, to control to accelerate ion direct of travel, have an angle of inclination, by portion relative to epi-layer surface 202a
Divide in the epitaxial layer 202 below N-type impurity implantation wall sp, with the phenomenon for avoiding passage from being not turned on.
Next, as shown in figure 3h, p-type body zone 208a is formed on the p-type trap 203a in epitaxial layer 202, and in vertical
Upwards, stack and be connected between p-type trap 203a and epi-layer surface 202a；N-type drain 207a is formed on N-type trap 203c
In epitaxial layer 202, and on longitudinal direction, stacking and be connected between N-type trap 203c and epi-layer surface 202a, and in transverse direction,
It is connected with NLDD areas 205b；Wherein, PN junctions 212a is located between PLDD areas 205a and NLDD areas 205b.Certainly, N-type leakage is formed
Pole 207a ion implantation technology step, can be integrated into same with formation N-type source 206a ion implantation technology step
Processing step, will be described in detail in rear.
A kind of preferably embodiment, for example, wherein PLDD areas 205a impurity doping concentration is higher than p-type trap 203a
Impurity doping concentration, and NLDD areas 205b impurity doping concentration be higher than N-type trap 203c impurity doping concentration.Citing and
Speech, PLDD areas 205a impurity doping concentration 2 to 10 times of the impurity doping concentration higher than p-type trap 203a, and NLDD areas 205b's
Impurity doping concentration is higher than N-type trap 203c 2 to 10 times of impurity doping concentration.Wherein, doping concentration is referred to for example in ion
It is implanted into processing step, performed plane doping concentration, it is however generally that, this plane doping concentration, numerical value can be higher than in conduct
Three-dimensional doping concentration after the thermal process step of (anneal) function of annealing, this is well known to those skilled in the art, herein
It will not go into details.So arrange, the HCE in SCE can be relaxed.
The 3rd embodiment of Fig. 4 display present invention.The present embodiment shows the section view of the MOS elements 300 according to the present invention
Schematic diagram.Implement sharp difference with first to be, the MOS elements 300 of the present embodiment also include n type buried layer 209, are formed at
In substrate 201 and epitaxial layer 202, and positioned at its junction, and on the longitudinal direction, being connected to below p-type trap 203a.Its object is to
P-type trap 203a and semiconductor substrate 201 electrically are separated, to avoid p-type trap 203a from being electrically directly connected to semiconductor substrate 201,
The mistake on electrically is caused, especially when semiconductor substrate 201 has P-type conduction type.
The 4th embodiment of Fig. 5 display present invention.The present embodiment shows the section view of the MOS elements 400 according to the present invention
Schematic diagram.The present embodiment is intended to explanation according to the present invention, forms the mode of insulation layer 204, however it is not limited to such as one embodiment
It is shown.The present embodiment is with one embodiment difference, as shown in figure 5, insulation layer 204 is shallow trench isolation
In (shallow trench isolation, STI) structure rather than such as one embodiment, insulation layer 204 is zone oxidation
(local oxidation of silicon, LOCOS) structure.Other techniques are identical with one embodiment, form such as Fig. 5
Shown MOS elements 400.
The 5th embodiment of Fig. 6 display present invention.The present embodiment shows the section view of the MOS elements 500 according to the present invention
Schematic diagram.The present embodiment is intended to explanation according to the present invention, forms N-type drain 207a ion implantation technology step, can be with shape
Ion implantation technology step into N-type source 206a is integrated into same processing step, and this causes N-type impurity, is forming N-type leakage
Also such as similar in N-type source 206a during the 207a of pole, it accelerates ion direct of travel, to have relative to epi-layer surface 202a
One angle of inclination, part N-type impurity is implanted into the epitaxial layer 202 below wall sp, as shown in fig. 6, consequently, it is possible to can save
The processing step for independently forming N-type drain 207a in addition is saved, to reduce manufacturing cost.
It should be noted that, the present invention is in many features, unlike the prior art.It is described as follows with one embodiment：
Compare the prior art MOS elements 100 and MOS elements 200 according to first embodiment of the invention shown in Fig. 1, according to this hair
Bright MOS elements 200 mainly have following three points with the difference of prior art MOS elements 100：
1. there are double traps of different conductivity types according to the MOS elements 200 of the present invention, wherein, p-type trap 203a is in N-type source
206a is relative to PN junction 212a homonymies；And N-type trap 203c in N-type drain 207a relative to PN junction 212a homonymies；
2. there are double LDD regions of different conductivity types according to the MOS elements 200 of the present invention, wherein, PLDD areas 205a is in p-type
Trap 203a is relative to PN junction 212a homonymies；And NLDD areas 205b in N-type trap 203c relative to PN junction 212a homonymies；
3. there is the PN junctions 212a formed by p-type trap 203a and N-type trap 203c according to the MOS elements 200 of the present invention, it is preceding
State " homonymy ", that is, refer in PN junctions 212a the same side.And PN junctions 212a between PLDD areas 205a and NLDD areas 205b it
Between.
In the normal operating of prior art MOS elements 100, grid 111a grid bias is put on, in p-type trap 103
At grid 111a dielectric layer di junction, attract conducting currier and form passage (as shown in black dotted lines wire in Fig. 1
Meaning), grid bias changes, then the quantity of conducting currier changes in passage, and causing passage (channel), nearby electric field changes
Become, channel characteristic is changed, cause electric current to change.This is well known to those skilled in the art, and will not be described here.And root
According to the MOS elements 200 of the present invention, its channel is to be determined by p-type trap 203a with N-type source 206a, rather than such as prior art MOS
The channel of element 100 is the NLDD areas 105b by the NLDD areas 105a with N-type source 106a homonymies and with N-type drain 107a homonymies
Determined.Illustrated according to black dotted lines wire in the channel such as Fig. 2 of the MOS elements 200 of the present invention, and element spacing
(pitch), represented with grid length, can reach identical it is electrical when it is relatively short, that is, passage it is relatively short, this makes
Conducting resistance it is relatively low, and due to PLDD areas 205a impurity doping concentration be higher than p-type trap 203a impurity doping concentration,
Therefore SCE is successfully inhibited.In addition, in prior art MOS elements 100, it collapses the NLDD areas for betiding drain electrode 107a ends
Junction between 105b and p-type trap 103a, because NLDD areas 105b impurity doping concentration is of a relatively high, therefore its breakdown voltage phase
To relatively low.And according to the MOS elements 200 of the present invention, it collapses (breakdown) and betides PN junction 212a, due to N-type trap
203c impurity doping concentration is relatively low, therefore its breakdown voltage is of a relatively high, hot carrier (hot carrier) effect
It is suppressed relatively.
Fig. 7 A show that prior art MOS elements and the indicatrix of the element characteristic of the MOS elements according to the present invention are compared
Figure, as shown in Figure 7 A, transverse axis illustrate the grid length of MOS elements, and the left side longitudinal axis illustrates the critical voltage of MOS elements
(threshold voltage), the right side longitudinal axis illustrates the breakdown voltage of MOS elements.And thick black solid line signal is according to the present invention's
The indicatrix of the element characteristic of MOS elements, and the feature of the element characteristic of thick black dotted line signal prior art MOS elements is bent
Line.Fig. 7 A signal according to the present invention MOS elements in grid length under the situation of shortening, DIBL does not also occur, its critical electricity
Pressure substantially maintains identical level, and its breakdown voltage is also of a relatively high, and this is the MOS elements according to the present invention better than existing
One of characteristic of technology MOS elements.
Fig. 7 B show that the feature of prior art N-type MOS elements and the element characteristic of the N-type MOS elements according to the present invention is bent
Line compares figure, as shown in Figure 7 B, and transverse axis illustrates the grid length of N-type MOS elements, and the left side longitudinal axis illustrates the critical of N-type MOS elements
Voltage, the right side longitudinal axis illustrates the conducting resistance of N-type MOS elements.And thick black solid line signal is according to the N-type MOS elements of the present invention
The indicatrix of element characteristic, and the indicatrix of the element characteristic of thick black dotted line signal prior art N-type MOS elements.Fig. 7 B
Illustrate according to the present invention N-type MOS elements in grid length under the situation of shortening, DIBL does not also occur, its critical voltage is big
Cause maintains identical level, and prior art N-type MOS elements, in grid length under the situation of shortening, there occurs DIBL,
The level of its critical voltage declines with gate length shrinks, therefore, to avoid the level of critical voltage from declining, phase is maintained again
When gate operational voltage (such as 5V), prior art N-type MOS elements its grid lengths can not be less than 0.6 μm generally, and according to
It is also not in DIBL that the grid length of the N-type MOS elements of the present invention, which can foreshorten to 0.3 μm, but to avoid reduction collapse electricity
Pressure, in this instance, with 0.4 μm preferably；Therefore, because according to the present invention, grid length can use shorter grid avoiding SCE
Length, its conducting resistance is relatively low, and element can reduce, and also reduce manufacturing cost, and this is excellent for the MOS elements according to the present invention
In one of characteristic of prior art MOS elements.
Fig. 7 C show that the feature of prior art p-type MOS elements and the element characteristic of the p-type MOS elements according to the present invention is bent
Line compares figure, as seen in figure 7 c, and transverse axis illustrates the grid length of p-type MOS elements, and the left side longitudinal axis illustrates the critical of p-type MOS elements
Voltage, the right side longitudinal axis illustrates the conducting resistance of p-type MOS elements.And thick black solid line signal is according to the p-type MOS elements of the present invention
The indicatrix of element characteristic, and the indicatrix of the element characteristic of thick black dotted line signal prior art p-type MOS elements.Fig. 7 C
Illustrate according to the present invention p-type MOS elements in grid length under the situation of shortening, compared to prior art p-type MOS elements
DIBL, hence it is evident that relax many, the degree that the level of its critical voltage declines relaxes relatively, and prior art p-type MOS elements, in
Grid length there occurs serious DIBL under the situation of shortening, and the level of its critical voltage is quick with gate length shrinks
Decline, therefore, to avoid the level rapid decrease of critical voltage, suitable gate operational voltage (such as 5V) is maintained again, it is existing
There is its grid length of technology p-type MOS elements to be less than 0.6 μm generally, and it is long according to the grid of the p-type MOS elements of the present invention
It is also not in DIBL that degree, which can foreshorten to 0.3 μm, but to avoid reducing breakdown voltage, in this instance, with 0.4 μm preferably；Cause
This, due to according to the present invention, grid length is avoiding the SCE from can using shorter grid length, and its conducting resistance is relatively low, member
Part can reduce, and also reduce manufacturing cost, this be according to the present invention MOS elements better than prior art MOS elements characteristic it
One.
The 6th embodiment of Fig. 9 display present invention, shows the complementary metal oxide with double traps according to the present invention
The schematic cross-sectional view of thing semiconductor (Complementary Metal Oxide Semiconductor, CMOS) element 700.Such as
Shown in Fig. 9, cmos element 700 for example comprising：Semiconductor substrate 201, epitaxial layer 202, p-type trap 203a and 203d, N-type trap 203b
Diffusion (lightly doped diffusion, LDD) area 205a and 205d, N-type is lightly doped with 203c, insulation layer 204, p-type light
Doping diffusion (lightly doped diffusion, LDD) area 205b and 205c, N-type source 206a, N-type drain 207a, p-type
Source electrode 206b, p-type drain electrode 207b, p-type body zone 208aa, N-type body zone 208b, grid 211a and 211b, n type buried layer 213,
And marker space 214.
Semiconductor substrate 201 is in longitudinally upper (direction as shown in thick black dotted line arrow in figure), with relative upper surface
201a and lower surface 201b.Epitaxial layer 202 is formed on semiconductor substrate 201, and on longitudinal direction, stacking and be connected to upper surface
On 201a, the epi-layer surface 202a with opposing upper 201a.Insulation layer 204 is formed on epitaxial layer 202, to by outside
Prolong layer 202 and divide into NMOS element regions 204a and PMOS element regions 204b (as shown in thick black solid line area marking arrow in figure
Region).
P-type trap 203a is formed in the NMOS element regions 204a of epitaxial layer 202, and on longitudinal direction, positioned at epi-layer surface
Below 202a.P-type body zone 208aa is formed on the p-type trap 203a in epitaxial layer 202, and on longitudinal direction, stacking and be connected to
Between p-type trap 203a and epi-layer surface 202a.N-type trap 203c is formed in the NMOS element regions 204a of epitaxial layer 202, and in
On longitudinal direction, P is adjacent to below epi-layer surface 202a, and in laterally upper (direction as shown in thick black solid arrow in figure)
Type trap 203a, and N-type trap 203c and p-type trap 203a abut and form PN junctions 212a.Grid 211a is formed at epi-layer surface
In NMOS element regions 204a on 202a, on longitudinal direction, grid 211a is stacked and is connected on epi-layer surface 202a.Wherein,
Grid 211a includes dielectric layer di, stack layer st and wall sp.Dielectric layer di is formed on epi-layer surface 202a, and with
Epi-layer surface 202a connections.Stack layer st is formed on dielectric layer di, comprising conductive material, to the electricity as grid 211a
Property contact, self-aligned when can act also as being formed PLDD areas 205a and NLDD areas 205b shields.Wall sp is formed at stacking
On epi-layer surface 202a outside layer st side wall, cladding stack layer st side wall, comprising insulating materials, can act also as forming N
Self-aligned during type drain electrode 207a and N-type source 206a is shielded.
PLDD areas 205a, with self-aligned processing step, is formed in the epitaxial layer 202 on p-type trap 203a, and in longitudinal direction
On, stack and be connected between p-type trap 203a and epi-layer surface 202a.NLDD areas 205b, with self-aligned processing step, shape
Into in the epitaxial layer 202 on N-type trap 203c, and on longitudinal direction, stacking and be connected to N-type trap 203c and epi-layer surface 202a
Between.N-type source 206a is formed in the epitaxial layer 202 on p-type trap 203a, and on longitudinal direction, stacking and be connected to p-type trap
Between 203a and epi-layer surface 202a, and between p-type body zone 208aa and PLDD area 205a in transverse direction, are connected to.N-type
Drain electrode 207a is formed in the epitaxial layer 202 on N-type trap 203c, and on longitudinal direction, stacking and be connected to N-type trap 203c and extension
Between layer surface 202a, and in transverse direction, it is connected with NLDD areas 205b.Wherein, PN junctions 212a be located at PLDD areas 205a with
Between NLDD areas 205b, and PN junctions 212a is in the range of NMOS element regions 204a, between PLDD areas 205a and NLDD areas 205b
Between.
N-type trap 203b is formed in the PMOS element regions 204b of epitaxial layer 202, and on longitudinal direction, positioned at epi-layer surface
Below 202a.N-type body zone 208b is formed on the N-type trap 203b in epitaxial layer 202, and on longitudinal direction, stacking and be connected to N
Between type trap 203b and epi-layer surface 202a.P-type trap 203d is formed in the PMOS element regions 204b of epitaxial layer 202, and in
On longitudinal direction, N is adjacent to below epi-layer surface 202a, and in laterally upper (direction as shown in thick black solid arrow in figure)
Type trap 203b, and p-type trap 203d and N-type trap 203b abut and form PN junctions 212b.Grid 211b is formed at epi-layer surface
In PMOS element regions 204b on 202a, on longitudinal direction, grid 211b is stacked and is connected on epi-layer surface 202a.Wherein,
Grid 211b includes dielectric layer di ', stack layer st ' and wall sp '.Dielectric layer di ' is formed on epi-layer surface 202a,
And be connected with epi-layer surface 202a.Stack layer st ' is formed on dielectric layer di ', comprising conductive material, to be used as grid
211b electrical contact, self-aligned when can act also as being formed NLDD areas 205c and PLDD areas 205d is shielded.Wall sp ' shapes
Into on the epi-layer surface 202a outside stack layer st ' side wall, cladding stack layer st ' side wall, comprising insulating materials, also may be used
Shielded as self-aligned when forming p-type drain electrode 207b and p-type source electrode 206b.
NLDD areas 205c, with self-aligned processing step, is formed in the epitaxial layer 202 on N-type trap 203b, and in longitudinal direction
On, stack and be connected between N-type trap 203b and epi-layer surface 202a.PLDD areas 205d, with self-aligned processing step, shape
Into in the epitaxial layer 202 on p-type trap 203d, and on longitudinal direction, stacking and be connected to p-type trap 203d and epi-layer surface 202a
Between.P-type source electrode 206b is formed in the epitaxial layer 202 on N-type trap 203b, and on longitudinal direction, stacking and be connected to N-type trap
Between 203b and epi-layer surface 202a, and between N-type body zone 208b and NLDD area 205c in transverse direction, are connected to.N-type is leaked
Pole 207b is formed in the epitaxial layer 202 on p-type trap 203d, and on longitudinal direction, stacking and be connected to p-type trap 203d and epitaxial layer
Between the 202a of surface, and in transverse direction, it is connected with PLDD areas 205d.Wherein, PN junctions 212b is located at NLDD areas 205c and PLDD
Between area 205d, and PN junctions 212b is in the range of PMOS element regions 204b, between NLDD areas 205c and PLDD areas 205d.
Wherein, insulation layer 204 is for example formed on epitaxial layer 202, to define NMOS element regions 204a and PMOS element regions
204b；And p-type body zone 208aa, grid 211a, PLDD areas 205a, NLDD area 205b, N-type source 206a and N-type drain
207a is located in NMOS element regions 204a；N-type body zone 208b, grid 211b, N-type are lightly doped diffusion region 205c, p-type and are lightly doped
Diffusion region 205d, p-type source electrode 206b and p-type drain electrode 207b are located in PMOS element regions 204b.In addition, it should be noted that, it is a kind of
Preferably in embodiment, PLDD areas 205a is in addition to N-type source 206a and dielectric layer di adjoinings, only with p-type trap 203a
It is adjacent；And NLDD areas 205b is only abutted in addition to N-type drain 207a and dielectric layer di adjoinings with N-type trap 203c；And N-type
Diffusion region 205c is lightly doped in addition to p-type source electrode 206b and dielectric layer di ' adjoinings, is only abutted with N-type trap 203b；And p-type
Diffusion region 205d is lightly doped in addition to p-type drain electrode 207b and dielectric layer di ' adjoinings, is only abutted with p-type trap 203d.
Wherein, the cmos element 700 with double traps, such as, but not limited to also includes n type buried layer 213, is formed at substrate 201
With in epitaxial layer 202, and positioned at substrate 201 and the junction of epitaxial layer 202, and on longitudinal direction, being connected to below p-type trap 203d.N-type
Buried regions 213 is generally all located at below p-type trap 203d, and separates p-type trap 203d and substrate 201, to make p-type trap 203d and base
Plate 201 is electrically not directly connected.
Wherein, marker space 214 is connected between NMOS element region 204a and PMOS element regions 204b, and separates NMOS elements
Area 204a and PMOS element regions 204b.And longitudinal depth of marker space 214, counted downwards since the longitudinal direction epi-layer surface 202a
Calculate, be not less than p-type trap 203a, N-type trap 203c, N-type trap 203b, the depth with p-type trap 203d any region.
A kind of preferably embodiment, for example, wherein PLDD areas 205a impurity doping concentration is higher than p-type trap 203a
Impurity doping concentration, and NLDD areas 205b impurity doping concentration be higher than N-type trap 203c impurity doping concentration.Citing and
Speech, PLDD areas 205a impurity doping concentration 2 to 10 times of the impurity doping concentration higher than p-type trap 203a, and NLDD areas 205b's
Impurity doping concentration is higher than N-type trap 203c 2 to 10 times of impurity doping concentration.Wherein, doping concentration is referred to for example in ion
It is implanted into processing step, performed plane doping concentration, it is however generally that, this plane doping concentration, numerical value can be higher than in thermal technology
Three-dimensional doping concentration after skill step, this is well known to those skilled in the art, and will not be described here.So arrange, can
To relax the HCE in SCE.
A kind of preferably embodiment, for example, as shown in Fig. 2 wherein marker space 214 is including deep trench insulated
(deep trench isolation, DTI) structure.
The 7th embodiment of Figure 10 A-10I display present invention.Figure 10 A-10I show the double traps of having according to the present invention
The schematic cross-sectional view of the manufacture method of complementary metal oxide semiconductor element 700.First, there is provided semiconductor as shown in Figure 10 A
Substrate 201, wherein, semiconductor substrate 201 is such as, but not limited to P-type silicon substrate, can also be other semiconductor substrates certainly.
Semiconductor substrate 201 is in longitudinally upper (direction as shown in thick black dotted line arrow in figure), with relative upper surface 201a with
Surface 201b.Then with lithographic process steps and ion implantation technology step, n type buried layer ion implantation region 213 ' is formed.Then
As shown in Figure 10 B, epitaxial layer 202 is formed on semiconductor substrate 201, and on longitudinal direction, it is outer with opposing upper 201a
Prolong layer surface 202a, epitaxial layer 202 is stacked and is connected on the 201a of upper surface.And with thermal process step, form n type buried layer 213
In semiconductor substrate 201 and epitaxial layer 202, and positioned at the junction of n type buried layer 213 and semiconductor substrate 201.
Next, please continue to refer to Figure 10 B, form p-type trap 203a and 203d in epitaxial layer 202, and on longitudinal direction, heap
Fold and be connected on the upper surface 201a of semiconductor substrate 201.Then, N-type trap 203b and 203c is formed in epitaxial layer 202,
And on longitudinal direction, N traps 203b and 203c is located at below epi-layer surface 202a, and in being adjacent to p-type trap 203d in transverse direction respectively
With 203a.N-type trap 203c and p-type trap 203a formation PN junctions 212a；N-type trap 203b and p-type trap 203d formation PN junctions 212b.
Wherein, PN junctions 212a is located between the PLDD areas 205a formed in subsequent process steps and NLDD areas 205b；PN junctions
Diffusion region 205d is lightly doped for the p-type that 212b is located at formed in subsequent process steps and N-type is lightly doped between the 205c of diffusion region.
P-type trap 203a and 203d, and the method for forming N-type trap 203b and 203c are formed, such as, but not limited to photoetching process, ion
Implantation technique and thermal process formation (not shown), this is well known to those skilled in the art, and will not be described here.
Next, as illustrated in figure 10 c, forming marker space 214 and being connected to NMOS element regions 204a and PMOS element regions 204b
Between, and separate NMOS element regions 204a and PMOS element regions 204b.Marker space 214 is such as, but not limited to zanjon as depicted
Slot insulation (deep trench isolation, DTI) structure, it is well known to those skilled in the art, and will not be described here.
Then, insulation layer 204 is formed on epitaxial layer 202, to define NMOS element regions 204a and PMOS element region 204b, and follow-up
In technique, p-type body zone 208aa, grid 211a, PLDD areas 205a, NLDD area 205b, the N-type source 206a and N formed
Type drain electrode 207a is located in NMOS element regions 204a；Diffusion region 205c, p-type is lightly doped in N-type body zone 208b, grid 211b, N-type
Diffusion region 205d, p-type source electrode 206b is lightly doped, is located at p-type drain electrode 207b in PMOS element regions 204b.Wherein, insulation layer 204
For zone oxidation as depicted (local oxidation of silicon, LOCOS) structure or shallow trench isolation
(shallow trench isolation, STI) structure.Next, as shown in Figure 10 D, dielectric layer di and di ' are formed, with heap
Lamination st and st ' is simultaneously connected to epi-layer surface on epi-layer surface 202a, and on longitudinal direction, dielectric layer di and di ' are stacked
On 202a, and stack layer st and st ' are stacked and are connected on dielectric layer di.
Next, as shown in figure 10e, such as in identical lithographic process steps, respectively with dielectric layer di and di ' and heap
Lamination st and st ' and photoresist layer 205a ' is as shielding, to define PLDD areas 205a and 205d ion implantation region, and for example
With identical ion implantation technology step, by p type impurity, with the form of accelerating ion (as shown in figure compared with thin dotted line arrow
Meaning), it is implanted into the region defined, to form PLDD areas 205a and 205d ion implantation region.Next, as shown in figure 10f, example
Such as in identical lithographic process steps, respectively using dielectric layer di and di ', stack layer st and st ' and photoresist layer 205b ' as
Shielding, to define NLDD areas 205b and 205c ion implantation region, and with ion implantation technology step, by N-type impurity, to accelerate
In the form (as illustrated in figure compared with thin dotted line arrow) of ion, the region for being implanted into definition, to form NLDD areas 205b and 205c
Ion implantation region.
Next, as shown in figure 10g, N-type source 206a is formed in the epitaxial layer 202 on p-type trap 203a, and in longitudinal direction
On, stack and be connected between p-type trap 203a and epi-layer surface 202a, and in transverse direction, being connected to subsequent process steps institute
Between the p-type body zone 208aa and PLDD area 205a of formation.It should be noted that, work is ion implanted in formation N-type source 206a
In skill step, as shown in figure 10g, using wall sp, stack layer st and photoresist layer 206a ' as shielding, to define N-type source
206a ion implantation region, and with ion implantation technology step, by N-type impurity, with (in such as figure relatively thin empty in the form of accelerating ion
Line arrow is illustrated), it is implanted into the region defined, to form N-type source 206a ion implantation region.It should be noted that, form N
Type source electrode 206a ion implantation technology step, such as to control to accelerate ion direct of travel, relative to epi-layer surface 202a
With an angle of inclination, part N-type impurity is implanted into the epitaxial layer 202 below wall sp, to avoid passage from being not turned on
Phenomenon.
Next, as shown in Figure 10 H, p-type source electrode 206b is formed in the epitaxial layer 202 on N-type trap 203b, and in longitudinal direction
On, stack and be connected between N-type trap 203b and epi-layer surface 202a, and in transverse direction, being connected to subsequent process steps institute
The N-type body zone 208b and N-type of formation are lightly doped between the 205c of diffusion region.It should be noted that, formed p-type source electrode 206b from
In son implantation processing step, as shown in Figure 10 H, using wall sp ', stack layer st ' and photoresist layer 206b ' as shielding, with
P-type source electrode 206b ion implantation region is defined, and with ion implantation technology step, by p type impurity, in the form of accelerating ion
In (as illustrated in figure compared with thin dotted line arrow), the region for being implanted into definition, to form p-type source electrode 206b ion implantation region.Palpus
Illustrate, form p-type source electrode 206b ion implantation technology step, such as to control to accelerate ion direct of travel, relative to
Epi-layer surface 202a has an angle of inclination, and part p type impurity is implanted into the epitaxial layer 202 below wall sp ', with
Avoid the phenomenon that passage is not turned on.
Next, as shown in figure 10i, p-type body zone 208aa is formed on the p-type trap 203a in epitaxial layer 202, and in
On longitudinal direction, stack and be connected between p-type trap 203a and epi-layer surface 202a；N-type drain 207a is formed on N-type trap 203c
Epitaxial layer 202 in, and on longitudinal direction, stacking and be connected between N-type trap 203c and epi-layer surface 202a, and in transverse direction
On, it is connected with NLDD areas 205b；Wherein, PN junctions 212a is located between PLDD areas 205a and NLDD areas 205b.Certainly, N is formed
Type drain electrode 207a ion implantation technology step, can be integrated into together with forming N-type source 206a ion implantation technology step
One processing step, will be described in detail in rear.
Next, continuing referring to Figure 10 I, N-type body zone 208b is formed on the N-type trap 203b in epitaxial layer 202, and
In on longitudinal direction, stacking and be connected between N-type trap 203b and epi-layer surface 202a；Form p-type and drain 207b in p-type trap 203d
On epitaxial layer 202 in, and on longitudinal direction, stacking and be connected between p-type trap 203d and epi-layer surface 202a, and in transverse direction
On, diffusion region 205d is lightly doped with p-type and is connected；Wherein, PN junctions 212b is lightly doped diffusion region 205c positioned at N-type and gently mixed with p-type
Between miscellaneous diffusion region 205d.Certainly, p-type drain electrode 207b ion implantation technology step is formed, can be with forming p-type source electrode 206b
Ion implantation technology step be integrated into same processing step, will in it is rear be described in detail.
A kind of preferably embodiment, for example, wherein PLDD areas 205a impurity doping concentration is higher than p-type trap 203a
Impurity doping concentration, and NLDD areas 205b impurity doping concentration be higher than N-type trap 203c impurity doping concentration.Citing and
Speech, PLDD areas 205a impurity doping concentration 2 to 10 times of the impurity doping concentration higher than p-type trap 203a, and NLDD areas 205b's
Impurity doping concentration is higher than N-type trap 203c 2 to 10 times of impurity doping concentration.For example, wherein diffusion region is lightly doped in N-type
205c impurity doping concentration is higher than N-type trap 203b impurity doping concentration, and diffusion region 205d impurity doping is lightly doped in p-type
Concentration is higher than p-type trap 203d impurity doping concentration.For example, diffusion region 205c impurity doping concentration height is lightly doped in N-type
In N-type trap 203b 2 to 10 times of impurity doping concentration, and diffusion region 205d impurity doping concentration is lightly doped higher than p-type trap in p-type
2 to 10 times of 203d impurity doping concentration.Wherein, doping concentration is referred to for example in ion implantation technology step, performed
Plane doping concentration, it is however generally that, this plane doping concentration, numerical value can be higher than annealing (anneal) thermal process step after
Three-dimensional doping concentration, this is well known to those skilled in the art, and will not be described here.So arrange, can relax in SCE
HCE.
The 8th embodiment of Figure 11 display present invention.The present embodiment shows cuing open according to cmos element 800 of the invention
Depending on schematic diagram.Implement sharp difference with the 7th to be, the marker space 214 of the cmos element 800 of the present embodiment, including p-type
Marker space 214a and N-type marker space 214b.P-type marker space 214a is formed at the NMOS element region 204a in epitaxial layer 202, and in
On the longitudinal direction, below the epi-layer surface 202a, and in being adjacent to N-type trap 203c in transverse direction.N-type marker space 214b is formed
PMOS element region 204b in epitaxial layer 202, and on longitudinal direction, below epi-layer surface 202a, and in laterally upper neighbour
It is connected to p-type trap 203d.And longitudinal depth of marker space 214, calculate downwards, be not less than since the longitudinal direction epi-layer surface 202a
P-type trap 203a, N-type trap 203c, N-type trap 203b, the depth with p-type trap 203d any region.
The 9th embodiment of Figure 12 display present invention.The present embodiment shows cuing open according to cmos element 900 of the invention
Depending on schematic diagram.The present embodiment is intended to explanation according to the present invention, forms the mode of insulation layer 204, however it is not limited to such as the 7th implementation
Shown in example.The present embodiment is that as shown in figure 12, insulation layer 204 is shallow trench isolation with the 7th embodiment difference
In (shallow trench isolation, STI) structure rather than such as the 7th embodiment, insulation layer 204 is zone oxidation
(local oxidation of silicon, LOCOS) structure.Other techniques are identical with the 7th embodiment, formed as schemed
Cmos element 900 shown in 12.
The tenth embodiment of Figure 13 display present invention.The present embodiment shows cuing open according to cmos element 1000 of the invention
Depending on schematic diagram.The present embodiment is intended to explanation according to the present invention, forms N-type drain 207a ion implantation technology step, Ke Yiyu
The ion implantation technology step for forming N-type source 206a is integrated into same processing step, and this causes N-type impurity, is forming N-type
Also such as similar in N-type source 206a during drain electrode 207a, it accelerates ion direct of travel, to have relative to epi-layer surface 202a
There is an angle of inclination, part N-type impurity is implanted into the epitaxial layer 202 below wall sp, as shown in fig. 6, consequently, it is possible to can
The processing step for independently forming N-type drain 207a in addition is saved, to reduce manufacturing cost.In addition, according to the present invention, forming p-type
Drain electrode 207b ion implantation technology step, can be integrated into same with formation p-type source electrode 206b ion implantation technology step
Individual processing step, this causes p type impurity, and when forming p-type drain electrode 207b, also such as similar in p-type source electrode 206b, it accelerates ion
Direct of travel, to have an angle of inclination relative to epi-layer surface 202a, part p type impurity is implanted into below wall sp '
Epitaxial layer 202 in, as shown in figure 13, consequently, it is possible to can save independently form in addition p-type drain 207b processing step, with
Reduce manufacturing cost.
It should be noted that, the present invention is in many features, unlike the prior art.It is described as follows with the 7th embodiment：
Compare the prior art cmos element 600 shown in Fig. 8 and the 7th embodiment cmos element 700 according to the present invention, according to this
The cmos element 700 of invention mainly has at following 4 points with the difference of prior art cmos element 600：
1. there are double traps of different conductivity types according to the cmos element 700 of the present invention, for example, p-type trap 203a is in N-type source
206a is relative to PN junction 212a homonymies；And N-type trap 203c in N-type drain 207a relative to junction PN junction 212a homonymies；N-type
Trap 203b is in p-type source electrode 206b relative to PN junction 212b homonymies；And p-type trap 203d drains 207b relative to junction PN in p-type
Junction 212b homonymies；
2. had respectively in NMOS element regions 204a and PMOS element regions 204b according to the cmos element 700 of the present invention different
Double LDD regions of conductivity type, wherein, PLDD areas 205a is in p-type trap 203a relative to PN junction 212a homonymies；And NLDD areas 205b exists
N-type trap 203c is relative to PN junction 212a homonymies；NLDD areas 205c is in N-type trap 203b relative to PN junction 212b homonymies；And
PLDD areas 205d is in p-type trap 203d relative to PN junction 212b homonymies；
3. there is the PN junction 212a formed by p-type trap 203a and N-type trap 203c according to the cmos element 700 of the present invention,
And with the PN junctions 212b formed by N-type trap 203b and p-type trap 203d, it is foregoing " homonymy ", that is, refer in PN junctions 212a or
212b the same side.And PN junctions 212a, between PLDD areas 205a and NLDD areas 205b, PN junctions 212b is between NLDD areas
Between 205c and PLDD areas 205d.
4. according to the cmos element 700 of the present invention there is marker space 214 to be connected to NMOS element regions 204a and PMOS element regions
Between 204b, and separate NMOS element regions 204a and PMOS element regions 204b.And longitudinal depth of marker space 214, from epitaxial layer
The longitudinal direction that surface 202a starts is calculated downwards, is not less than p-type trap 203a, N-type trap 203c, N-type trap 203b and p-type trap 203d
The depth of any region.
For example, in the NMOS element region 104a normal operatings of prior art cmos element 600, grid is put on
111a grid bias, at the junction of p-type trap 103a and grid 111a dielectric layer, attracts conducting currier and forms passage
(as black dotted lines wire is illustrated in Fig. 1), grid bias changes, then the quantity of conducting currier changes in passage, causes
Nearby electric field changes passage (channel), channel characteristic is changed, causes electric current to change.This is those skilled in the art
It is known, it will not be described here.And the NMOS element region 204a of the cmos element 700 according to the present invention, its passage is by p-type trap
203a determined with N-type source 206a, rather than as prior art cmos element 600 NMOS element regions 104a in passage be by
Determined with the NLDD areas 105a of N-type source 106a homonymies and with the NLDD areas 105b of N-type drain 107a homonymies.According to the present invention
Cmos element 700 NMOS element regions 204a channel such as Fig. 9 in black dotted lines wire illustrated, and element spacing
(pitch), represented with grid length, can reach identical it is electrical when it is relatively short, that is, passage it is relatively short, this makes
Conducting resistance it is relatively low, and due to PLDD areas 205a impurity doping concentration be higher than p-type trap 203a impurity doping concentration,
Therefore SCE is successfully inhibited.In addition, in the NMOS element regions 104a of prior art cmos element 600, its collapse is betided Lou
Junction between the NLDD areas 105b and p-type trap 103a at pole 107a ends, because NLDD areas 105b impurity doping concentration is of a relatively high,
Therefore its breakdown voltage is relatively low.And the NMOS element region 204a of the cmos element 700 according to the present invention, it collapses
(breakdown) PN junction 212a are betided, because N-type trap 203c impurity doping concentration is relatively low, therefore its collapse electricity
Pressure is of a relatively high, and hot carrier (hot carrier) effect is also suppressed relatively.The CMOS according to the present invention can similarly be spreaded to
The PMOS element region 204b of element 700, its collapse (breakdown) voltage is higher compared with the prior art, hot carrier (hot
Carrier) effect is also suppressed compared with the prior art.
Illustrate the present invention for preferred embodiment above, it is described above, only it is easy to those skilled in the art
Solve present disclosure, not for limit the present invention interest field.Under the same spirit of the present invention, people in the art
Member can think and various equivalence changes.For example, in the case where not influenceing the main characteristic of element, other processing steps or knot can be added
Structure, such as critical voltage adjust area；For another example, photoetching technique is not limited to masking techniques, can also include electron beam lithography.Again
For example, the change in all embodiments, the marker space 214 that can be interacted in use, such as Figure 11 embodiments includes p-type marker space
214a and N-type marker space 214b, can also be applied to Figure 12 and Figure 13 embodiment, etc..All this kind, all can be according to this hair
Bright teaching is analogized and obtained, therefore, and the scope of the present invention should cover above-mentioned and other all equivalence changes.
Claims (24)
1. a kind of metal oxide semiconductor device with double traps, it is characterised in that include：
Semiconductor substrate, on a longitudinal direction, with a relative upper surface and a lower surface；
One epitaxial layer, is formed on the substrate, on the longitudinal direction, the epi-layer surface with the relative upper surface, and this is outer
Prolong layer to stack and be connected on the upper surface；
One first conductive type well, is formed in the epitaxial layer, and on the longitudinal direction, below the epi-layer surface；
One first conductive type body region, is formed in first conductive type well in the epitaxial layer, and on the longitudinal direction, stacks simultaneously
It is connected between first conductive type well and the epi-layer surface；
One second conductive type well, is formed in the epitaxial layer, and on the longitudinal direction, below the epi-layer surface, and in one
First conductive type well, and second conductive type well and first conductive type well, one PN junctions of formation are adjacent in transverse direction；
One grid, is formed in the epi-layer surface, and on the longitudinal direction, the gate stack is simultaneously connected in the epi-layer surface；
Diffusion region is lightly doped in one first conductivity type, and with self-aligned processing step, this being formed in first conductive type well is outer
Prolong in layer, and on the longitudinal direction, stacking and be connected between first conductive type well and the epi-layer surface；
Diffusion region is lightly doped in one second conductivity type, and with self-aligned processing step, this being formed in second conductive type well is outer
Prolong in layer, and on the longitudinal direction, stacking and be connected between second conductive type well and the epi-layer surface；
One second conductivity type source electrode, is formed in the epitaxial layer in first conductive type well, and on the longitudinal direction, stacking simultaneously connects
Be connected between first conductive type well and the epi-layer surface, and in the transverse direction, be connected to first conductive type body region with
First conductivity type is lightly doped between diffusion region；And
One second conductivity type drains, and is formed in the epitaxial layer in second conductive type well, and on the longitudinal direction, stacking simultaneously connects
It is connected between second conductive type well and the epi-layer surface, and in the transverse direction, diffusion region is lightly doped with second conductivity type
Connection；
Wherein, diffusion region is lightly doped positioned at first conductivity type in the PN junctions and second conductivity type is lightly doped between diffusion region.
2. the metal oxide semiconductor device as claimed in claim 1 with double traps, wherein, also comprising an insulation layer, shape
Into on the epitaxial layer, to define a metal oxide semiconductor device area, and first conductive type body region, the grid, should
First conductivity type is lightly doped diffusion region, second conductivity type and diffusion region, the second conductivity type source electrode and second conduction is lightly doped
Type drain electrode is located in the metal oxide semiconductor device area.
3. the metal oxide semiconductor device as claimed in claim 2 with double traps, wherein, the insulation layer is zone oxidation
Structure or insulation structure of shallow groove.
4. the metal oxide semiconductor device as claimed in claim 1 with double traps, wherein, first conductivity type is lightly doped
The impurity doping concentration of diffusion region is higher than the impurity doping concentration of first conductive type well, and diffusion is lightly doped in second conductivity type
The impurity doping concentration in area is higher than the impurity doping concentration of second conductive type well.
5. the metal oxide semiconductor device as claimed in claim 1 with double traps, wherein, also comprising one second conductivity type
Buried regions, is formed in the substrate and the epitaxial layer, and positioned at its junction, and on the longitudinal direction, being connected to first conductive type well
Lower section.
6. a kind of metal oxide semiconductor device manufacture method with double traps, it is characterised in that include：
Semiconductor substrate is provided, it is on a longitudinal direction, with a relative upper surface and a lower surface；
An epitaxial layer is formed on the semiconductor substrate, and on the longitudinal direction, the epi-layer surface with the relative upper surface,
And the epitaxial layer is stacked and is connected on the upper surface；
One first conductive type well is formed in the epitaxial layer, and on the longitudinal direction, below the epi-layer surface；
One first conductive type body region is formed in first conductive type well in the epitaxial layer, and on the longitudinal direction, is stacked simultaneously
It is connected between first conductive type well and the epi-layer surface；
One second conductive type well is formed in the epitaxial layer, and on the longitudinal direction, second conductive type well is located at the epitaxial layer table
Below face, and in being adjacent to first conductive type well in a transverse direction, and second conductive type well is formed with first conductive type well
One PN junctions；
A grid is formed in the epi-layer surface, on the longitudinal direction, the gate stack is simultaneously connected in the epi-layer surface；
With self-aligned processing step, form one first conductivity type and diffusion region is lightly doped in the extension in first conductive type well
In layer, and on the longitudinal direction, stacking and be connected between first conductive type well and the epi-layer surface；
With self-aligned processing step, form one second conductivity type and diffusion region is lightly doped in the extension in second conductive type well
In layer, and on the longitudinal direction, stacking and be connected between second conductive type well and the epi-layer surface；
One second conductivity type source electrode is formed in the epitaxial layer in first conductive type well, and on the longitudinal direction, stacking simultaneously connects
Be connected between first conductive type well and the epi-layer surface, and in the transverse direction, be connected to first conductive type body region with
First conductivity type is lightly doped between diffusion region；And
One second conductivity type is formed to drain in the epitaxial layer in second conductive type well, and on the longitudinal direction, stacking simultaneously connects
It is connected between second conductive type well and the epi-layer surface, and in the transverse direction, diffusion region is lightly doped with second conductivity type
Connection；
Wherein, diffusion region is lightly doped positioned at first conductivity type in the PN junctions and second conductivity type is lightly doped between diffusion region.
7. the metal oxide semiconductor device manufacture method as claimed in claim 6 with double traps, wherein, also comprising formation
One insulation layer is on the epitaxial layer, to define a metal oxide semiconductor device area, and first conductive type body region, the grid
Pole, first conductivity type be lightly doped diffusion region, second conductivity type be lightly doped diffusion region, the second conductivity type source electrode, with this
The drain electrode of two conductivity types is located in the metal oxide semiconductor device area.
8. the metal oxide semiconductor device manufacture method as claimed in claim 7 with double traps, wherein, the insulation layer is
Zone oxidation structure or insulation structure of shallow groove.
9. the metal oxide semiconductor device manufacture method as claimed in claim 6 with double traps, wherein, first conduction
Impurity doping concentration of the impurity doping concentration higher than first conductive type well of diffusion region is lightly doped in type, and second conductivity type is light
The impurity doping concentration of doped diffusion region is higher than the impurity doping concentration of second conductive type well.
10. the metal oxide semiconductor device manufacture method as claimed in claim 6 with double traps, wherein, also comprising shape
Into one second conductive type buried layer in the substrate and the epitaxial layer, and positioned at its junction, and on the longitudinal direction, be connected to this first
Below conductive type well.
11. a kind of complementary metal oxide semiconductor element with double traps, it is characterised in that include：
Semiconductor substrate, on a longitudinal direction, with a relative upper surface and a lower surface；
One epitaxial layer, is formed on the semiconductor substrate, on the longitudinal direction, the epi-layer surface with the relative upper surface,
And the epitaxial layer is stacked and is connected on the upper surface；
One insulation layer, is formed on the epitaxial layer, the epi region is divided into a NMOS element regions and a PMOS element regions；
One first p-type trap, is formed at the NMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the epi-layer surface
Lower section；
One p-type body zone, is formed on the first p-type trap in the epitaxial layer, and on the longitudinal direction, stack and be connected to this
Between one p-type trap and the epi-layer surface；
One first N-type trap, is formed at the NMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the epi-layer surface
Lower section, and in being adjacent to the first p-type trap in a transverse direction, and first N-type trap connects with one the oneth PN of the first p-type trap formation
Face；
One first grid, is formed at the NMOS element regions in the epi-layer surface, and on the longitudinal direction, the first grid is stacked simultaneously
It is connected in the epi-layer surface；
Diffusion region is lightly doped in one first p-type, with self-aligned processing step, is formed in the epitaxial layer on the first p-type trap,
And on the longitudinal direction, stacking and be connected between the first p-type trap and the epi-layer surface；
Diffusion region is lightly doped in one first N-type, with self-aligned processing step, is formed in the epitaxial layer in first N-type trap,
And on the longitudinal direction, stacking and be connected between first N-type trap and the epi-layer surface；
One N-type source, is formed in the epitaxial layer on the first p-type trap, and on the longitudinal direction, stack and be connected to this first
Between p-type trap and the epi-layer surface, and diffusion region is lightly doped in the transverse direction, being connected to the p-type body zone and first p-type
Between；
One N-type drain, is formed in the epitaxial layer in first N-type trap, and on the longitudinal direction, stack and be connected to this first
Between N-type trap and the epi-layer surface, and in the transverse direction, diffusion region is lightly doped with first N-type and is connected；
One second N-type trap, is formed at the PMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the epi-layer surface
Lower section；
One N-type body zone, is formed in second N-type trap in the epitaxial layer, and on the longitudinal direction, stack and be connected to this
Between two N-type traps and the epi-layer surface；
One second p-type trap, is formed at the PMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the epi-layer surface
Lower section, and in being adjacent to second N-type trap in the transverse direction, and second N-type trap connects with one the 2nd PN of the second p-type trap formation
Face；
One second grid, is formed at the PMOS element regions in the epi-layer surface, and on the longitudinal direction, the second grid is stacked simultaneously
It is connected in the epi-layer surface；
Diffusion region is lightly doped in one second N-type, with self-aligned processing step, is formed in the epitaxial layer in second N-type trap,
And on the longitudinal direction, stacking and be connected between second N-type trap and the epi-layer surface；
Diffusion region is lightly doped in one second p-type, with self-aligned processing step, is formed in the epitaxial layer on the second p-type trap,
And on the longitudinal direction, stacking and be connected between the second p-type trap and the epi-layer surface；
One p-type source electrode, is formed in the epitaxial layer in second N-type trap, and on the longitudinal direction, stack and be connected to this second
Between N-type trap and the epi-layer surface, and diffusion region is lightly doped in the transverse direction, being connected to the N-type body zone and second N-type
Between；
One p-type drain, be formed in the epitaxial layer on the second p-type trap, and on the longitudinal direction, stack and be connected to this second
Between p-type trap and the epi-layer surface, and in the transverse direction, diffusion region is lightly doped with second p-type and is connected；And
One marker space, is connected between the NMOS element regions and the PMOS element regions, and its depth, since the epi-layer surface
Longitudinal direction downwards calculate, be not less than the first p-type trap, first N-type trap, second N-type trap, any with the second p-type trap
The depth in region；
Wherein, diffusion region is lightly doped positioned at first p-type in the first PN junctions and first N-type is lightly doped between diffusion region；
Wherein, diffusion region is lightly doped positioned at second p-type in the 2nd PN junctions and second N-type is lightly doped between diffusion region.
12. the complementary metal oxide semiconductor element as claimed in claim 11 with double traps, wherein, the insulation layer is
Zone oxidation structure or insulation structure of shallow groove.
13. the complementary metal oxide semiconductor element as claimed in claim 11 with double traps, wherein, first p-type
The impurity doping concentration that diffusion region is lightly doped is higher than the impurity doping concentration of the first p-type trap, and diffusion is lightly doped in first N-type
The impurity doping concentration in area is higher than the impurity doping concentration of first N-type trap.
14. the complementary metal oxide semiconductor element as claimed in claim 11 with double traps, wherein, second p-type
The impurity doping concentration that diffusion region is lightly doped is higher than the impurity doping concentration of the second p-type trap, and diffusion is lightly doped in second N-type
The impurity doping concentration in area is higher than the impurity doping concentration of second N-type trap.
15. the complementary metal oxide semiconductor element as claimed in claim 11 with double traps, wherein, also comprising a N
Type buried regions, is formed in the semiconductor substrate and the epitaxial layer, and positioned at its junction, and on the longitudinal direction, it is connected to the 2nd P
Below type trap.
16. the complementary metal oxide semiconductor element as claimed in claim 11 with double traps, wherein, marker space bag
Include a deep trench insulated structure.
17. the complementary metal oxide semiconductor element as claimed in claim 11 with double traps, wherein, marker space bag
Include:
One p-type marker space, is formed at the NMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the epi-layer surface
Lower section, and in being adjacent to first N-type trap in the transverse direction；And
One N-type marker space, is formed at the PMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the epi-layer surface
Lower section, and in being adjacent to the second p-type trap in the transverse direction.
18. a kind of complementary metal oxide semiconductor element manufacture method with double traps, it is characterised in that include：
Semiconductor substrate is provided, it is on a longitudinal direction, with a relative upper surface and a lower surface；
An epitaxial layer is formed on the semiconductor substrate, and on the longitudinal direction, the epi-layer surface with the relative upper surface,
And the epitaxial layer is stacked and is connected on the upper surface；
An insulation layer is formed on the epitaxial layer, the epi region is divided into a NMOS element regions and a PMOS element regions；
The NMOS element regions of one first p-type trap in the epitaxial layer are formed, and on the longitudinal direction, under the epi-layer surface
Side；
A p-type body zone is formed on the first p-type trap in the epitaxial layer, and on the longitudinal direction, stack and be connected to this
Between one p-type trap and the epi-layer surface；
The NMOS element regions of one first N-type trap in the epitaxial layer are formed, and on the longitudinal direction, under the epi-layer surface
Side, and in being adjacent to the first p-type trap in a transverse direction, and first N-type trap and the first p-type trap one the oneth PN junctions of formation；
A first grid is formed in the NMOS element regions in the epi-layer surface, on the longitudinal direction, the first grid is stacked simultaneously
It is connected in the epi-layer surface；
With self-aligned processing step, form one first p-type and diffusion region be lightly doped in the epitaxial layer on the first p-type trap,
And on the longitudinal direction, stacking and be connected between the first p-type trap and the epi-layer surface；
With self-aligned processing step, form one first N-type and diffusion region be lightly doped in the epitaxial layer in first N-type trap,
And on the longitudinal direction, stacking and be connected between first N-type trap and the epi-layer surface；
A N-type source is formed in the epitaxial layer on the first p-type trap, and on the longitudinal direction, stacking and be connected to the first P
Between type trap and the epi-layer surface, and diffusion region is lightly doped in the transverse direction, being connected to the p-type body zone and first p-type
Between；
A N-type drain is formed in the epitaxial layer in first N-type trap, and on the longitudinal direction, stacking and be connected to the first N
Between type trap and the epi-layer surface, and in the transverse direction, diffusion region is lightly doped with first N-type and is connected；
The PMOS element regions of one second N-type trap in the epitaxial layer are formed, and on the longitudinal direction, under the epi-layer surface
Side；
A N-type body zone is formed in second N-type trap in the epitaxial layer, and on the longitudinal direction, stack and be connected to this
Between two N-type traps and the epi-layer surface；
The PMOS element regions of one second p-type trap in the epitaxial layer are formed, and on the longitudinal direction, under the epi-layer surface
Side, and in being adjacent to second N-type trap in the transverse direction, and second N-type trap and the second p-type trap one the 2nd PN junctions of formation；
A second grid is formed in the PMOS element regions in the epi-layer surface, on the longitudinal direction, the second grid is stacked simultaneously
It is connected in the epi-layer surface；
With self-aligned processing step, form one second N-type and diffusion region be lightly doped in the epitaxial layer in second N-type trap,
And on the longitudinal direction, stacking and be connected between second N-type trap and the epi-layer surface；
With self-aligned processing step, form one second p-type and diffusion region be lightly doped in the epitaxial layer on the second p-type trap,
And on the longitudinal direction, stacking and be connected between the second p-type trap and the epi-layer surface；
A p-type source electrode is formed in the epitaxial layer in second N-type trap, and on the longitudinal direction, stacking and be connected to the 2nd N
Between type trap and the epi-layer surface, and diffusion region is lightly doped in the transverse direction, being connected to the N-type body zone and second N-type
Between；
Formed a p-type drain electrode, in the epitaxial layer on the second p-type trap, and on the longitudinal direction, stack and be connected to this second
Between p-type trap and the epi-layer surface, and in the transverse direction, diffusion region is lightly doped with second p-type and is connected；And
A marker space is formed, is connected between the NMOS element regions and the PMOS element regions, and its depth, from the epi-layer surface
The longitudinal direction of beginning is calculated downwards, is not less than the first p-type trap, first N-type trap, second N-type trap and the second p-type trap
The depth of any region；
Wherein, diffusion region is lightly doped positioned at first p-type in the first PN junctions and first N-type is lightly doped between diffusion region；
Wherein, diffusion region is lightly doped positioned at second p-type in the 2nd PN junctions and second N-type is lightly doped between diffusion region.
19. the complementary metal oxide semiconductor element manufacture method as claimed in claim 18 with double traps, wherein, should
Insulation layer is zone oxidation structure or insulation structure of shallow groove.
20. the complementary metal oxide semiconductor element manufacture method as claimed in claim 18 with double traps, wherein, should
Impurity doping concentration of the impurity doping concentration higher than the first p-type trap of diffusion region is lightly doped in first p-type, and first N-type is light
The impurity doping concentration of doped diffusion region is higher than the impurity doping concentration of first N-type trap.
21. the complementary metal oxide semiconductor element manufacture method as claimed in claim 18 with double traps, wherein, should
Impurity doping concentration of the impurity doping concentration higher than the second p-type trap of diffusion region is lightly doped in second p-type, and second N-type is light
The impurity doping concentration of doped diffusion region is higher than the impurity doping concentration of second N-type trap.
22. the complementary metal oxide semiconductor element manufacture method as claimed in claim 18 with double traps, wherein, also
Comprising one n type buried layer of formation in the substrate and the epitaxial layer, and positioned at its junction, and on the longitudinal direction, it is connected to the 2nd P
Below type trap.
23. the complementary metal oxide semiconductor element manufacture method as claimed in claim 18 with double traps, wherein, should
Marker space includes a deep trench insulated structure.
24. the complementary metal oxide semiconductor element manufacture method as claimed in claim 18 with double traps, wherein, should
Marker space includes:
One p-type marker space, is formed at the NMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the epi-layer surface
Lower section, and in being adjacent to first N-type trap in the transverse direction；And
One N-type marker space, is formed at the PMOS element regions in the epitaxial layer, and on the longitudinal direction, positioned at the epi-layer surface
Lower section, and in being adjacent to the second p-type trap in the transverse direction.
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| US20050006701A1 (en) * | 2003-07-07 | 2005-01-13 | Tzu-Chiang Sung | High voltage metal-oxide semiconductor device |
| CN101359688A (en) * | 2007-07-31 | 2009-02-04 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| CN101484985A (en) * | 2005-07-25 | 2009-07-15 | 飞思卡尔半导体公司 | Semiconductor devices and method of fabrication |
| CN107026199A (en) * | 2016-02-02 | 2017-08-08 | 立锜科技股份有限公司 | Metal oxide semiconductor device and its manufacture method with double traps |
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2016
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050006701A1 (en) * | 2003-07-07 | 2005-01-13 | Tzu-Chiang Sung | High voltage metal-oxide semiconductor device |
| CN1577892A (en) * | 2003-07-07 | 2005-02-09 | 台湾积体电路制造股份有限公司 | High voltage metal-oxide semiconductor device |
| CN101484985A (en) * | 2005-07-25 | 2009-07-15 | 飞思卡尔半导体公司 | Semiconductor devices and method of fabrication |
| CN101359688A (en) * | 2007-07-31 | 2009-02-04 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| CN107026199A (en) * | 2016-02-02 | 2017-08-08 | 立锜科技股份有限公司 | Metal oxide semiconductor device and its manufacture method with double traps |
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