CN107293487A - Fin formula field effect transistor and forming method thereof - Google Patents
Fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN107293487A CN107293487A CN201610206325.4A CN201610206325A CN107293487A CN 107293487 A CN107293487 A CN 107293487A CN 201610206325 A CN201610206325 A CN 201610206325A CN 107293487 A CN107293487 A CN 107293487A
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- 238000000137 annealing Methods 0.000 claims abstract description 53
- 230000004888 barrier function Effects 0.000 claims description 79
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- 230000003247 decreasing effect Effects 0.000 claims description 8
- 230000007423 decrease Effects 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
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- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
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- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 208000027418 Wounds and injury Diseases 0.000 description 5
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A kind of fin formula field effect transistor and forming method thereof, wherein method includes：Semiconductor substrate is provided；The mask layer with opening is formed on the semiconductor substrate；Using the mask layer as mask, ion implanting is carried out to Semiconductor substrate along the opening, ion area is formed in the Semiconductor substrate of the open bottom；Made annealing treatment, the ion area is spread to both sides, part ion area is covered by mask layer, form the fin ion area covered by the mask layer；After annealing, continue using the mask layer as mask, remove the open bottom part semiconductor substrate, form fin；Formed after fin, remove the mask layer.Methods described can reduce the OFF leakage current of fin formula field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of fin formula field effect transistor and its formation
Method.
Background technology
MOS transistor is one of most important element in modern integrated circuits.The basic knot of MOS transistor
Structure includes：Semiconductor substrate；Positioned at the grid structure of semiconductor substrate surface, positioned at grid structure side
Source region in Semiconductor substrate and the drain region in grid structure opposite side Semiconductor substrate.MOS crystal
The operation principle of pipe is：By applying voltage in grid structure, regulation passes through grid structure bottom channel
Electric current produces switching signal.
With the development of semiconductor technology, the control of the MOS transistor of traditional plane formula to channel current
Ability dies down, and causes serious leakage current.And fin formula field effect transistor (Fin FET) is a kind of emerging
Multi-gate device, generally comprise the fin for protruding from semiconductor substrate surface, fin described in covering part
The grid structure of top surface and sidewall surfaces, source region in the fin of grid structure side and is located at
Drain region in the fin of grid structure opposite side.
However, the OFF leakage current of the fin formula field effect transistor of prior art formation is larger.
The content of the invention
The problem of present invention is solved is to provide a kind of fin formula field effect transistor and forming method thereof, to reduce
The OFF leakage current of fin formula field effect transistor.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：
Semiconductor substrate is provided；The mask layer with opening is formed on the semiconductor substrate；With the mask
Layer is mask, ion implanting is carried out to Semiconductor substrate along the opening, in partly leading for the open bottom
Ion area is formed in body substrate；Made annealing treatment, the ion area is spread to both sides, part ion
Area is covered by mask layer, forms the fin ion area covered by the mask layer；After annealing, continue
Using the mask layer as mask, the open bottom part semiconductor substrate is removed, fin is formed；Formed
After fin, the mask layer is removed.
Optionally, the ion energy of the ion implanting is 1KeV~500KeV, and ion dose is
1E12atom/cm2~1E16atom/cm2, ion implantation angle is 0 degree~45 degree.
Optionally, the depth of the ion implanting is 300 angstroms~10000 angstroms.
Optionally, when the type of the fin formula field effect transistor is N-type, the ion of the ion implanting
For N-type ion or p-type ion.
Optionally, when the type of the fin formula field effect transistor is p-type, the ion of the ion implanting
For N-type ion or p-type ion.
Optionally, the annealing is laser annealing, rapid thermal annealing or spike annealing.
Optionally, the gas used that makes annealing treatment is N2, temperature is 750 degrees Celsius~1300 degrees Celsius.
Optionally, the technique for removing the part semiconductor substrate of the open bottom is anisotropy dry etching work
Skill.
Optionally, in addition to：In the side wall formation side wall of the mask layer；Using the mask layer as mask
While using the side wall as mask, along it is described opening to Semiconductor substrate carry out ion implanting, described
Ion area is formed in the Semiconductor substrate of open bottom；Removing the part semiconductor lining of the open bottom
Before bottom, the side wall is removed.
Optionally, carry out after the annealing, removing the part semiconductor lining of the open bottom
Before bottom, in addition to：Remove the mask layer of partial width.
Optionally, the Semiconductor substrate has first area and second area；The opening includes being located at
The first of first area is open and is open positioned at second area second；The ion area includes being located at the firstth area
The first ion area in domain and the second ion area positioned at second area；The fin includes being located at first area
The first fin and the second fin positioned at second area；The fin ion area includes being located at first area
The first fin ion area and the second fin ion area positioned at second area；Using the mask layer as mask,
Ion implanting, the shape in the Semiconductor substrate of the open bottom are carried out to Semiconductor substrate along the opening
The step of into ion area, includes：Form the second barrier layer of covering second opening；With the described second resistance
Barrier and mask layer are mask, the first ion implanting are carried out to Semiconductor substrate along the first opening, in institute
The first ion area is formed in the Semiconductor substrate for stating the first open bottom；Remove behind the second barrier layer, formed
Cover the first barrier layer of first opening；Using first barrier layer and mask layer as mask, along
Second opening carries out the second ion implanting to Semiconductor substrate, is served as a contrast in the semiconductor of second open bottom
The second ion area is formed in bottom；Remove first barrier layer；After annealing, the first ion area
Spread with the second ion area to both sides, part the first ion area and part the second ion area are by the mask layer
Covering, forms the first fin ion area and the second fin ion area covered by the mask layer；Continue with
The mask layer is mask, removes the open bottom part semiconductor substrate, and the step of forming fin is wrapped
Include：The first open bottom part semiconductor substrate is removed, the first fin is formed in first area；Remove the
Two open bottom part semiconductor substrates, in second area the second fin of formation.
Optionally, in addition to：In side wall the first side wall of formation of the mask layer of first area；Form first
After side wall, second barrier layer is formed；While using second barrier layer and mask layer as mask with
First side wall is mask, the first ion implanting is carried out to Semiconductor substrate along the first opening, in institute
The first ion area is formed in the Semiconductor substrate for stating the first open bottom；Remove behind second barrier layer,
In side wall the second side wall of formation of the mask layer of second area；Formed after the second side wall, form described first
Barrier layer；Using second side wall as mask while using first barrier layer and mask layer being mask,
The second ion implanting is carried out to Semiconductor substrate along the second opening, in partly leading for second open bottom
The second ion area is formed in body substrate；Before the part semiconductor substrate of first open bottom is removed,
Remove the first side wall；Before the part semiconductor substrate of second open bottom is removed, second is removed
Side wall.
Optionally, carry out after the annealing, partly led in the part for removing first open bottom
Before body substrate, in addition to：Remove the mask layer of first area partial width；Carry out the annealing
Afterwards, before the part semiconductor substrate of second open bottom is removed, in addition to：Remove second
The mask layer of region partial width.
The present invention also provides a kind of fin formula field effect transistor, including：Semiconductor substrate；Fin, is located at
In the Semiconductor substrate；Fin ion area, in the fin, and positioned at the side wall of the fin,
The concentration of the fin ion area intermediate ion is successively decreased from fin side wall into fin.
Optionally, the Semiconductor substrate has first area and second area；The fin includes being located at
First fin of first area and the second fin positioned at second area；The fin ion area includes being located at
First fin ion area of first area and the second fin ion area positioned at second area；First fin
Ion area of portion is located in the first fin, and in the side wall of the first fin, the first fin ion area
The concentration of ion is successively decreased from the first fin side wall into the first fin；The second fin ion area is located at the
In two fins, and positioned at the side wall of the second fin, the concentration of the ion in the second fin ion area by
Second fin side wall successively decreases into the second fin.
Compared with prior art, technical scheme has advantages below：
Annealing makes the ion area be spread to both sides, because the diffusion of ion area intermediate ion is by highly concentrated
Degree region is carried out to low concentration region, and the ion area intermediate ion of the mask layer covering is dense after annealing
That spends is distributed as：Perpendicular to ion area side wall on ion area direction from inside to outside, mask layer covering
The descending concentrations of ion area intermediate ion；Because the ion area that mask layer is covered forms fin ion area so that
Formed after fin, fin ion area's intermediate ion concentration is distributed as：On the direction perpendicular to fin side wall,
From the descending concentrations of fin side wall fin ion area intermediate ion into fin.Due to fin ion area intermediate ion
Concentration is successively decreased from fin side wall into fin so that from fin side wall on direction into fin, fin
The depletion layer of middle formation further extends into fin, adds in fin depletion layer perpendicular to fin side
Depth of the wall from fin side wall into fin on direction so that under OFF state in fin channel region it is removable
Dynamic carrier is reduced, so as to reduce the OFF leakage current of fin formula field effect transistor.
Brief description of the drawings
Fig. 1 to Fig. 5 is that the structure of fin formula field effect transistor forming process in first embodiment of the invention is shown
It is intended to；
Fig. 6 to Figure 12 is that the structure of fin formula field effect transistor forming process in second embodiment of the invention is shown
It is intended to；
Figure 13 to Figure 15 is the structure of fin formula field effect transistor forming process in third embodiment of the invention
Schematic diagram；
Figure 16 to Figure 24 is the structure of fin formula field effect transistor forming process in fourth embodiment of the invention
Schematic diagram.
Embodiment
The fin formula field effect transistor of prior art formation, what is pointed to perpendicular to fin side wall into fin
On direction, the ion concentration adulterated in the fin of fin formula field effect transistor is uniformly distributed, close in fin
The region of fin portion surface is easier the consumption for exhausting, being formed in fin than the region away from fin portion surface in fin
Layer is located at close to the region of fin portion surface to the greatest extent so that the depth of depletion layer is smaller, causes the current-carrying under OFF state
It is sub easily to be flowed through from the region away from fin portion surface, and the carrier in fin flows through the fin of depletion layer sidepiece
Portion, the depth of the depletion layer is bigger under OFF state, and moveable carrier is fewer in fin, the consumption
The depth of layer to the greatest extent is smaller, and moveable carrier is more in fin, so as to cause the fin effect under OFF state
Answer the leakage current of transistor larger.
Research find, if perpendicular to fin side wall from the direction that fin side wall is pointed into fin, fin
The ion concentration adulterated in portion is successively decreased, can reduce in fin away from fin portion surface region intermediate ion it is dense
Degree, so that perpendicular to fin side wall, from fin side wall on the direction into fin, fin
The depletion layer of middle formation further extends into fin, increase depletion layer perpendicular to fin side wall to fin
Depth on interior pointing direction, so that moveable carrier is reduced in OFF state lower channel area,
So as to reduce the OFF leakage current of fin formula field effect transistor.
On this basis, the present invention provides a kind of forming method of fin formula field effect transistor, including：Carry
For Semiconductor substrate；The mask layer with opening is formed on the semiconductor substrate；With the mask layer
For mask, ion implanting is carried out to Semiconductor substrate along the opening, in the semiconductor of the open bottom
Ion area is formed in substrate；Made annealing treatment, the ion area is spread to both sides, part ion area
Covered by mask layer, form the fin ion area covered by the mask layer；After annealing, continue with
The mask layer is mask, removes the open bottom part semiconductor substrate, forms fin；Form fin
Behind portion, the mask layer is removed.Methods described can reduce the OFF leakage current of fin formula field effect transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
First embodiment
Fig. 1 to Fig. 5 is that the structure of fin formula field effect transistor forming process in first embodiment of the invention is shown
It is intended to.
With reference to Fig. 1, there is provided Semiconductor substrate 100；Being formed in the Semiconductor substrate 100 has opening
121 mask layer 120.
The Semiconductor substrate 100 provides technique platform to be subsequently formed fin formula field effect transistor.It is described
Semiconductor substrate 100 can be silicon, germanium, SiGe, carborundum or GaAs；The Semiconductor substrate
100 can also be monocrystalline silicon, polysilicon, non-crystalline silicon or silicon-on-insulator；It is described partly to lead in the present embodiment
The material of body substrate 100 is silicon.
The mask layer 120 is hard mask layer, and the material of the mask layer 120 can be silicon nitride, carbon
SiClx or silica.
Formed mask layer 120 the step of be：Mask layer is formed in the Semiconductor substrate 100,
Then the graphical mask layer, so as to form the mask layer 120 with opening 121.
In the present embodiment, before the mask layer is formed, it can also include：In the semiconductor
Etching barrier layer 110 is formed on substrate 100, it act as：(1) in the graphical mask layer
During, protect the surface of Semiconductor substrate 100, it is to avoid Semiconductor substrate 100 is by etching injury；(2)
During subsequent ion injects, reduction Semiconductor substrate 100 is damaged by ion implanting.At it
In its embodiment, etching barrier layer can not be formed.
The material of the etching barrier layer 110 is silica.
It should be noted that the mask layer 120 material and the etching barrier layer 110 material not
Together so that during the graphical mask layer, to the etch rate of etching barrier layer 110
Less than the etch rate to mask layer, the surface of Semiconductor substrate 100 is protected, it is to avoid semiconductor is served as a contrast
Bottom 100 is by etching injury.
It is mask with the mask layer 120 with reference to Fig. 2, along 121 pairs of Semiconductor substrates 100 of the opening
Ion implanting is carried out, ion area 130 is formed in the Semiconductor substrate 100 of 121 bottoms of the opening.
In the present embodiment, during ion implanting is carried out, due to the presence of etching barrier layer 110,
Ion implanting can be avoided to directly act on Semiconductor substrate 100, thus reduce Semiconductor substrate 100 by
The damage of the ion implanting.
When the type of the fin formula field effect transistor is N-type, the ion of the ion implanting is N-type
Ion or p-type ion；When the type of the fin formula field effect transistor is p-type, the ion note
The ion entered is N-type ion or p-type ion.The N-type ion for example can be P (phosphorus) ion
Or As ions, the p-type ion for example can be B ions or In ions.
The ion energy of the ion implanting is 1KeV~500KeV, and ion dose is
1E12atom/cm2~1E16atom/cm2, ion implantation angle is 0 degree~45 degree, the ion implanting
Angle refers to the angle formed between the normal to a surface of Semiconductor substrate 100.
The meaning of the ion dose scope of ion implanting selection is：If the ionic agent of the ion implanting
Amount is less than 1E12atom/cm2, cause the average value mistake of the ion concentration in the fin ion area that is subsequently formed
It is small, cause the ON state current of fin field-effect transistor too small；If the ion dose of the ion implanting is big
In 1E16atom/cm2, cause technique to waste.
The meaning of the ion energy range of ion implanting selection is：If the ion energy of the ion implanting
Amount is less than 1KeV, and the depth for being injected into Semiconductor substrate 100 is too small；If the ion energy of the ion implanting
Amount is more than 500KeV, causes the implant damage to Semiconductor substrate 100 excessive.
The depth of the ion implanting is 300 angstroms~10000 angstroms, the model of the depth selection of the ion implanting
Enclose with following meaning：If the depth of the ion implanting is less than 300 angstroms, cause the fin being subsequently formed
Ion area is too small in the height in the surface direction of Semiconductor substrate 100, the height in fin ion area
The ratio for occupying fin height is too small, it is impossible to effectively reduce the OFF leakage current of fin formula field effect transistor；
If the depth of the ion implanting is more than 10000 angstroms, cause the implant damage mistake to Semiconductor substrate 100
Greatly.
With reference to Fig. 3, formed behind the ion area 130, made annealing treatment, make the ion area 130 to
Both sides are spread, and part ion area 130 is covered by mask layer 120, and formation is covered by the mask layer 120
Fin ion area.
The annealing is laser annealing, rapid thermal annealing or spike annealing.
The gas used that makes annealing treatment is N2, temperature is 750 degrees Celsius~1300 degrees Celsius.
The annealing selects the meaning of this temperature range to be：If the temperature of the annealing is less than
750 degrees Celsius, cause the ion being unable in active ions area 130；If the temperature of the annealing is more than
1300 degrees Celsius, cause heat budget excessive, reduce the reliability of fin formula field effect transistor.
It should be noted that during the annealing is carried out, the ion area 130 not only can
Spread, also can be downwards diffused along the normal to a surface of Semiconductor substrate 100 to both sides.The ion
Area 130 is referred to both sides diffusion：Perpendicular to ion area 130 side wall by ion area 130 from inside to outside
Side is diffused up.
The diffusion in the ion area 130 be as caused by being diffused the ion in ion area 130,
In the annealing, on the one hand, the ion in ion area 130 spreads to both sides, on the other hand, from
Ion in sub-district 130 is diffused downwards along the normal to a surface of Semiconductor substrate 100；Ion area 130
After being spread to both sides, the ion area 130 of part is covered by mask layer 120, due to the diffusion of ion be by
The region of high concentration is carried out to the region of low concentration, so that the ion area 130 that mask layer 120 is covered
In ion concentration be distributed as：In the side perpendicular to the side wall of ion area 130 by ion area 130 from inside to outside
Upwards, the descending concentrations for the intermediate ion of ion area 130 that mask layer 120 is covered.
For convenience of explanation, after annealing, the ion area 130 that mask layer 120 is covered is referred to as fin
Ion area.It is subsequently formed after fin, fin ion area is located in fin, and positioned at the side wall of fin.
With reference to Fig. 4, after annealing, it is mask to continue with the mask layer 120, removes the opening
121 (referring to Fig. 3) base section Semiconductor substrates 100, form fin 140.
Specifically, the technique for removing the part semiconductor substrate 100 of 121 bottoms of the opening is each to different
Property dry carving technology, such as anisotropic plasma etch technique or reactive ion etching process.
Ion area 130 can be more than or equal to by removing the thickness of 121 base section Semiconductor substrates 100 of opening
Thickness, might be less that the thickness in ion area 130, the Semiconductor substrate 100 of the bottom of opening 121
Thickness and the thickness in ion area 130 refer to the chi in the surface direction of Semiconductor substrate 100
It is very little.
, also can be by while the part semiconductor substrate 100 of 121 bottoms of opening is removed in the present embodiment
The etching barrier layer 110 of 121 bottoms of being open is removed in the lump；In other embodiments, when no formed is carved
When losing barrier layer 110, without entering to be about to the step of etching barrier layer 110 of 121 bottoms of opening is removed.
It should be noted that being formed after fin 140, fin 140 exposes the table in fin ion area 141
Face, fin ion area 141 is located in fin 140, and positioned at the side wall of fin 140.Due to mask layer
Ion concentration in the ion areas 130 of 120 coverings is distributed as：Perpendicular to the side wall of ion area 130 by from
On the direction of sub-district 130 from inside to outside, the descending concentrations for the intermediate ion of ion area 130 that mask layer 120 is covered,
So that being formed after fin 140, the concentration of the intermediate ion of fin ion area 141 is distributed as：Vertical
In on the direction of the side wall of fin 140, from the side wall of fin 140 into fin 140, fin ion area 141
The descending concentrations of intermediate ion.
With reference to Fig. 5, formed after fin 140, remove the mask layer 120 (referring to Fig. 4).
The technique for removing the mask layer 120 is dry carving technology or wet-etching technique.
In the present embodiment, remove after the mask layer 120, in addition to：Remove the bottom of mask layer 120
Etching barrier layer 110；In other embodiments, when not forming etching barrier layer, it is not necessary to gone
Except mask layer bottom etching barrier layer the step of.
Due to foring the fin 140 with fin ion area 141, the intermediate ion of fin ion area 141
Concentration successively decreased from the side wall of fin 140 into fin 140 so that perpendicular to the side wall of fin 140 by fin
On the direction that the side wall of portion 140 is pointed into fin 140, the depletion layer formed in fin 140 is to fin 140
Interior further extension, add depletion layer perpendicular to the side wall of fin 140 from the side wall of fin 140 to fin
Depth in 140, so that moveable carrier in the channel region of fin formula field effect transistor under OFF state
Reduce, so as to reduce the OFF leakage current of fin formula field effect transistor.
In the present embodiment, it can also include：Shape in Semiconductor substrate 100 between adjacent fin 140
Into isolation structure, the top surface of the isolation structure is less than the top surface of the fin 140；Formed
Across the grid structure of the fin 140, the grid structure is located on isolation structure, covering part fin
The top surface and side wall in portion 140.
In the present embodiment, the fin formula field effect transistor of formation, with reference to Fig. 5, including：Semiconductor substrate
100；Fin 140, in the Semiconductor substrate 100；Fin ion area 141, positioned at the fin
In portion 140, and positioned at the side wall of the fin 140, the concentration of the intermediate ion of fin ion area 141
Successively decreased from the side wall of fin 140 into fin 140.
Second embodiment
Fig. 6 to Figure 12 is that the structure of fin formula field effect transistor forming process in second embodiment of the invention is shown
It is intended to.
The difference of second embodiment and first embodiment is：Also include：In the side wall shape of the mask layer
Into side wall；Using the side wall as mask while using the mask layer being mask, half-and-half led along the opening
Body substrate carries out ion implanting, and ion area is formed in the Semiconductor substrate of the open bottom；Removing
Before the part semiconductor substrate of the open bottom, the side wall is removed.
In the present embodiment, the width in fin ion area can be adjusted according to the thickness of side wall, the fin from
The width of sub-district is referred in the size in fin sidewall direction, so that it is brilliant to adjust fin field effect
The threshold voltage of body pipe.
It is the step of the side wall formation side wall of the mask layer：With reference to Fig. 6, Fig. 6 is on the basis of Fig. 1
The schematic diagram of formation, in the side wall and the top surface of bottom and mask layer 120 of the opening 121
Form spacer material layer 220；With reference to Fig. 7, the spacer material layer positioned at the top surface of mask layer 120 is removed
220, so that in the side wall formation side wall 221 of the mask layer 120.
Specifically, the material of the spacer material layer 220 is silicon nitride or silica, and the side wall material
The material of the bed of material 220 is different with the material of mask layer 120 so that follow-up to remove the side wall 221
During, the etch rate to mask layer 120 is more than to the etch rate of side wall 221, to side wall 221
Etch rate there is high etching selection ratio relative to the etch rate to mask layer 120, beneficial to follow-up
Remove side wall 221.
The technique for forming the spacer material layer 220 is depositing operation, such as plasma activated chemical vapour deposition
Technique, sub-atmospheric pressure chemical vapor deposition method or low-pressure chemical vapor deposition process；Remove and be located at mask
The technique of the spacer material layer 220 of 120 top surface of layer is anisotropy dry carving technology.
Then, with the side wall 221 it is mask while with the mask layer 120 being mask with reference to Fig. 8,
Ion implanting is carried out along described 121 pairs of Semiconductor substrates 100 of opening, half in 121 bottoms of the opening
Ion area 230 is formed in conductor substrate 100.
The parameter that the parameter of the ion implanting is used with reference to the injection of first embodiment intermediate ion is carried out, no longer
It is described in detail.
Then, with reference to Fig. 9, made annealing treatment, the ion area 230 is spread to both sides, partly from
Sub-district 230 is covered by mask layer 120, forms the fin ion area covered by mask layer 120.
It is subsequently formed after fin, the fin ion area is located in fin, and positioned at the side wall of fin.
The parameter of the annealing is carried out with reference to the parameter made annealing treatment in first embodiment, is no longer described in detail.
Then, with reference to Figure 10, the side wall 221 (referring to Fig. 9) is removed.
The technique for removing the side wall 221 is dry carving technology or wet-etching technique.
Then, with reference to Figure 11, the part semiconductor lining of 121 (referring to Figure 10) bottoms of the opening is removed
Bottom 100, forms fin 240.
The technique of part semiconductor substrate 100 of 121 bottoms of the opening is removed with reference to first embodiment,
No longer it is described in detail.
, also can be by while the part semiconductor substrate 100 of 121 bottoms of opening is removed in the present embodiment
The etching barrier layer 110 of 121 bottoms of being open is removed in the lump；In other embodiments, when no formed is carved
When losing barrier layer, without entering to be about to the step of etching barrier layer of open bottom is removed.
Formed after fin 240, fin ion area 241 is located in fin 240, and positioned at fin 240
Side wall, the concentration distribution of the intermediate ion of fin ion area 241 is：In the direction perpendicular to the side wall of fin 240
On, from the side wall of fin 240 into fin 240, the descending concentrations of the intermediate ion of fin ion area 241.
It should be noted that in the present embodiment, after being made annealing treatment and in the removal opening 121
The step of side wall 221 being removed before the part semiconductor substrate 100 of bottom；In other embodiments,
Can be：Carry out being removed side wall 221 after the ion implanting and before the annealing is carried out
The step of.
The width in the fin ion area 241 to be formed, fin ion area 241 are adjusted according to the thickness of side wall 221
The change of width can change the threshold voltage of fin formula field effect transistor, specifically, working as fin field effect
Transistor is N-type fin formula field effect transistor, when the ion in fin ion area 241 is p-type, with
The width in fin ion area 241 reduces, the threshold voltage reduction of fin formula field effect transistor；When fin
Effect transistor is N-type fin formula field effect transistor, as the ion in fin ion area 241 is N-type
When, the width in fin ion area 241 reduces, the threshold voltage rise of fin formula field effect transistor；Work as fin
The ion that formula field-effect transistor is in p-type fin formula field effect transistor, fin ion area 241 is N-type
When, reduce with the width in fin ion area 241, the threshold voltage reduction of fin formula field effect transistor；
241 ion is P in fin formula field effect transistor is p-type fin formula field effect transistor, fin ion area
During type, reduce with the width in fin ion area 241, the threshold voltage rise of fin formula field effect transistor.
Then, with reference to Figure 12, the mask layer 120 (referring to Figure 11) is removed.
The technique of the mask layer 120 is removed with reference to first embodiment, is no longer described in detail.
In the present embodiment, remove after the mask layer 120, in addition to：Remove the bottom of mask layer 120
Etching barrier layer 110；In other embodiments, when not forming etching barrier layer, it is not necessary to gone
Except mask layer bottom etching barrier layer the step of.
In the present embodiment, it can also include：Shape in Semiconductor substrate 100 between adjacent fin 240
Into isolation structure, the top surface of the isolation structure is less than the top surface of the fin 240；Formed
Across the grid structure of the fin 240, the grid structure is located on isolation structure, covering part fin
The top surface and side wall in portion 240.
In the present embodiment, the fin formula field effect transistor of formation, with reference to Figure 12, including：Semiconductor substrate
100；Fin 240, in the Semiconductor substrate 100；Fin ion area 241, positioned at the fin
In portion 240, and positioned at the side wall of fin 240, the concentration of the intermediate ion of fin ion area 241 is by fin
The side wall of portion 240 successively decreases into fin 240.
3rd embodiment
Figure 13 to Figure 15 is the structure of fin formula field effect transistor forming process in third embodiment of the invention
Schematic diagram.
The difference of 3rd embodiment and first embodiment is：Carry out after the annealing and removing
Before the part semiconductor substrate of the open bottom, in addition to：Remove the mask layer of partial width, institute
State width and refer to the size in mask layer sidewall direction.
In the present embodiment, the width of the opening can be adjusted according to the width of mask layer is removed, so that
Adjust the width of the corresponding Semiconductor substrate of open bottom so that the width in the fin ion area formed in fin
Degree is adjusted, and the width in the fin ion area refers to the size in fin sidewall direction,
So as to adjust the threshold voltage of fin formula field effect transistor, specifically, when fin formula field effect transistor is N
When ion in type fin formula field effect transistor, fin ion area is p-type, with the width in fin ion area
Degree reduces, the reduction of fin formula field effect transistor threshold voltage；When fin formula field effect transistor is N-type fin
When ion in field-effect transistor, fin ion area is N-type, reduce with the width in fin ion area,
The threshold voltage rise of fin formula field effect transistor；When fin formula field effect transistor is p-type fin field effect
When ion in transistor, fin ion area is N-type, reduce with the width in fin ion area, fin
Field-effect transistor threshold voltage is reduced；When fin formula field effect transistor be p-type fin formula field effect transistor,
When ion in fin ion area is p-type, reduce with the width in fin ion area, fin field effect is brilliant
The threshold voltage rise of body pipe.
With reference to Figure 13, Figure 13 is the schematic diagram that is formed on the basis of Fig. 3, after carrying out the annealing,
Remove the mask layer 120 of partial width.
The method for removing the mask layer 120 of partial width is dry etching or wet etching.
With reference to Figure 14, after the mask layer 120 for removing partial width, the opening 121 is removed (with reference to figure
13) the part semiconductor substrate 100 of bottom.
The technique of part semiconductor substrate 100 of 121 bottoms of the opening is removed with reference to first embodiment,
No longer it is described in detail.
The part semiconductor substrate 100 of 121 bottoms of the opening is removed, so as to form fin 340；Formed
After fin 340, fin ion area 341 is located in fin 340, and fin ion area 341 is located at fin
340 side walls, the concentration of the intermediate ion of fin ion area 341 is distributed as：Perpendicular to the side of fin 340
On the direction of wall, from the side wall of fin 340 into fin 340, the concentration of the intermediate ion of fin ion area 341
Successively decrease.
, also can be by while the part semiconductor substrate 100 of 121 bottoms of opening is removed in the present embodiment
The etching barrier layer 110 of 121 bottoms of being open is removed in the lump；In other embodiments, when no formed is carved
When losing barrier layer, without entering to be about to the step of etching barrier layer of open bottom is removed.
Then, with reference to Figure 15, the mask layer 120 (referring to Figure 14) is removed.
The technique of the mask layer 120 is removed with reference to first embodiment, is no longer described in detail.
In the present embodiment, remove after the mask layer 120, in addition to：Remove the bottom of mask layer 120
Etching barrier layer 110；In other embodiments, when not forming etching barrier layer, it is not necessary to gone
Except mask layer bottom etching barrier layer the step of.
In the present embodiment, the fin formula field effect transistor of formation, with reference to Figure 15, including：Semiconductor substrate
100；Fin 340, in the Semiconductor substrate 100；Fin ion area 341, positioned at the fin
In portion 340, and positioned at the side wall of the fin 340, and the intermediate ion of fin ion area 341 is dense
Degree is successively decreased from the side wall of fin 340 into fin 340.
In the present embodiment, it can also include：Shape in Semiconductor substrate 100 between adjacent fin 340
Into isolation structure, the top surface of the isolation structure is less than the top surface of the fin 340；Formed
Across the grid structure of the fin 340, the grid structure is located on isolation structure, covering part fin
The top surface and side wall in portion 340.
Fourth embodiment
Fourth embodiment is with the first difference implemented：The Semiconductor substrate has first area and
Two regions；The opening includes being open and being open positioned at second area second positioned at the first of first area；
The ion area is included positioned at the first ion area and the second ion area positioned at second area of first area；
The fin includes the first fin and the second fin positioned at second area positioned at first area；The fin
Ion area of portion include positioned at first area the first fin ion area and positioned at second area the second fin from
Sub-district.Comprise the following steps that description.
Figure 16 to Figure 24 is the structure of fin formula field effect transistor forming process in fourth embodiment of the invention
Schematic diagram.
With reference to Figure 16 there is provided Semiconductor substrate 300, the Semiconductor substrate 300 has first area (I
Region) and second area (II region).
The type of the follow-up fin formula field effect transistor formed in first area and subsequently formed in second area
Fin formula field effect transistor type on the contrary, when first area be used for form N-type fin field effect crystal
Guan Shi, second area is used to form p-type fin formula field effect transistor, when first area is used to form p-type
During fin formula field effect transistor, second area is used to form N-type fin formula field effect transistor.
With continued reference to Figure 16, being formed in the Semiconductor substrate 300 has the first opening 321 and second
The mask layer 320 of opening 322, first opening 321 is located at first area, second opening 322
Positioned at second area.
Specifically, forming mask layer (not shown) first in the Semiconductor substrate 300, then
The graphical mask layer, so as to form the mask with the first opening 321 and the second opening 322
Layer.The mask layer 320 is hard mask layer, and the material of the mask layer 320 is silicon nitride, carborundum
Or silica.
In the present embodiment, before the mask layer is formed, it can also include：In the semiconductor
Etching barrier layer 310 is formed on substrate 300, it act as：(1) in the graphical mask layer
During, protect the surface of Semiconductor substrate 300, it is to avoid Semiconductor substrate 300 is by etching injury；(2)
During follow-up first ion implanting, reduction Semiconductor substrate 300 is damaged by the first ion implanting
Wound, during follow-up second ion implanting, reduction Semiconductor substrate 300 is by the second ion implanting
Damage.In other embodiments, etching barrier layer can not be formed.
The material of the etching barrier layer 310 can be silica.
It should be noted that the mask layer 320 material and the etching barrier layer 310 material not
Together so that during the graphical mask layer, to the etch rate of etching barrier layer 310
Less than the etch rate to mask layer, the surface of Semiconductor substrate 300 is protected, it is to avoid semiconductor is served as a contrast
Bottom 300 is by etching injury.
With reference to Figure 17, the second barrier layer 331 of covering second opening 322 is formed.
The material on second barrier layer 331 is photoresist.
In the present embodiment, the second barrier layer 331 of covering second area, and second barrier layer are formed
331 expose first area.
It is mask with second barrier layer 331 and mask layer 320 with reference to Figure 18, along the first opening
321 pairs of Semiconductor substrates 300 carry out the first ion implanting, the semiconductor in the described first 321 bottoms of opening
The first ion area 340 is formed in substrate 300.
The parameter of first ion implanting is no longer described in detail with reference to the parameter of first embodiment intermediate ion injection.
With reference to Figure 19, remove behind second barrier layer 331, form covering first opening 321
First barrier layer 330.
Formed behind the first ion area 340, remove second barrier layer 331, then formed covering first and open
First barrier layer 330 of mouth 321.
The material on first barrier layer 330 is photoresist.
In the present embodiment, remove behind second barrier layer 331, form the first resistance of covering first area
Barrier 330, and first barrier layer 330 exposes second area.
It is mask with first barrier layer 330 and mask layer 320 with reference to Figure 20, along the second opening
322 pairs of Semiconductor substrates 300 carry out the second ion implanting, the semiconductor in the described second 322 bottoms of opening
The second ion area 341 is formed in substrate 300.
The parameter that the parameter of second ion implanting is used with reference to the injection of first embodiment intermediate ion, no longer
It is described in detail.
With reference to Figure 21, first barrier layer 330 (referring to Figure 20) is removed.
Then, with reference to Figure 22, made annealing treatment, make ion area of the first ion area 340 and second
341 spread to both sides, and part the first ion area 340 and part the second ion area 341 are by the mask layer
320 coverings, form the first fin ion area covered by first area mask layer 320 and second area mask
The second fin ion area that floor 320 is covered.
The parameter of the annealing is no longer described in detail with reference to the parameter that use is made annealing treatment in first embodiment.
It should be noted that during the annealing is carried out, the first ion area 340 is not
It can only spread, also can downwards be expanded along the normal to a surface of first area Semiconductor substrate 300 to both sides
Dissipate, the ion in the second ion area 341 can be not only diffused to both sides, also can be along the secondth area
The normal to a surface of Semiconductor substrate 300 in domain is diffused downwards.
After ion in first ion area 340 spreads to both sides, part the first ion area 340 is by the firstth area
The mask layer 320 in domain is covered, and part the second ion area 341 is covered by the mask layer 320 of second area,
Because ion diffusion is the region progress from the region of high concentration to low concentration, so first area mask layer
The concentration distribution of the intermediate ions of the first ion area 340 of 320 coverings is：Perpendicular to the side of the first ion area 340
Wall is on the first ion area 340 direction from inside to outside, the first ion that first area mask layer 320 is covered
The descending concentrations of the intermediate ion of area 340；Second area mask layer 320 cover the second ion area 341 in from
Son concentration distribution be：Perpendicular to the side wall of the second ion area 341 by the second ion area 341 from inside to outside
On direction, the descending concentrations for the intermediate ion of the second ion area 341 that second area mask layer 320 is covered.
For convenience of explanation, after annealing, the first ion area that first area mask layer 320 is covered
340 are referred to as the first fin ion area, and the second ion area 341 that second area mask layer 320 is covered is referred to as
Second fin ion area.It is subsequently formed after the first fin and the second fin, the first fin ion area is located at the
In one fin, and positioned at the side wall of the first fin, the second fin ion area is located in the second fin, and position
In the second fin side wall.
Then, with reference to Figure 23, the part for removing described first opening, 321 (referring to Figure 22) bottoms is partly led
Body substrate 300, the first fin 350 is formed in first area；Remove the part half of the second 322 bottoms of opening
Conductor substrate 300, in second area the second fin 351 of formation.
Formed after the first fin 350, the first fin 350 exposes the surface in the first fin ion area 352,
First fin ion area 352 is located in the first fin 350, and positioned at the side wall of the first fin 350, institute
The concentration distribution for stating the intermediate ion of the first fin ion area 352 is：Perpendicular to the side wall of the first fin 350
On direction, from the side wall of the first fin 350 into the first fin 350 intermediate ion of first fin ion area 352
Descending concentrations；Formed after the second fin 351, the second fin 351 exposes the second fin ion area 353
Surface, the second fin ion area 353 is located in the second fin 351, and positioned at the second fin 351
Side wall, the intermediate ion concentration distribution of the second fin ion area 353 is：Perpendicular to the second fin 351
On the direction of side wall, from the side wall of the second fin 351 into the second fin 351 second fin ion area 353
The descending concentrations of intermediate ion.
In the present embodiment, the first fin 350 and the second fin 351 are formed in one step, work is simplified
Skill；In other embodiments, the first fin 350 and the second fin can be formed respectively in different step
351。
Remove the part semiconductor substrate 300 of 321 bottoms of the first opening and remove the second opening 322
The technique of the part semiconductor substrate 300 of bottom is anisotropy dry carving technology, such as anisotropic plasma
Body etching technics or reactive ion etching process.
Remove first be open 321 base section Semiconductor substrates 300 thickness can be more than or equal to first from
The thickness of sub-district 340 (referring to Figure 22), might be less that the thickness in the first ion area 340；Remove the
The thickness of two 322 base section Semiconductor substrates 300 of opening can be more than or equal to the second ion area 341
Thickness, might be less that the thickness in the second ion area 341 (referring to Figure 22), first opening 321
The thickness of the Semiconductor substrate 300 of the thickness of the Semiconductor substrate 300 of bottom and the second 322 bottoms of opening
Refer to the size in the surface direction of Semiconductor substrate 100.
In the present embodiment, the part semiconductor lining of the first opening 321 and the second 322 bottoms of opening is being removed
Also can be by the first opening 321 and the etching barrier layer 310 1 of the second 322 bottoms of opening while bottom 300
And remove；In other embodiments, when not forming etching barrier layer, the first opening is about to without entering
The step of being removed with the etching barrier layer of the second open bottom.
Because the first fin ion area 352 and the second fin ion area 353 have above-described ion dense
Degree distribution so that perpendicular to the side wall of the first fin 350 from the side wall of the first fin 350 to the first fin 350
On the direction of interior sensing, the depletion layer formed in the first fin 350 further prolongs into the first fin 350
Stretch, pointed to perpendicular to the side wall of the second fin 351 from the side wall of the second fin 351 into the second fin 351
Direction on, the depletion layer formed in the second fin 351 further extends into the second fin 351, increase
Added in the first fin 350 depletion layer perpendicular to the side wall of the first fin 350 from the side wall of the first fin 350
Depth into the first fin 350 on direction, adds in the second fin 351 depletion layer perpendicular to
Depth of the side wall of two fin 351 from the side wall of the second fin 351 into the second fin 351 on direction, so that
So that the moveable carrier under OFF state in the channel region of first area fin formula field effect transistor subtracts
Few, the moveable carrier under OFF state in the channel region of second area fin formula field effect transistor subtracts
It is few, so as to reduce the OFF leakage current of first area and second area fin formula field effect transistor.
Then, with reference to Figure 24, the mask layer 320 (referring to Figure 23) is removed.
The technique for removing the mask layer 320 is dry carving technology or wet-etching technique.
In the present embodiment, remove after the mask layer 320, in addition to：Remove the bottom of mask layer 320
Etching barrier layer 310.In other embodiments, when not forming etching barrier layer, it is not necessary to gone
The step of except mask layer bottom etching barrier layer.
In the present embodiment, it can also include：Between adjacent first fin 350, adjacent second fin 351
Between and the Semiconductor substrate 300 between the first fin 350 and the second fin 351 on formed isolation
Structure, the top surface of the isolation structure is less than the top of the fin 351 of the first fin 350 and second
Portion surface；It is developed across the grid structure of the fin 351 of the first fin 350 and second, the grid
Structure is located on isolation structure, the top surface of the first fin of covering part 350 and side wall and part the
The top surface and side wall of two fins 351.
In the present embodiment, the fin formula field effect transistor of formation, with reference to Figure 24, including:Semiconductor substrate 300,
The Semiconductor substrate 300 has first area (I regions) and second area (II region)；First fin
Portion 350, in the Semiconductor substrate 300 of first area；Second fin 351, positioned at second area
In Semiconductor substrate 300；First fin ion area 352, in the first fin 350, and positioned at first
The side wall of fin 350, the concentration of the intermediate ion of the first fin ion area 352 is by the side of the first fin 350
Wall successively decreases into the first fin 350；Second fin ion area 353, in the second fin 351, and position
The concentration of ion in the side wall of the second fin 351, the second fin ion area 353 is by the second fin
351 side walls successively decrease into the second fin 351.
5th embodiment
The difference of 5th embodiment and fourth embodiment is：In the side wall of the mask layer of first area
The first side wall is formed, the second barrier layer of the opening of covering second, the second barrier layer exposure is then formed
Go out the first opening；Using second barrier layer, mask layer and the first side wall as mask, along the first opening
First ion implanting is carried out to Semiconductor substrate, formed in the Semiconductor substrate of first open bottom
First ion area；Remove behind second barrier layer, formed in the side wall of the mask layer of second area
Second side wall, then forms the first barrier layer of the opening of covering first, and first barrier layer exposes the
Two openings；Using first barrier layer, mask layer and the second side wall as mask, along the second opening half-and-half
Conductor substrate carries out the second ion implanting, and second is formed in the Semiconductor substrate of second open bottom
Ion area；Before the part semiconductor substrate of first open bottom is removed, the first side wall is removed；
Before the part semiconductor substrate of second open bottom is removed, the second side wall is removed.
The step of removing first side wall can formed the first ion area after and made annealing treatment
Carry out before, can also be after an annealing treatment and in the part semiconductor of removal first open bottom
Carried out before substrate；The step of removing second side wall can formed the second ion area after and entering
Carried out before row annealing, can also be after an annealing treatment and in removal second open bottom
Carried out before part semiconductor substrate.
Specifically, the material of first side wall is silicon nitride or silica, and the material of first side wall
Material is different with the material of mask layer so that follow-up during first side wall is removed, to the first side
The etch rate of wall is more than to the etch rate of mask layer, to the etch rate of the first side wall relative to covering
The etch rate of film layer has high etching selection ratio, beneficial to removing the first side wall；Second side wall
Material is silicon nitride or silica, and the material of second side wall is different with the material of mask layer so that
Subsequently during second side wall is removed, the etch rate of the second side wall is more than to mask layer
Etch rate, has high etching relative to the etch rate to mask layer to the etch rate of the second side wall
Selection ratio, beneficial to removing the second side wall.
In the present embodiment, the width in the first ion area can be adjusted according to the thickness of the first side wall, and can
The width in the second ion area is adjusted according to the thickness of the second side wall, so as to adjust first area and second area
The threshold voltage of corresponding fin formula field effect transistor.Specifically, the width on the first fin ion area
Change and first area fin formula field effect transistor threshold voltage change relation, on the second fin
The change of the width in ion area of portion and the pass of the change of the threshold voltage of second area fin formula field effect transistor
Second embodiment is referred to, is no longer described in detail.
Sixth embodiment
The region of sixth embodiment and fourth embodiment is：Carry out after the annealing, removing
Before the part semiconductor substrate of first open bottom, in addition to：Remove first area partial width
Mask layer；Carry out after the annealing, removing the part semiconductor of second open bottom
Before substrate, in addition to：Remove the mask layer of second area partial width.
In the present embodiment, first opening can be adjusted according to the width of first area mask layer is removed
Width, so as to adjust the width of the corresponding Semiconductor substrate of the first open bottom so that in the first fin
The width in the first fin ion area formed is adjusted；Can be according to the width for removing second area mask layer
Spend to adjust the width of second opening, so as to adjust the corresponding Semiconductor substrate of the second open bottom
Width so that the width in the second fin ion area formed in the second fin is adjusted；So as to adjust the
One region and the threshold voltage of the corresponding fin formula field effect transistor of second area.
Specifically, change and first area fin field effect crystal on the width in the first fin ion area
The relation of the change of the threshold voltage of pipe, on the second fin ion area width change and second area
The relation of the change of the threshold voltage of fin formula field effect transistor is no longer described in detail with reference to second embodiment.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (15)
1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：
Semiconductor substrate is provided；
The mask layer with opening is formed on the semiconductor substrate；
Using the mask layer as mask, ion implanting is carried out to Semiconductor substrate along the opening, opened described
Ion area is formed in the Semiconductor substrate of mouth bottom；
Made annealing treatment, the ion area is spread to both sides, part ion area is covered by mask layer, shape
Into the fin ion area covered by the mask layer；
After annealing, continue using the mask layer as mask, remove the open bottom part semiconductor lining
Bottom, forms fin；
Formed after fin, remove the mask layer.
2. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
The ion energy of ion implanting is 1KeV~500KeV, and ion dose is
1E12atom/cm2~1E16atom/cm2, ion implantation angle is 0 degree~45 degree.
3. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
The depth of ion implanting is 300 angstroms~10000 angstroms.
4. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that work as institute
When the type for stating fin formula field effect transistor is N-type, the ion of the ion implanting for N-type ion or
P-type ion.
5. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that work as institute
When the type for stating fin formula field effect transistor is p-type, the ion of the ion implanting for N-type ion or
P-type ion.
6. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described
Make annealing treatment as laser annealing, rapid thermal annealing or spike annealing.
7. the forming method of fin formula field effect transistor according to claim 6, it is characterised in that described
The gas used is made annealing treatment for N2, temperature is 750 degrees Celsius~1300 degrees Celsius.
8. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that remove
The technique of the part semiconductor substrate of the open bottom is anisotropy dry carving technology.
9. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that also wrap
Include：In the side wall formation side wall of the mask layer；With the side while using the mask layer as mask
Wall is mask, and ion implanting is carried out to Semiconductor substrate along the opening, the half of the open bottom
Ion area is formed in conductor substrate；Before the part semiconductor substrate of the open bottom is removed, go
Except the side wall.
10. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that carry out
After the annealing, before the part semiconductor substrate of the open bottom is removed, in addition to：
Remove the mask layer of partial width.
11. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that
The Semiconductor substrate has first area and second area；The opening is included positioned at first area
First is open and is open positioned at second area second；The ion area includes first positioned at first area
Ion area and the second ion area positioned at second area；The fin includes first positioned at first area
Fin and the second fin positioned at second area；The fin ion area includes the positioned at first area
One fin ion area and the second fin ion area positioned at second area；
Using the mask layer as mask, ion implanting is carried out to Semiconductor substrate along the opening, opened described
The step of forming ion area in the Semiconductor substrate of mouth bottom includes：
Form the second barrier layer of covering second opening；
Using second barrier layer and mask layer as mask, first is carried out to Semiconductor substrate along the first opening
Ion implanting, forms the first ion area in the Semiconductor substrate of first open bottom；
Remove behind the second barrier layer, form the first barrier layer of covering first opening；
Using first barrier layer and mask layer as mask, second is carried out to Semiconductor substrate along the second opening
Ion implanting, forms the second ion area in the Semiconductor substrate of second open bottom；
Remove first barrier layer；
After annealing, the first ion area and the second ion area spread to both sides, part the first ion area
Covered with part the second ion area by the mask layer, form the first fin covered by the mask layer
Ion area and the second fin ion area；
Continue using the mask layer as mask, remove the open bottom part semiconductor substrate, form fin
The step of include：
The first open bottom part semiconductor substrate is removed, the first fin is formed in first area；
The second open bottom part semiconductor substrate is removed, in second area the second fin of formation.
12. the forming method of fin formula field effect transistor according to claim 11, it is characterised in that also wrap
Include：
In side wall the first side wall of formation of the mask layer of first area；
Formed after the first side wall, form second barrier layer；
Using first side wall as mask while using second barrier layer and mask layer being mask, along
One opening carries out the first ion implanting to Semiconductor substrate, is served as a contrast in the semiconductor of first open bottom
The first ion area is formed in bottom；
Remove behind second barrier layer, in side wall the second side wall of formation of the mask layer of second area；
Formed after the second side wall, form first barrier layer；
Using second side wall as mask while using first barrier layer and mask layer being mask, along
Two openings carry out the second ion implanting to Semiconductor substrate, are served as a contrast in the semiconductor of second open bottom
The second ion area is formed in bottom；
Before the part semiconductor substrate of first open bottom is removed, the first side wall is removed；Removing
Before the part semiconductor substrate of second open bottom, the second side wall is removed.
13. the forming method of fin formula field effect transistor according to claim 11, it is characterised in that carry out
After the annealing, before the part semiconductor substrate of first open bottom is removed, also
Including：Remove the mask layer of first area partial width；
After carrying out the annealing, before the part semiconductor substrate of second open bottom is removed,
Also include：Remove the mask layer of second area partial width.
14. according to the fin formula field effect transistor of claim 1 to 13 any one formation, it is characterised in that bag
Include：
Semiconductor substrate；
Fin, in the Semiconductor substrate；
Fin ion area, in the fin, and positioned at the side wall of the fin, the fin ion area
The concentration of intermediate ion is successively decreased from fin side wall into fin.
15. fin formula field effect transistor according to claim 14, it is characterised in that the Semiconductor substrate
With first area and second area；The fin includes being located at the first fin of first area and is located at
Second fin of second area；The fin ion area includes the first fin ion positioned at first area
Area and the second fin ion area positioned at second area；The first fin ion area is located at the first fin
In, and positioned at the side wall of the first fin, the concentration of the first fin ion area intermediate ion is by the first fin
Portion side wall successively decreases into the first fin；The second fin ion area is located in the second fin, and is located at
The concentration of ion in the side wall of second fin, the second fin ion area from the second fin side wall to
Successively decrease in second fin.
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