CN107271230B - The preparation method and detection method of test sample - Google Patents
The preparation method and detection method of test sample Download PDFInfo
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- CN107271230B CN107271230B CN201610213349.2A CN201610213349A CN107271230B CN 107271230 B CN107271230 B CN 107271230B CN 201610213349 A CN201610213349 A CN 201610213349A CN 107271230 B CN107271230 B CN 107271230B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
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Abstract
The present invention provides a kind of preparation method of test sample, comprising: provides semiconductor structure, the semiconductor structure includes: the first connector；Positioned at the barrier layer on the first connector surface, less than the diffusion coefficient of the first connector, the atomic density that the atomic density difference between the dielectric layer and the barrier layer is greater than between the first connector and barrier layer is poor for the diffusion coefficient on the barrier layer；Section resolution fault, Formation cross-section film are carried out to the semiconductor structure；Processing is diffused to the section film.By being diffused processing to the section film, biggish first connector of diffusion coefficient is made to diffuse into dielectric layer.In addition, poor positioned at the atomic density that the dielectric layer in second face of section film and the atomic density difference on the barrier layer are greater than between the first connector and barrier layer.Therefore, the clarity of the formed image of barrier layer side wall can be increased after test sample forms image, reduces detection difficulty.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of preparation method of test sample and detection sides
Method.
Background technique
With being constantly progressive for semiconductor technology, the characteristic size of semiconductor devices is gradually become smaller.Features in semiconductor devices
To semiconductor technology, more stringent requirements are proposed for the diminution of size.
In semiconductor technology, damascene process is used for metal interconnecting wires due to the etching for avoiding to metallic copper
In manufacturing process.In order to guarantee the yields of damascene structure, need through transmission electron microscope (Transmission
Electron microscope, TEM) detection point is carried out to the deposition thickness of etch topography in damascene structure and barrier layer
Analysis.
The diminution of semiconductor devices critical size makes semiconductor devices by the influence of RC retardation ratio effect.It is partly led to reduce
The RC retardation ratio effect of body device, medium with low dielectric constant material are used for the dielectric layer of metal interconnecting wires.Meanwhile semiconductor devices
The diminution of critical size reduces the width of metal interconnecting wires also accordingly.However, change and the metal interconnecting wires of dielectric layer material
The diminution of width brings huge challenge to the detection and analysis of semiconductor devices.
The image that the test sample of prior art preparation is formed under the microscope is not clear enough, it is difficult to be detected.
Summary of the invention
Problems solved by the invention is to provide a kind of preparation method of test sample, can reduce sample detection difficulty.
To solve the above problems, the present invention provides a kind of preparation method of test sample, comprising:
Semiconductor structure is provided, the semiconductor structure includes: substrate, is located at intrabasement first connector, the base
Bottom exposes first connector；Dielectric layer on the first connector and substrate；Barrier layer in dielectric layer, institute
State barrier layer and be located at the first connector surface, the diffusion coefficient on the barrier layer less than the first connector diffusion coefficient, it is described
The atomic density that atomic density difference between substrate and the barrier layer is greater than between the first connector and barrier layer is poor；
Section resolution fault, Formation cross-section are carried out to the semiconductor structure along the direction perpendicular to the first connector surface
Film, the section film include the first connector of part, barrier layer, the portion for surrounding barrier layer, encirclement first connector
Point substrate and the certain media layer for surrounding barrier layer, the section film have opposite the first face and the second face, and described the
Barrier layer and the first connector are exposed on one side, and the second face exposes substrate and dielectric layer；
Processing is diffused to the section film.
Optionally, the material for surrounding the part of substrate of the first connector is silica.
Optionally, DIFFUSION TREATMENT makes the material of the first connector is basad or dielectric layer is interior to spread, until exposing substrate
The surface contacted with the first connector.
Optionally, the interconnection structure further includes the second connector positioned at the barrier layer surface.
Optionally, the diffusion coefficient of second connector is greater than the diffusion coefficient on barrier layer.
Optionally, the material of second connector is copper.
Optionally, the method for the DIFFUSION TREATMENT is heat and moisture preserving processing.
Optionally, the step of heat and moisture preserving is handled includes: that the section film is made to be in 20 DEG C~24 DEG C of temperature,
Humidity is 7h~9h in the environment of 40%~50%.
Optionally, the step of heat and moisture preserving is handled includes: that the section film is made to be in 30 DEG C~40 DEG C of temperature,
Humidity is 1.5h~2.5h in the environment of 55%~65%.
Optionally, the material of first connector is copper.
Optionally, the material on the barrier layer is tantalum or tantalum nitride.
Optionally, size of first connector on the direction for being parallel to the first connector and barrier layer contact surface is
90nm~110nm.
Optionally, the technique for carrying out the section resolution fault to the semiconductor structure includes that work is thinned in focused ion beam
Skill.
Optionally, the thickness of the section film is less than 1nm.
Optionally, the material advanced low-k materials or silica of the dielectric layer.
Correspondingly, the present invention also provides a kind of sample detection methods, comprising:
Test sample is formed using the preparation method of above-mentioned test sample；
The test sample is detected by electron lens.
Compared with prior art, technical solution of the present invention has the advantage that
In the preparation method of test sample of the invention, by being diffused processing to the section film, make diffusion system
Biggish first connector of number diffuses into dielectric layer, to reduce the thickness of the first connector in the film of section.In addition, being located at
The dielectric layer in second face of section film and the atomic density difference on the barrier layer are greater than between the first connector and barrier layer
Atomic density it is poor, it is poor so as to increase barrier layer and the scattered light intensity of its surrounding structure.It therefore, can be in test sample
After forming image, increase the luminance difference for the image that barrier layer side wall and its surrounding structure are formed, to increase the barrier layer side
The clarity of the formed image of wall reduces detection difficulty.
In detection method of the invention, the test sample is to be diffused processing by pair cross-section film to be formed.It is logical
It crosses and processing is diffused to the section film, so that biggish first connector of diffusion coefficient is diffused into dielectric layer, to reduce
The thickness of first connector in the film of section.In addition, dielectric layer and the barrier layer positioned at second face of section film
Atomic density difference to be greater than atomic density between the first connector and barrier layer poor, so as to increase barrier layer and its around
The scattered light intensity of structure is poor.Therefore, it can reduce the detection difficulty to the cross-sectional sample.
Detailed description of the invention
Fig. 1 to Fig. 4 is the structural schematic diagram of each step of one embodiment of test sample preparation method of the invention.
Specific embodiment
There are problems for the test sample preparation method of the prior art, such as: the test sample detection difficulty of formation is big.
Now in conjunction with a kind of preparation method of test sample, the big reason of the test sample detection difficulty of formation is analyzed:
In the preparation method of the test sample, for semiconductor structure by section resolution fault, Formation cross-section film is described
Section film is test sample.In one embodiment, the section film includes: section connecting element and barrier layer, surrounds institute
It states the part of substrate of connector and surrounds the certain media layer on barrier layer.By detecting the section film, the company is obtained
The thickness of the shape characteristic and the barrier layer of fitting and the contact surface on the barrier layer.However, in the test sample, resistance
Barrier is contacted with connector, and barrier layer differs smaller with the atomic density of connector, therefore, in the detection process, barrier layer with
The contrast that connector is formed by image is smaller, and therefore, the barrier layer side wall is formed by fogging image, it is difficult to carry out
Detection.
To solve the technical problem, the present invention provides a kind of preparation methods of test sample, comprising: provides semiconductor
Structure, the semiconductor structure include: substrate, are located at intrabasement first connector, and the substrate exposes described first and connects
Fitting；Dielectric layer on the first connector and substrate；Barrier layer in dielectric layer, the barrier layer are located at first and connect
Fitting surface, the diffusion coefficient on the barrier layer less than the first connector diffusion coefficient, the substrate and the barrier layer it
Between atomic density difference to be greater than atomic density between the first connector and barrier layer poor；Along perpendicular to the first connector surface
Direction carries out section resolution fault, Formation cross-section film to the semiconductor structure, and the section film includes that part first connects
Fitting, barrier layer surround barrier layer, surround the part of substrate of first connector and surround the certain media on barrier layer
Layer, the section film have opposite the first face and the second face, and first face exposes barrier layer and the first connector, the
Two faces expose substrate and dielectric layer；Processing is diffused to the section film.
Wherein, by being diffused processing to the section film, diffuse into biggish first connector of diffusion coefficient
Dielectric layer, to reduce the thickness of the first connector in the film of section.In addition, being located at the medium in second face of section film
The atomic density that the atomic density difference on layer and the barrier layer is greater than between the first connector and barrier layer is poor, so as to increase
Barrier layer and the scattered light intensity of its surrounding structure are poor.Therefore, barrier layer side wall can be increased after test sample forms image
The luminance difference of the image formed with its surrounding structure reduces to increase the clarity of the formed image of barrier layer side wall
Detection difficulty.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 4 is the structural schematic diagram of each step of one embodiment of preparation method of test sample of the present invention.
It should be noted that transmission electron microscope (Transmission electron microscope, TEM) has
There is high resolution, the big advantage of amplification factor can be used in observing ultra microstructure, have important answer in technical field of semiconductors
With.In the present embodiment, elaborated for preparing TEM test sample to the preparation method of test sample of the invention.
Transmission electron microscope be it is accelerated and aggregation e-beam projection to very thin sample on, electronics and sample
Atomic collision in product and change direction, to scatter.The size and the density phase of sample that sample acts on electron scattering
It closes.The bigger scattering process to electronics of sample rate is bigger, and the brightness of image of formation is lower, conversely, sample rate is smaller to electricity
The scattering process of son is smaller, and the brightness of image of formation is higher, therefore can form the different image of light and shade.
Referring to FIG. 1, providing semiconductor structure, the semiconductor structure includes: substrate 101, the in substrate 101
A connection piece 111, the substrate 101 expose first connector 111；On the first connector 111 and substrate 101
Dielectric layer 102；Barrier layer 112 in dielectric layer 102, the barrier layer 112 is located at first 111 surfaces of connection, described
The diffusion coefficient on barrier layer 112 less than the first connector 111 diffusion coefficient, between the substrate 101 and the barrier layer 112
Atomic density difference to be greater than atomic density between the first connector 111 and barrier layer 112 poor.
In the present embodiment, some materials that the substrate 101 surrounds first connector 111 are silica.Other
In embodiment, the substrate can also include silicon substrate.
The dielectric layer 102 is for realizing the electrical isolation between different semiconductor devices；The interconnection structure for realizing
Need the electrical connection between interface unit.
In the present embodiment, the material of the dielectric layer 102 is silica.In other embodiments, the material of the dielectric layer
Material can also include: silicon substrate high molecular material for advanced low-k materials.
In this implementation, the material of first connector 111 is copper.Copper has lower resistivity, and good anti-electricity moves
It moves performance.In other embodiments, the material of first connector can also be tungsten.
In the present embodiment, the material on the barrier layer 112 is tantalum.In other embodiments, the material on the barrier layer is also
It can be tantalum nitride.
It should be noted that, if the thickness on the barrier layer 112 is too small, being difficult to reduce the second connection in the present embodiment
Diffusion of the ion to dielectric layer 102 in part 113；If the thickness on the barrier layer 112 is excessive, it is easy to influence the first connector
111 and the second electric conductivity between connector 113.Therefore, it is necessary to the thickness to shown barrier layer 112 to detect, and just need
Reduce the difficulty detected to the barrier layer 112.
It should be noted that the present embodiment is described in detail so that damascene process forms interconnection structure as an example.It is described
Semiconductor structure further includes the second connector 113 on the barrier layer 112.
Second connector 113 is electrically connected for realizing the first connector 111 and external circuit；The barrier layer
112 for reducing diffusion of 112 intermediate ion of the second connector to dielectric layer 102.
It should be noted that the step of forming the semiconductor structure by damascene process includes: to provide substrate 101
With the first connector 111 being located in substrate 101；Second is formed on 101 surface of substrate and 111 surface of the first connector to be situated between
The material bed of material；The second medium material layer is performed etching to first connector 111 is exposed, the first groove is formed；
Barrier layer 112 is formed in first bottom portion of groove and sidewall surfaces；The second connector is formed on 112 surface of barrier layer
113。
In the step of forming the semiconductor structure using damascene process, by dry etching to the second medium
Material layer performs etching, and forms first groove.In other embodiments, it can also be carved by wet etching or dry method wet process
Erosion cooperatively forms first groove.
It should be noted that being easy to cause the first groove during performing etching to the second medium material layer
Side wall is uneven, to be easy to influence the electric conductivity of second connector 113.In addition, the etching process is also easy to make
First connector 111 is etched and is formed and be recessed on 111 surface of the first connector, and the recess is to first connector
111, the electrical property of barrier layer 112 and the second connector 113 is all easy to produce influence.Therefore, in the present embodiment, in reduction pair
While the detection difficulty of 112 thickness of barrier layer, the inspection to 111 surface indentation of etch topography and the first connector is also reduced
Survey difficulty.
In the present embodiment, the material of second connector 112 is copper.Copper has lower resistivity, good anti-electricity
Migrate performance.In other embodiments, the material of second connector can also be tungsten.
Please referring to Fig. 2 to 4, Fig. 2 is top view of the figure one along the direction A；Fig. 4 is the front view of Fig. 3.Connect along perpendicular to first
The direction on fitting 111 (as shown in Figure 3) surface to the semiconductor structure carry out section resolution fault, Formation cross-section film 120,
The section film 120 includes the first connector of part 111, barrier layer 112, surrounds barrier layer 112, surrounds first connection
The part of substrate 101 of part 111 and the certain media layer 102 for surrounding barrier layer 112, the section film 120 have opposite
First face 121 and the second face 122, first face 121 expose barrier layer 112 and the first connector 111, and the second face 122 is sudden and violent
Expose substrate 101 and dielectric layer 102.
In the present embodiment, the semiconductor structure further includes the second connector 113 positioned at 112 surface of barrier layer.
Therefore, in the present embodiment, the section film 120 further include: the second connector 113.
In the present embodiment, the step of section resolution fault includes: sampling, and Formation cross-section thin slice, section thin slice includes opposite
The first primary face and the second primary face；Pit milled processed is carried out to first primary face of section thin slice, in the section
Sheet surface forms pit, and the section sheet thickness of the pit bottom is smaller, is subsequently used for being detected；To the pit bottom
Second primary face of portion or section thin slice carries out reduction processing, Formation cross-section film 120.Wherein, treated first is initial
First face 121 of face Formation cross-section film 120, the second face 122 of treated second primary face Formation cross-section film 120.
In the present embodiment, the step of sampling include: the dotted line 1-1 ' along Fig. 2 direction to the semiconductor structure into
Row dicing treatment, Formation cross-section thin slice.
In the present embodiment, the pit, hand lapping are formed in the section sheet surface by the method for hand lapping
The damage of pair cross-section thin slice is small.
In the present embodiment, by focused ion beam (Focused Ion beam, FIB) thinning technique to the pit bottom
Section thin slice carry out reduction processing, Formation cross-section film 120.Focused ion beam thinning technique is with high-efficient, the time is short
Advantage.
Specifically, the mistake of reduction processing is carried out to the section thin slice of the pit bottom by focused ion beam thinning technique
Cheng Zhong is easy to cause if ion beam voltage is excessive and is formed by the perforation of section film 120；If ion beam voltage is too small, hold
Easily reduce thinned efficiency.Therefore, in the present embodiment, the ion beam voltage is in the range of 0kV~30kV.
In the present embodiment, minimum of the thickness h of the section film 120 between first face 111 and the second face 122
Distance.
In the present embodiment, the thickness of the section film 120 is excessive to be easily reduced the clear of the image formed in detection process
Clear degree；If the thickness of the section film 120 is too small, it is easy to produce hole.Specifically, the thickness h of the section film 120
Less than 1nm.
In other embodiments, ion beam thinning technique can also be cooperated to carry out the section thin slice by hand lapping
Reduction processing, Formation cross-section film 120.Specifically, the voltage of the ion beam is 0kV~5kV.
In the present embodiment, in the section film 120, first connector 111 is being parallel to the first connector 111
It is the width d of first connector 111 with the size on the direction of 112 contact surface of barrier layer.
If the width d of first connector 111 is excessive, it is easy to increase the difficulty of diffusion, if first connection
The width d of part 111 is too small, is easy to increase the difficulty of detection.Specifically, in the present embodiment, the width of first connector 111
D is 90nm~110nm.
Referring to FIG. 4, being diffused processing to the section film 120.
It should be noted that expansion of the diffusion coefficient on the barrier layer 112 less than the first connector 111 (as shown in Figure 3)
Coefficient is dissipated, then during being diffused processing to the section film 120, the diffusion velocity of the atom in barrier layer 112 is small
The diffusion rate of atom in the first connector 111.The decline of atomic density is greater than in barrier layer 112 in first connector 111
The decline of atomic density, therefore, it is bright that the increase that the first connector 111 forms brightness of image is greater than the image that barrier layer 112 is formed
The increase of degree.To which the luminance difference that the first connector 111 forms image and the formation of barrier layer 112 image increases, image definition
Increase.
The DIFFUSION TREATMENT can make the atom in the first connector 111 (as shown in Figure 1) diffuse into the substrate
101, the atomic density of 111 region of the first connector is reduced, to make the first connector 111 to formation figure in detection process
The influence of image brightness reduces, and the detection of 101 pairs of substrate formation of first connector 111 is covered in the section film 120
The influence of brightness of image increases.Connect however, the atomic density difference between the substrate 101 and the barrier layer 112 is greater than first
Atomic density between fitting 111 and barrier layer 112 is poor.Therefore, can increase barrier layer 112 be formed by image and its around
The luminance difference of the formed image of structure.Therefore, the clarity on barrier layer 112 in formed image can be increased, it is difficult to reduce detection
Degree.
In the present embodiment, the test sample is TEM test sample, first connector 111 and the second connector 113
Material be copper；The material on the barrier layer 112 is tantalum；The dielectric layer 102 and the material of substrate 101 are silica.Therefore,
The atomic density on the barrier layer 112 is greater than the atomic density of the first connector 111, and the atom of first connector 111 is close
Degree is greater than the atomic density of substrate 101.
In the present embodiment, barrier layer 112 is greater than the first connector 111 to the scattering process of electronics and makees to the scattering of electronics
With, therefore, barrier layer 112 formed TEM image brightness less than the image that the first connector is formed brightness.At diffusion
Reason reduces the atomic density of the first connector 111, and in the detection process, 111 corresponding position of the first connector is formed
Image be by the first connector 111 and be located at side wall of first connector 111 towards second face 122 (as shown in Figure 3)
The result that the atom pair electronics of the substrate 101 on surface scatters jointly.Substrate 101 is to the scattering process of electronics less than the first connector
The scattering process of 111 pairs of electronics, therefore, the brightness for the image that 111 corresponding position of the first connector is formed increase.It can
Increase the clarity for the image that 112 side wall of barrier layer is formed.
In the present embodiment, the atom of first connector 111 is set to diffuse into the substrate by the DIFFUSION TREATMENT
101, groove 130 is formed, is located on first face 121 (as shown in figure Fig. 3) at the top of the groove 130,130 bottom of groove
Portion exposes 101 surface of substrate, and side wall exposes 112 surface of barrier layer.
Therefore, during carrying out TEM detection to the test sample in the present embodiment, 300 corresponding position of groove
The image of formation is the result that 300 bottom substrate 101 of groove acts on electron scattering.The atomic density of substrate 101 is lower, because
This, the brightness of image of formation is higher, the figure that the side wall so as to increase barrier layer 112 towards 130 side of groove is formed
The clarity of picture.
In addition, the material of second connector 113 is identical as the material of first connector 111 in the present embodiment,
Therefore, during being diffused processing, the atom of second connector 113 can also be spread, to make described
The atomic density of two connectors 113 reduces, and increases the barrier layer 112 towards the clear of the 113 side side wall of the second connector
Clear degree, to reduce the detection difficulty to 112 thickness of barrier layer.
It should be noted that the increase of the formed image definition of 112 side wall of barrier layer can increase etch topography
It is formed by the clarity of image with 111 surface indentation of the first connector, reduces to 111 surface of etch topography and the first connector
The detection difficulty of recess.
In the present embodiment, the method for the DIFFUSION TREATMENT is heat and moisture preserving processing.The heat and moisture preserving processing refers to: making
The section film 120 is in the sufficiently long time in the environment of high temperature and humidity, diffuses into the atom of the first connector 112
In substrate 101.
The diffusion of atom is that frequently transposition, mobile result can occur at high temperature due to atom.Therefore, the expansion of atom
It dissipates related with temperature.Temperature is higher, and atom diffusion rate is bigger, and the time needed is shorter.
Specifically, in the present embodiment, the step of DIFFUSION TREATMENT includes: to make the section film 120 in temperature
20 DEG C~24 DEG C, humidity is 7h~9h in the environment of 40%~50%.In other embodiments, the step of DIFFUSION TREATMENT is gone back
It may include: that the section film 120 is made to be in 30 DEG C~40 DEG C of temperature, 1.5h in the environment of humidity is 55%~65%~
2.5h。
To sum up, in the preparation method of test sample of the invention, by being diffused processing to the section film 120,
Biggish first connector of diffusion coefficient is set to diffuse into dielectric layer, to reduce the thickness of the first connector in section film 120
Degree.It is connect in addition, the dielectric layer and the atomic density difference on the barrier layer positioned at 120 second face of section film are greater than first
Atomic density between part and barrier layer is poor.It is poor so as to increase barrier layer and the scattered light intensity of its surrounding structure.Therefore,
The luminance difference for the image that barrier layer side wall and its surrounding structure are formed can be increased, to increase after test sample forms image
Add the clarity of the formed image of barrier layer side wall, reduces detection difficulty.
Correspondingly, the present invention also provides a kind of detection methods, comprising:
The test sample that the preparation method of test sample described in above-described embodiment is formed is provided；
The test sample is detected by electron lens.
With continued reference to FIG. 4, providing test sample described in above-described embodiment.
In the present embodiment, the test sample is formed by the section film 120 by DIFFUSION TREATMENT.
Specifically, the section film 120 includes: the first connector of part 111 (as shown in Figure 3), resistance in the present embodiment
Barrier 112 surrounds barrier layer 112, surrounds the part of substrate 101 of first connector 111 and surrounds barrier layer 112
Certain media layer 102, the section film 120 have opposite the first face 121 and the second face 122, the exposure of the first face 121
Barrier layer 112 and the first connector 111, the second face 122 expose substrate 101 and dielectric layer 102 out.
In the present embodiment, the section film 120 further includes the second connector 113 positioned at 112 surface of barrier layer.
In the present embodiment, the material of the substrate 101 and dielectric layer 102 is silica.In other embodiments, the base
The material at bottom can also be silicon.
In the present embodiment, the material of first connector 111 and the second connector 113 is copper.In other embodiments,
The material of first connector 111 and the second connector 113 can also be tungsten.
In the present embodiment, the material on the barrier layer 112 is tantalum.In other embodiments, the material on the barrier layer is also
It can be tantalum nitride.
In the present embodiment, the atom of first connector 111 is set to diffuse into the substrate by DIFFUSION TREATMENT
101, groove 130 is formed, on first face 121 (as shown in Figure 3), 130 bottom of groove is sudden and violent at 121 top of groove
Expose 101 surface of substrate, side wall exposes 112 surface of barrier layer.
Therefore, in the present embodiment, the test sample includes: part of substrate 101；Groove in the substrate 101
130；Second connector 113, barrier layer 112, the dielectric layer 102 for surrounding barrier layer 112 and second connector 113.
With continued reference to Fig. 4, the test sample is detected by electron lens.
In the present embodiment, pass through transmission electron microscope (Transmission electron microscope, TEM)
The test sample is observed.Detect the thickness and first connector on the middle barrier layer 112 of the section film 120
The etch topography and recess on 111 surfaces.
Transmission electron microscope (Transmission electron microscope, TEM) has high resolution, puts
The big advantage of big multiple can be used in observing ultra microstructure, have important application in technical field of semiconductors.
Transmission electron microscope be it is accelerated and aggregation e-beam projection to very thin sample on, electronics and sample
Atomic collision in product and change direction, to scatter.The size and the density phase of sample that sample acts on electron scattering
It closes.The bigger scattering process to electronics of sample rate is bigger, and the brightness of image of formation is lower, conversely, sample rate is smaller to electricity
The scattering process of son is smaller, and the brightness of image of formation is higher, therefore can form the different image of light and shade.
The scattering of electronics is made it should be noted that barrier layer 112 is greater than the first connector 111 to the scattering process of electronics
With, therefore, barrier layer 112 formed TEM image brightness less than the image that the first connector is formed brightness.In detection process
In, the image that 111 corresponding position of the first connector by DIFFUSION TREATMENT is formed is by the first connector 111 and to be located at
The result that the atom pair electronics of first connector 111 towards the substrate 101 of the sidewall surfaces in second face 122 scatters jointly.
Scattering process of the substrate 101 to the scattering process of electronics less than the first connector 111 to electronics.Therefore, first connector
111 corresponding positions formed image brightness increase, so as to increase by 112 side wall of barrier layer formation image it is clear
Degree.
In the present embodiment, the test sample is that first connector 111 is made to diffuse into 101 shape of substrate completely
At.Therefore, the image that 130 corresponding position of groove is formed is to be dissipated by 130 bottom substrate 101 of groove to electronics
What the effect of penetrating was formed.The substrate 101 and the density contrast on barrier layer 112 are larger, therefore, to the scattering process of electronics difference compared with
Greatly, the picture contrast of formation is larger.Therefore, the image of formation is apparent, can reduce the thickness to barrier layer 112 and blocking
The layer etch topography on 112 surfaces and the detection difficulty of recess.
To sum up, in detection method of the invention, the test sample is to be diffused processing by pair cross-section film to be formed
's.By being diffused processing to the section film, biggish first connector of diffusion coefficient is made to diffuse into dielectric layer, thus
Reduce the thickness of the first connector in the film of section.In addition, dielectric layer and the resistance positioned at second face of section film
The atomic density that the atomic density difference of barrier is greater than between the first connector and barrier layer is poor.So as to increase barrier layer and its
The scattered light intensity of surrounding structure is poor.Therefore, it can reduce the detection difficulty to the cross-sectional sample.
Claims (15)
1. a kind of preparation method of test sample characterized by comprising
Semiconductor structure is provided, the semiconductor structure includes: substrate, is located at intrabasement first connector, and the substrate is sudden and violent
Expose first connector；Dielectric layer on the first connector and substrate；Barrier layer in dielectric layer, the resistance
Barrier is located at the first connector surface, the diffusion coefficient of the diffusion coefficient less than the first connector on the barrier layer, the substrate
The atomic density that atomic density difference between the barrier layer is greater than between the first connector and barrier layer is poor；
Section resolution fault is carried out to the semiconductor structure along the direction perpendicular to the first connector surface, Formation cross-section is thin
Film, the section film include the first connector of part, partial barrier, the part of substrate for surrounding first connector, with
And the certain media layer on barrier layer is surrounded, the section film has opposite the first face and the second face, the first face exposure
Barrier layer and the first connector, the second face expose substrate and dielectric layer out, the dielectric layer positioned at second face of section film
The atomic density being greater than between the first connector and barrier layer with the atomic density difference on the barrier layer is poor；
Processing is diffused to the section film.
2. the preparation method of test sample as described in claim 1, which is characterized in that surround the part of substrate of the first connector
Material be silica.
3. the preparation method of test sample as described in claim 1, which is characterized in that DIFFUSION TREATMENT makes the material of the first connector
Diffusion in basad or dielectric layer is expected, until exposing the surface that substrate is contacted with the first connector.
4. the preparation method of test sample as described in claim 1, which is characterized in that the semiconductor structure further includes being located at
Second connector of the barrier layer surface.
5. the preparation method of test sample as claimed in claim 4, which is characterized in that the diffusion coefficient of second connector
Greater than the diffusion coefficient on barrier layer.
6. the preparation method of test sample as claimed in claim 4, which is characterized in that the material of second connector is
Copper.
7. the preparation method of test sample as described in claim 1, which is characterized in that the method for the DIFFUSION TREATMENT is heat preservation
Moisturizing processing.
8. the preparation method of test sample as claimed in claim 7, which is characterized in that the step of heat and moisture preserving is handled is wrapped
It includes: so that the section film is in 20 DEG C~24 DEG C of temperature, humidity is 7h~9h in the environment of 40%~50%.
9. the preparation method of test sample as claimed in claim 7, which is characterized in that the step of heat and moisture preserving is handled is wrapped
It includes: so that the section film is in 30 DEG C~40 DEG C of temperature, humidity is 1.5h~2.5h in the environment of 55%~65%.
10. the preparation method of test sample as described in claim 1, which is characterized in that the material of first connector is
Copper.
11. the preparation method of test sample as described in claim 1, which is characterized in that the material on the barrier layer be tantalum or
Tantalum nitride.
12. the preparation method of test sample as described in claim 1, which is characterized in that first connector is being parallel to
Size on the direction of first connector and barrier layer contact surface is 90nm~110nm.
13. the preparation method of test sample as described in claim 1, which is characterized in that carry out institute to the semiconductor structure
The technique for stating section resolution fault includes focused ion beam reduction process.
14. the preparation method of test sample as described in claim 1, which is characterized in that the thickness of the section film is less than
1nm。
15. the preparation method of test sample as described in claim 1, which is characterized in that the material of the dielectric layer is low Jie
Permittivity material or silica.
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| CN102412191A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Transmission electron microscopy sample preparation method capable of detecting Damascus seed crystal layer and barrier layer |
| CN104075918A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院金属研究所 | Method for preparing micro intercommunicated hole structure transmission electron microscope sample |
| CN104614216B (en) * | 2015-02-06 | 2017-06-23 | 武汉新芯集成电路制造有限公司 | The quick sample preparation methods for obtaining barrier layer pattern |
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| US6876021B2 (en) * | 2002-11-25 | 2005-04-05 | Texas Instruments Incorporated | Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier |
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| CN102412191A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Transmission electron microscopy sample preparation method capable of detecting Damascus seed crystal layer and barrier layer |
| CN104075918A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院金属研究所 | Method for preparing micro intercommunicated hole structure transmission electron microscope sample |
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