CN107241076B - Power amplifier amplitude limiter - Google Patents
Power amplifier amplitude limiter Download PDFInfo
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- CN107241076B CN107241076B CN201710421187.6A CN201710421187A CN107241076B CN 107241076 B CN107241076 B CN 107241076B CN 201710421187 A CN201710421187 A CN 201710421187A CN 107241076 B CN107241076 B CN 107241076B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
- H03G11/02—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general by means of diodes
Abstract
The invention discloses a power amplifier amplitude limiter, which comprises an amplification amplitude limiting unit and an overdrive protection unit; the amplification and amplitude limiting unit comprises a filter, an amplification and amplitude limiting circuit and the like, the overdrive protection unit comprises a PNP triode, a four-channel PIN diode attenuator and the like, signals enter the amplification and amplitude limiting unit through a connector X1 and then are output through a connector X2, a connector X2 is connected with a connector X3, and the signals enter the overdrive protection unit through a connector X3 and are output through a connector X4. The amplitude limiter of the invention is connected with the overdrive protection device after the amplitude limiting unit is amplified, thus preventing the input signal from being overlarge and the instant overshoot of the pulse signal and achieving the effect of amplitude limiting.
Description
Technical Field
The invention relates to the field of amplitude limiters, in particular to an amplitude limiter of a power amplifier.
Background
Due to the development of science and technology, people continuously and deeply research basic physics, light sources and superconductivity, and along with the wide application of all-solid-state power amplifiers in the high-power fields of electron accelerators, laser sources and the like, the power grade of the solid-state power amplifier is continuously improved. According to the special application of the solid-state power amplifier, the use reliability of the solid-state power amplifier and the stability of output power are improved. A power amplifier amplitude limiter is required to be added between the input of the high-power solid-state power amplifier and the output of the continuous wave signal and the pulse signal to limit the output amplitude of the continuous wave signal and the pulse signal, so that the output signal amplitude is kept stable.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to limit the output amplitude of a continuous wave signal so as to keep the output signal amplitude stable, and provides a power amplifier amplitude limiter.
In order to achieve the purpose, the technical scheme of the invention is as follows: a power amplifier amplitude limiter comprises an amplification amplitude limiting unit and an overdrive protection unit;
the signal of the amplification and amplitude limiting unit is accessed by a connector X1, a connector X1 is connected with the input end of a resistor R2, two ends of the resistor R2 are respectively connected with the rear ground wire through a resistor R1 and a resistor R3, the output end of the resistor R2 is connected with the input end of a capacitor C1, the output end of a capacitor C1 is connected with the input end of a filter V1, the rear end of the filter V1 is sequentially connected with a capacitor C2 and a capacitor C3, the output end of the capacitor C3 is connected with the input end of a filter V2, the output end of the filter V2 is connected with the input end of a capacitor C4, and the output end of the; the input end of the resistor R4 is connected with the anode of a 12V power supply, the front and the back of the resistor R4 are respectively provided with a grounding capacitor C5 and a grounding capacitor C6, and the output end of the resistor R4 is respectively connected with a first amplification amplitude limiting circuit and a second amplification amplitude limiting circuit; the output end of the first amplification amplitude limiting circuit is connected with the input end of the capacitor C2, and the output end of the second amplification amplitude limiting circuit is connected with the input end of the capacitor C4;
the first amplification amplitude limiting circuit comprises a low-voltage-difference linear regulator V3 ", an input port Vi of a low-voltage-difference linear regulator V3" is connected with an input end of a resistor R4, a grounded capacitor C7, a grounded capacitor C8 and a grounded capacitor C9 are respectively arranged between the input port Vi and a resistor R4, an output port Vo of the low-voltage-difference linear regulator V3 "is connected with an input end of a resistor R5, a grounded port VGND of the low-voltage-difference linear regulator V3" is connected with an input end of an adjustable grounded resistor R6, the output port Vo and the grounded port VGND are connected through a resistor R7, an output end of the resistor R5 is connected with an input end of an inductor L, an output end of the resistor R5 is further connected with a grounded capacitor C10, a grounded capacitor C11 and a grounded capacitor C12, and an;
the second amplification amplitude limiting circuit has the same structure as the first amplification amplitude limiting circuit, and comprises a low-dropout linear regulator V3 ', a resistor R4 ', a grounding capacitor C7 ', a grounding capacitor C8 ', a grounding capacitor C9 ', a resistor R5 ', an adjustable grounding resistor R6 ', a resistor R7 ', an inductor L1 ', a grounding capacitor C10 ', a grounding capacitor C11 ', a grounding capacitor C12 ', and the output end of the inductor L1 ' is connected to the input end of the capacitor C4;
in the overdrive protection unit, a connector X3 is sequentially connected with a resistor R3 and a capacitor C3, the connector X3 is connected with the capacitor C3, a ground resistor R3 and a ground resistor R3 are respectively arranged at the front and the rear of the resistor R3, the capacitor C3 and the capacitor C3 are respectively connected with an input/output PIN V3-1 and a V3-3 of a four-channel PIN diode attenuator V3, a bias PIN V3-2 of the four-channel PIN diode attenuator V3 is sequentially connected with the resistor R3, the ground capacitor C3 and the resistor R3 and then connected with a collector C of a PNP triode V3, a shunt bias PIN V3-4 and a ground capacitor C3-5 of the four-channel PIN diode attenuator V3 are sequentially connected with the ground capacitor C3 and the resistor R3, the tail ends of the two resistors R3 are simultaneously connected with one end of the ground capacitor C3, and one end of the two ends of the two resistors R3 are simultaneously connected with one end of the ground capacitor C, One end of a grounding resistor R22 and the other end of the resistor R21 are respectively connected with an external grounding capacitor C21 and a 12V power supply;
an emitter E of the PNP triode V4 is connected to a 12V power supply through an adjustable resistor R15, a base B of the PNP triode V4 is connected with the emitter E through a resistor R16, a base B of the PNP triode V4 is also connected with one end of a resistor R17, the other end of the resistor R17 is connected to a collector C ' of the NPN triode V5, an emitter E ' of the NPN triode V5 is grounded, a base B ' of the NPN triode V5 is respectively connected with a resistor R18, a grounded capacitor C17 and a grounded resistor R19, the tail end of the resistor R18 is respectively connected with a grounded capacitor C18 and the cathode of the Schottky diode V6, the anode of the Schottky diode V6 is connected with the anode of another Schottky diode V7, and the cathode of the Schottky diode V7 is connected with;
the connector X3 is further connected with one end of a resistor R23, the other end of the resistor R23 is connected with a ground resistor R24, a ground resistor R25 and a capacitor C22 respectively, the tail end of the capacitor C22 is connected with an RFIN pin of a detector N1, an SREF pin, a PWON pin and a COMM pin of the detector N1 are grounded respectively, a VPOS pin is connected with an IREF pin and is connected with an F L TR pin through the capacitor C23, the VPOS pin and the IREF pin are connected with two ground capacitors C24 simultaneously and are connected with a 5V power supply, and are connected with a 12V power supply through a resistor R26 simultaneously, two ends of the resistor R26 are provided with a ground capacitor C25 respectively, the VPOS pin and the IREF pin are connected with the cathode of a voltage stabilizing diode V8 simultaneously, and the anode of the;
the VRMS pin of the detector N1 is connected to the anode of a diac V9 and is simultaneously connected with a test port TP1, the other anode of the diac V9 is grounded, and the cathode of the diac V9 is respectively connected with a ground resistor R27, a ground capacitor C26 and a test port TP2 and is connected to the non-inverting input end of an amplifier A1;
the inverting input end of the amplifier A1 is connected with the output end of the amplifier A1 through a resistor R29, two ends of the resistor R29 are respectively provided with a grounding resistor R28, the output end of the amplifier A1 is connected with one end of a test port TP3 and one end of a resistor R30, the other end of the resistor R30 is connected with a grounding resistor R31, the other end of the resistor R30 is simultaneously connected with the non-inverting input end of the amplifier A2, the inverting input end of the amplifier A2 is connected with one end of a resistor R32, the other end of the resistor R32 is connected with the middle end of an adjustable resistor R33, one end of the adjustable resistor R33 is connected with a 12V power supply through a resistor R34; the output end of the amplifier A2 is respectively connected with a test port TP4 and a resistor R36, the tail end of the resistor R36 is connected with one end of a six-phase inverting buffer A3, and the other end of the six-phase inverting buffer A3 is respectively connected with a grounding capacitor C27 and pins A4-S0 of a trigger A4;
A4-R0 pins of the trigger A4 are connected with an A4-R1 pin, an A4-R2 pin, an A4-R3 pin and an A4-EN pin in series and then are respectively connected to one end of a resistor R37, the anode of a diode V10, a connector X7 and a source S of a field effect transistor V11, a 12V power supply is connected to the cathode of the diode V10 through a resistor R38, a six-phase inverted buffer A5 and a six-phase inverted buffer A6 in sequence, and the other end of the resistor R37 is connected to the 12V power supply; the pin A4-Q0 of the trigger A4 is connected with one end of a buffer A7, the other end of the buffer A7 is respectively connected with one end of a resistor R39, one end of a resistor R40 and the anode of a Schottky diode V6, and the other end of the resistor R40 is connected with a resistor R41 in series and then is connected with a connector X6;
the drain S of the field effect transistor V11 is grounded, the grid G is respectively connected with one end of a resistor R42 and a grounding resistor R43, and the other end of the resistor R42 is connected with a connector X8;
after entering the amplification and amplitude limiting unit through the connector X1, the signal is output through the connector X2, the connector X2 is connected with the connector X3, and the signal enters the overdrive protection unit through the connector X3 and is output through the connector X4.
The invention has the beneficial effects that: the amplitude limiter of the invention is connected with the overdrive protection device after the amplitude limiting unit is amplified, thus preventing the input signal from being overlarge and the instant overshoot of the pulse signal and achieving the effect of amplitude limiting.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a circuit diagram of an amplifying and amplitude limiting unit according to the present invention;
fig. 3 is a circuit diagram of an overdrive protection unit according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
As shown in fig. 1, 2 and 3, the power amplifier limiter of the present invention includes an amplification limiting unit and an overdrive protection unit;
the signal of the amplification and amplitude limiting unit is accessed by a connector X1, a connector X1 is connected with the input end of a resistor R2, two ends of the resistor R2 are respectively connected with the rear ground wire through a resistor R1 and a resistor R3, the output end of the resistor R2 is connected with the input end of a capacitor C1, the output end of a capacitor C1 is connected with the input end of a filter V1, the rear end of the filter V1 is sequentially connected with a capacitor C2 and a capacitor C3, the output end of the capacitor C3 is connected with the input end of a filter V2, the output end of the filter V2 is connected with the input end of a capacitor C4, and the output end of the; the input end of the resistor R4 is connected with the anode of a 12V power supply, the front and the back of the resistor R4 are respectively provided with a grounding capacitor C5 and a grounding capacitor C6, and the output end of the resistor R4 is respectively connected with a first amplification amplitude limiting circuit and a second amplification amplitude limiting circuit; the output end of the first amplification amplitude limiting circuit is connected with the input end of the capacitor C2, and the output end of the second amplification amplitude limiting circuit is connected with the input end of the capacitor C4;
the first amplification amplitude limiting circuit comprises a low-voltage-difference linear regulator V3 ", an input port Vi of a low-voltage-difference linear regulator V3" is connected with an input end of a resistor R4, a grounded capacitor C7, a grounded capacitor C8 and a grounded capacitor C9 are respectively arranged between the input port Vi and a resistor R4, an output port Vo of the low-voltage-difference linear regulator V3 "is connected with an input end of a resistor R5, a grounded port VGND of the low-voltage-difference linear regulator V3" is connected with an input end of an adjustable grounded resistor R6, the output port Vo and the grounded port VGND are connected through a resistor R7, an output end of the resistor R5 is connected with an input end of an inductor L, an output end of the resistor R5 is further connected with a grounded capacitor C10, a grounded capacitor C11 and a grounded capacitor C12, and an;
the second amplification amplitude limiting circuit has the same structure as the first amplification amplitude limiting circuit, and comprises a low-dropout linear regulator V3 ', a resistor R4 ', a grounding capacitor C7 ', a grounding capacitor C8 ', a grounding capacitor C9 ', a resistor R5 ', an adjustable grounding resistor R6 ', a resistor R7 ', an inductor L1 ', a grounding capacitor C10 ', a grounding capacitor C11 ', a grounding capacitor C12 ', and the output end of the inductor L1 ' is connected to the input end of the capacitor C4;
in the overdrive protection unit, a connector X3 is sequentially connected with a resistor R3 and a capacitor C3, the connector X3 is connected with the capacitor C3, a ground resistor R3 and a ground resistor R3 are respectively arranged at the front and the rear of the resistor R3, the capacitor C3 and the capacitor C3 are respectively connected with an input/output PIN V3-1 and a V3-3 of a four-channel PIN diode attenuator V3, a bias PIN V3-2 of the four-channel PIN diode attenuator V3 is sequentially connected with the resistor R3, the ground capacitor C3 and the resistor R3 and then connected with a collector C of a PNP triode V3, a shunt bias PIN V3-4 and a ground capacitor C3-5 of the four-channel PIN diode attenuator V3 are sequentially connected with the ground capacitor C3 and the resistor R3, the tail ends of the two resistors R3 are simultaneously connected with one end of the ground capacitor C3, and one end of the two ends of the two resistors R3 are simultaneously connected with one end of the ground capacitor C, One end of a grounding resistor R22 and the other end of the resistor R21 are respectively connected with an external grounding capacitor C21 and a 12V power supply;
an emitter E of the PNP triode V4 is connected to a 12V power supply through an adjustable resistor R15, a base B of the PNP triode V4 is connected with the emitter E through a resistor R16, a base B of the PNP triode V4 is also connected with one end of a resistor R17, the other end of the resistor R17 is connected to a collector C ' of the NPN triode V5, an emitter E ' of the NPN triode V5 is grounded, a base B ' of the NPN triode V5 is respectively connected with a resistor R18, a grounded capacitor C17 and a grounded resistor R19, the tail end of the resistor R18 is respectively connected with a grounded capacitor C18 and the cathode of the Schottky diode V6, the anode of the Schottky diode V6 is connected with the anode of another Schottky diode V7, and the cathode of the Schottky diode V7 is connected with;
the connector X3 is further connected with one end of a resistor R23, the other end of the resistor R23 is connected with a ground resistor R24, a ground resistor R25 and a capacitor C22 respectively, the tail end of the capacitor C22 is connected with an RFIN pin of a detector N1, an SREF pin, a PWON pin and a COMM pin of the detector N1 are grounded respectively, a VPOS pin is connected with an IREF pin and is connected with an F L TR pin through the capacitor C23, the VPOS pin and the IREF pin are connected with two ground capacitors C24 simultaneously and are connected with a 5V power supply, and are connected with a 12V power supply through a resistor R26 simultaneously, two ends of the resistor R26 are provided with a ground capacitor C25 respectively, the VPOS pin and the IREF pin are connected with the cathode of a voltage stabilizing diode V8 simultaneously, and the anode of the;
the VRMS pin of the detector N1 is connected to the anode of a diac V9 and is simultaneously connected with a test port TP1, the other anode of the diac V9 is grounded, and the cathode of the diac V9 is respectively connected with a ground resistor R27, a ground capacitor C26 and a test port TP2 and is connected to the non-inverting input end of an amplifier A1;
the inverting input end of the amplifier A1 is connected with the output end of the amplifier A1 through a resistor R29, two ends of the resistor R29 are respectively provided with a grounding resistor R28, the output end of the amplifier A1 is connected with one end of a test port TP3 and one end of a resistor R30, the other end of the resistor R30 is connected with a grounding resistor R31, the other end of the resistor R30 is simultaneously connected with the non-inverting input end of the amplifier A2, the inverting input end of the amplifier A2 is connected with one end of a resistor R32, the other end of the resistor R32 is connected with the middle end of an adjustable resistor R33, one end of the adjustable resistor R33 is connected with a 12V power supply through a resistor R34; the output end of the amplifier A2 is respectively connected with a test port TP4 and a resistor R36, the tail end of the resistor R36 is connected with one end of a six-phase inverting buffer A3, and the other end of the six-phase inverting buffer A3 is respectively connected with a grounding capacitor C27 and pins A4-S0 of a trigger A4;
A4-R0 pins of the trigger A4 are connected with an A4-R1 pin, an A4-R2 pin, an A4-R3 pin and an A4-EN pin in series and then are respectively connected to one end of a resistor R37, the anode of a diode V10, a connector X7 and a source S of a field effect transistor V11, a 12V power supply is connected to the cathode of the diode V10 through a resistor R38, a six-phase inverted buffer A5 and a six-phase inverted buffer A6 in sequence, and the other end of the resistor R37 is connected to the 12V power supply; the pin A4-Q0 of the trigger A4 is connected with one end of a buffer A7, the other end of the buffer A7 is respectively connected with one end of a resistor R39, one end of a resistor R40 and the anode of a Schottky diode V6, and the other end of the resistor R40 is connected with a resistor R41 in series and then is connected with a connector X6;
the drain S of the field effect transistor V11 is grounded, the grid G is respectively connected with one end of a resistor R42 and a grounding resistor R43, and the other end of the resistor R42 is connected with a connector X8;
after entering the amplification and amplitude limiting unit through the connector X1, the signal is output through the connector X2, the connector X2 is connected with the connector X3, and the signal enters the overdrive protection unit through the connector X3 and is output through the connector X4.
The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Claims (1)
1. A power amplifier amplitude limiter is characterized by comprising an amplification amplitude limiting unit and an overdrive protection unit;
the signal of the amplification and amplitude limiting unit is accessed by a connector X1, a connector X1 is connected with the input end of a resistor R2, two ends of the resistor R2 are respectively connected with the rear ground wire through a resistor R1 and a resistor R3, the output end of the resistor R2 is connected with the input end of a capacitor C1, the output end of a capacitor C1 is connected with the input end of a filter V1, the rear end of the filter V1 is sequentially connected with a capacitor C2 and a capacitor C3, the output end of the capacitor C3 is connected with the input end of a filter V2, the output end of the filter V2 is connected with the input end of a capacitor C4, and the output end of the; the input end of the resistor R4 is connected with the anode of a 12V power supply, the front and the back of the resistor R4 are respectively provided with a grounding capacitor C5 and a grounding capacitor C6, and the output end of the resistor R4 is respectively connected with a first amplification amplitude limiting circuit and a second amplification amplitude limiting circuit; the output end of the first amplification amplitude limiting circuit is connected with the input end of the capacitor C2, and the output end of the second amplification amplitude limiting circuit is connected with the input end of the capacitor C4;
the first amplification amplitude limiting circuit comprises a low-voltage-difference linear regulator V3 ", an input port Vi of a low-voltage-difference linear regulator V3" is connected with an output end of a resistor R4, a grounded capacitor C7, a grounded capacitor C8 and a grounded capacitor C9 are respectively arranged between the input port Vi and a resistor R4, an output port Vo of the low-voltage-difference linear regulator V3 "is connected with an input end of a resistor R5, a grounded port VGND of the low-voltage-difference linear regulator V3" is connected with an input end of an adjustable grounded resistor R6, the output port Vo and the grounded port VGND are connected through a resistor R7, an output end of the resistor R5 is connected with an input end of an inductor L, an output end of the resistor R5 is further connected with a grounded capacitor C10, a grounded capacitor C11 and a grounded capacitor C12, and an;
the second amplification amplitude limiting circuit has the same structure as the first amplification amplitude limiting circuit, and comprises a low-dropout linear regulator V3 ', a resistor R4 ', a grounding capacitor C7 ', a grounding capacitor C8 ', a grounding capacitor C9 ', a resistor R5 ', an adjustable grounding resistor R6 ', a resistor R7 ', an inductor L1 ', a grounding capacitor C10 ', a grounding capacitor C11 ', a grounding capacitor C12 ', and the output end of the inductor L1 ' is connected to the input end of the capacitor C4;
in the overdrive protection unit, a connector X3 is sequentially connected with a resistor R3 and a capacitor C3, the connector X3 is connected with the capacitor C3, a ground resistor R3 and a ground resistor R3 are respectively arranged at the front and the rear of the resistor R3, the capacitor C3 and the capacitor C3 are respectively connected with an input/output PIN V3-1 and a V3-3 of a four-channel PIN diode attenuator V3, a bias PIN V3-2 of the four-channel PIN diode attenuator V3 is sequentially connected with the resistor R3, the ground capacitor C3, a collector C of a PNP triode V3, a shunt bias PIN V3-4 and a ground capacitor C3-5 of the four-channel PIN diode attenuator V3 are sequentially connected with the ground capacitor C3 and one end of the resistor R3, the other end of the two resistors R3 is simultaneously connected with one end of the ground capacitor C3, and the tail end of the two resistors C3 of the two resistors are simultaneously connected with one end of the ground capacitor C3, One end of a grounding resistor R22 and the other end of the resistor R21 are sequentially connected with an external grounding capacitor C21 and a 12V power supply;
an emitter E of the PNP triode V4 is connected to a 12V power supply through an adjustable resistor R15, a base B of the PNP triode V4 is connected with the emitter E through a resistor R16, a base B of the PNP triode V4 is also connected with one end of a resistor R17, the other end of the resistor R17 is connected to a collector C ' of the NPN triode V5, an emitter E ' of the NPN triode V5 is grounded, a base B ' of the NPN triode V5 is respectively connected with one end of a resistor R18, a grounded capacitor C17 and a grounded resistor R19, the other end of the resistor R18 is respectively connected with a grounded capacitor C18 and the negative electrode of the Schottky diode V6, the positive electrode of the Schottky diode V6 is connected with the positive electrode of another Schottky diode V7, and the negative electrode of the Schottky diode V;
the connector X3 is further connected with one end of a resistor R23, the other end of the resistor R23 is connected with one ends of a ground resistor R24, a ground resistor R25 and a capacitor C22 respectively, the other end of the capacitor C22 is connected with an RFIN pin of a detector N1, an SREF pin, a PWON pin and a COMM pin of the detector N1 are grounded respectively, a VPOS pin is connected with the IREF pin and connected with an F L TR pin through the capacitor C23, the VPOS pin and the IREF pin are connected with two ground capacitors C24 at the same time and connected with a 5V power supply, and are connected with a 12V power supply through a resistor R26, two ends of the resistor R26 are provided with ground capacitors C25 respectively, the VPOS pin and the IREF pin are connected with the cathode of a voltage stabilizing diode V8 at the same time, and the;
the VRMS pin of the detector N1 is connected to the anode of a diac V9 and is simultaneously connected with a test port TP1, the other anode of the diac V9 is grounded, and the cathode of the diac V9 is respectively connected with a ground resistor R27, a ground capacitor C26 and a test port TP2 and is connected to the non-inverting input end of an amplifier A1;
the inverting input end of the amplifier A1 is connected with the output end of the amplifier A1 through a resistor R29, two ends of the resistor R29 are respectively provided with a grounding resistor R28, the output end of the amplifier A1 is connected with one end of a test port TP3 and one end of a resistor R30, the other end of the resistor R30 is connected with a grounding resistor R31, the other end of the resistor R30 is simultaneously connected with the non-inverting input end of the amplifier A2, the inverting input end of the amplifier A2 is connected with one end of a resistor R32, the other end of the resistor R32 is connected with the middle end of an adjustable resistor R33, one end of the adjustable resistor R33 is connected with a 12V power supply through a resistor R34; the output end of the amplifier A2 is respectively connected with one end of a test port TP4 and one end of a resistor R36, the other end of the resistor R36 is connected with one end of a six-phase inverting buffer A3, and the other end of the six-phase inverting buffer A3 is respectively connected with a grounding capacitor C27 and pins A4-S0 of a trigger A4;
A4-R0 pins of the trigger A4 are connected with an A4-R1 pin, an A4-R2 pin, an A4-R3 pin and an A4-EN pin in series and then are respectively connected to one end of a resistor R37, the anode of a diode V10, a connector X7 and a source S of a field effect transistor V11, a 12V power supply is connected to the cathode of the diode V10 through a resistor R38, a six-phase inverted buffer A5 and a six-phase inverted buffer A6 in sequence, and the other end of the resistor R37 is connected to the 12V power supply; the pin A4-Q0 of the trigger A4 is connected with one end of a buffer A7, the other end of the buffer A7 is respectively connected with one end of a resistor R39, one end of a resistor R40 and the anode of a Schottky diode V6, and the other end of the resistor R40 is connected with a resistor R41 in series and then is connected with a connector X6;
the drain D of the field effect transistor V11 is grounded, the grid G is respectively connected with one end of a resistor R42 and a grounding resistor R43, and the other end of the resistor R42 is connected with a connector X8;
after entering the amplification and amplitude limiting unit through the connector X1, the signal is output through the connector X2, the connector X2 is connected with the connector X3, and the signal enters the overdrive protection unit through the connector X3 and is output through the connector X4.
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| CN107241076A (en) | 2017-10-10 |
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