CN1072393C - 球阵式集成电路封装方法 - Google Patents

球阵式集成电路封装方法 Download PDF

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Publication number
CN1072393C
CN1072393C CN97100004A CN97100004A CN1072393C CN 1072393 C CN1072393 C CN 1072393C CN 97100004 A CN97100004 A CN 97100004A CN 97100004 A CN97100004 A CN 97100004A CN 1072393 C CN1072393 C CN 1072393C
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circuit
array type
bead array
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integrated circuit
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CN1190252A (zh
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林定皓
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HUATONG COMPUTER CO Ltd
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HUATONG COMPUTER CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种球阵式集成电路封装方法，主要是在薄铜片上经覆干膜与电镀形成朝上表面外突的导线及金属凸点，其次，则于该形成导线及金属凸点的表面依序经植入晶片、连线、灌胶的步骤后，再将前述位于底层的薄铜片去除，以使所述导线线路及金属凸点外露，再经覆盖绿漆、焊接踢球与蚀刻去除位于相邻晶片间的导线后，即可使晶片分离而呈相互独立的球阵式集成电路包装。

Description

球阵式集成电路封装方法
本发明涉及一种球阵式集成电路封装方法，是一种无需使用基板的球阵式(BGA)集成电路的封装方法，以使外包装更趋小巧。
为达到符合不同场合的需要，现今集成电路的外包装有各式不同的外包装形式，诸如DIP、PGA、BGA、TAB……等型式，而以球阵式(BGA)(BALL GRID ARRAY)集成电路的外包装而论，其是在集成电路外包装的底面形成纵横排列的多数锡球接点，而供热熔焊接于电路板相应的接点上，但是在此种包装形式，由于制程期间需适当支撑以及供做为锡球与晶片的介质之下，一般均需以电路板做为「支撑基板」，在加入基板的封装中，即导致外包装尺寸厚度增加，此举，在包装尺寸要求较为严格的笔记型或次笔记型电脑上使用时，即有过于占用空间的问题存在，故有再予改进的必要。
本发明的主要目的在于提供一种无基板的球阵式集成电路外包装方法，以省略基板而使得外包装更趋轻薄短小。
为达到上述目的，本发明采取如下技术方案：
本发明的球阵式集成电路封装方法，包括以下步骤：
a．在铜片上覆干膜与电镀形成线路；
b．对所述线路进行植入晶片；
c．对所述晶片与线路之间进行连线；
d．灌胶覆盖所述晶片；
e．蚀刻去除所述铜片，使所述线路外露；
f．对应于线路的接点位置植入锡球；
g．蚀刻去除位于相邻晶片间的多余线路，以形成个别独立的晶片封装。
所述的球阵式集成电路封装方法，其特征在于：还包括涂布绿漆的步骤，在所述植入锡球的步骤完成后，进行涂布绿漆的步骤，以保护线路部份。
所述的球阵式集成电路封装方法，其特征在于：所述电镀形成的线路为外突的形式。
所述的球阵式集成电路封装方法，其特征在于：还包括一个涂布绿漆的步骤，在所述蚀刻去除多余线路的步骤后，再进行涂布绿漆的步骤。
本发明的球阵式集成电路封装方法与传统封装方式相比，具有如下效果：
本发明的封装方法仅形成有线路及电镀凸点30，可使外包装更趋轻盈小巧，且对缩小封装厚度有着积极的帮助，故为一具新颖性及进步性的球阵式集成电路封装方法。
以下结合附图及实施例进一步说明本发明的具体结构特征及目的。
附图简要说明：
图1A～G是本发明的方法步骤示意图。
本发明的可使最终成品获得无基板型式的封装形式，其封装方法，大致是如图1A～G所示，首先是在图1A的薄铜片10上经覆盖干膜20与对该未被干膜20遮蔽的位置进行电镀金属的步骤，以供形成如图1B朝上突起的电镀凸点30及各式线路图形(图面上均以凸点表示)，然后进行植入晶片的步骤，此步骤是将数片晶片40以适当间隔距离黏合或结合方式附着于薄铜片10的具有电镀线路的表面上，之后，经如图1C的连线步骤，对各晶片40的各接脚焊接金线41以供连接至相应的电镀凸点30位置，其次，则进行如图1D的灌胶的步骤，此步骤是对各晶片40相应位置予以覆盖保护胶50，以防止晶片遭水份、空气或不当照射侵入，待保护胶50硬化后，即可进行如图1E所示，蚀刻去除前述薄铜片10，而使得前述各电镀凸点30及电镀线路呈外露状，之后，如图1F所示，在不需植入锡球的外露的电镀线路位置涂布绿漆(抗氧化膜)，然后对外露的电镀凸点30进行植入锡球70的步骤，以使得相应于各晶片40底面形成阵列式的锡球接点(亦即形成BGA集成电路包装)，由于在图1F中的相邻晶片40间仍有电镀线路11相互衔接，亦即在最后的步骤中，如图1G所示，再次进行一次蚀刻的步骤，以蚀刻去除前述的电镀线路11并再进行一道涂布绿漆保护的步骤，而使得相邻的晶片完全分离而呈独立的包装形式，如此即完成封装流程。
前述封装方式达了便于说明之故，而以仅附着两个晶片的方式描述，实际上，该封装方式是同时进行数片晶片的同时封装成型，特予陈明。
而在前述封装作业期间，即直接运用为位于薄铜片10做为中间流程的支撑，经灌胶后，即可利用保护胶50提供应有的支撑强度，因此，在后续步骤中，则可直接将薄铜片10蚀刻去除，而形成一种完全不含支撑基板的BGA集成电路包装，此即为本发明具创意及巧思之处，由前述本发明的最终成品(如图1G)来看，其是仅形成有线路及电镀凸点30，相比于传统封装方式，可使外包装更趋轻盈小巧，且对缩小封装厚度有着积极的帮助，故为一具新颖性及进步性的球阵式集成电路封装方法。

Claims (4)

1·一种球阵式集成电路封装方法，其特征在于：包括以下步骤：
a．在铜片上覆干膜与电镀形成线路；
b．对所述线路进行植入晶片；
c．对所述晶片与线路之间进行连线；
d．灌胶覆盖所述晶片；
e．蚀刻去除所述铜片，使所述线路外露；
f．对应于线路的接点位置植入锡球；
g．蚀刻去除位于相邻晶片间的多余线路，以形成个别独立的晶片封装。
2·根据权利要求1所述的球阵式集成电路封装方法，其特征在于：还包括涂布绿漆的步骤，在所述植入锡球的步骤完成后，进行涂布绿漆的步骤，以保护线路部份。
3·根据权利要求1所述的球阵式集成电路封装方法，其特征在于：所述电镀形成的线路为外突的形式。
4·根据权利要求1或2所述的球阵式集成电路封装方法，其特征在于：还包括一个涂布绿漆的步骤，在所述蚀刻去除多余线路的步骤后，再进行涂布绿漆的步骤。
CN97100004A 1997-02-05 1997-02-05 球阵式集成电路封装方法 Expired - Fee Related CN1072393C (zh)

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Publication number Priority date Publication date Assignee Title
CN100446201C (zh) * 2004-09-30 2008-12-24 株式会社瑞萨科技 半导体器件

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CN102136442B (zh) * 2010-01-22 2013-07-10 日月光封装测试(上海)有限公司 半导体封装打线工艺的加热装置及其夹具
CN103560121A (zh) * 2013-08-31 2014-02-05 华天科技（西安）有限公司 一种基于不同尺寸芯片采用植球优化技术的框架csp封装件及其制作工艺

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Publication number Priority date Publication date Assignee Title
JPH08222604A (ja) * 1995-02-15 1996-08-30 Oki Electric Ind Co Ltd 半導体装置の構造およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08222604A (ja) * 1995-02-15 1996-08-30 Oki Electric Ind Co Ltd 半導体装置の構造およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100446201C (zh) * 2004-09-30 2008-12-24 株式会社瑞萨科技 半导体器件

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